sfc: Move and rename Falcon/Siena common NIC operations
Add efx_nic_type operations for the many efx_nic functions that need to be implemented different on EF10. For now, change most of the existing efx_nic_*() functions into inline wrappers. As a later step, we may be able to improve branch prediction for operations used on the fast path by copying the pointers into each queue/channel structure. Move the Falcon/Siena implementations to new file farch.c and rename the functions and static data to use a prefix of 'efx_farch_'. Move efx_may_push_tx_desc() to nic.h, as the EF10 TX code will also use it. Signed-off-by: Ben Hutchings <bhutchings@solarflare.com>
This commit is contained in:
Ben Hutchings
parent
e42c3d85af
commit
86094f7f38
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@ -1,4 +1,5 @@
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sfc-y += efx.o nic.o falcon.o siena.o tx.o rx.o filter.o \
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sfc-y += efx.o nic.o farch.o falcon.o siena.o tx.o rx.o \
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filter.o \
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selftest.o ethtool.o qt202x_phy.o mdio_10g.o \
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tenxpress.o txc43128_phy.o falcon_boards.o \
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mcdi.o mcdi_port.o mcdi_mon.o ptp.o
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@ -1386,7 +1386,7 @@ static void efx_enable_interrupts(struct efx_nic *efx)
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efx->eeh_disabled_legacy_irq = false;
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}
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efx_nic_enable_interrupts(efx);
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efx->type->irq_enable_master(efx);
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efx_for_each_channel(channel, efx) {
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if (channel->type->keep_eventq)
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@ -1407,7 +1407,7 @@ static void efx_disable_interrupts(struct efx_nic *efx)
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efx_fini_eventq(channel);
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}
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efx_nic_disable_interrupts(efx);
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efx->type->irq_disable_non_ev(efx);
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}
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static void efx_remove_interrupts(struct efx_nic *efx)
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@ -346,7 +346,7 @@ static inline void falcon_irq_ack_a1(struct efx_nic *efx)
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}
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irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
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static irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
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{
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struct efx_nic *efx = dev_id;
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efx_oword_t *int_ker = efx->irq_status.addr;
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@ -373,7 +373,7 @@ irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
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/* Check to see if we have a serious error condition */
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syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
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if (unlikely(syserr))
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return efx_nic_fatal_interrupt(efx);
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return efx_farch_fatal_interrupt(efx);
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/* Determine interrupting queues, clear interrupt status
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* register and acknowledge the device interrupt.
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@ -1558,7 +1558,7 @@ static int falcon_test_nvram(struct efx_nic *efx)
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return falcon_read_nvram(efx, NULL);
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}
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static const struct efx_nic_register_test falcon_b0_register_tests[] = {
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static const struct efx_farch_register_test falcon_b0_register_tests[] = {
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{ FR_AZ_ADR_REGION,
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EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
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{ FR_AZ_RX_CFG,
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@ -1618,8 +1618,8 @@ falcon_b0_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
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efx_reset_down(efx, reset_method);
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tests->registers =
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efx_nic_test_registers(efx, falcon_b0_register_tests,
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ARRAY_SIZE(falcon_b0_register_tests))
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efx_farch_test_registers(efx, falcon_b0_register_tests,
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ARRAY_SIZE(falcon_b0_register_tests))
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? -1 : 1;
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rc = falcon_reset_hw(efx, reset_method);
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@ -1984,7 +1984,7 @@ static int falcon_probe_nic(struct efx_nic *efx)
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rc = -ENODEV;
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if (efx_nic_fpga_ver(efx) != 0) {
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if (efx_farch_fpga_ver(efx) != 0) {
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netif_err(efx, probe, efx->net_dev,
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"Falcon FPGA not supported\n");
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goto fail1;
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@ -2218,7 +2218,7 @@ static int falcon_init_nic(struct efx_nic *efx)
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efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
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}
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efx_nic_init_common(efx);
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efx_farch_init_common(efx);
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return 0;
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}
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@ -2367,6 +2367,28 @@ const struct efx_nic_type falcon_a1_nic_type = {
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.set_wol = falcon_set_wol,
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.resume_wol = efx_port_dummy_op_void,
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.test_nvram = falcon_test_nvram,
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.irq_enable_master = efx_farch_irq_enable_master,
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.irq_test_generate = efx_farch_irq_test_generate,
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.irq_disable_non_ev = efx_farch_irq_disable_master,
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.irq_handle_msi = efx_farch_msi_interrupt,
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.irq_handle_legacy = falcon_legacy_interrupt_a1,
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.tx_probe = efx_farch_tx_probe,
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.tx_init = efx_farch_tx_init,
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.tx_remove = efx_farch_tx_remove,
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.tx_write = efx_farch_tx_write,
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.rx_push_indir_table = efx_farch_rx_push_indir_table,
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.rx_probe = efx_farch_rx_probe,
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.rx_init = efx_farch_rx_init,
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.rx_remove = efx_farch_rx_remove,
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.rx_write = efx_farch_rx_write,
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.rx_defer_refill = efx_farch_rx_defer_refill,
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.ev_probe = efx_farch_ev_probe,
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.ev_init = efx_farch_ev_init,
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.ev_fini = efx_farch_ev_fini,
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.ev_remove = efx_farch_ev_remove,
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.ev_process = efx_farch_ev_process,
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.ev_read_ack = efx_farch_ev_read_ack,
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.ev_test_generate = efx_farch_ev_test_generate,
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.revision = EFX_REV_FALCON_A1,
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.mem_map_size = 0x20000,
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@ -2414,6 +2436,28 @@ const struct efx_nic_type falcon_b0_nic_type = {
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.resume_wol = efx_port_dummy_op_void,
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.test_chip = falcon_b0_test_chip,
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.test_nvram = falcon_test_nvram,
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.irq_enable_master = efx_farch_irq_enable_master,
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.irq_test_generate = efx_farch_irq_test_generate,
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.irq_disable_non_ev = efx_farch_irq_disable_master,
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.irq_handle_msi = efx_farch_msi_interrupt,
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.irq_handle_legacy = efx_farch_legacy_interrupt,
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.tx_probe = efx_farch_tx_probe,
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.tx_init = efx_farch_tx_init,
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.tx_remove = efx_farch_tx_remove,
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.tx_write = efx_farch_tx_write,
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.rx_push_indir_table = efx_farch_rx_push_indir_table,
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.rx_probe = efx_farch_rx_probe,
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.rx_init = efx_farch_rx_init,
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.rx_remove = efx_farch_rx_remove,
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.rx_write = efx_farch_rx_write,
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.rx_defer_refill = efx_farch_rx_defer_refill,
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.ev_probe = efx_farch_ev_probe,
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.ev_init = efx_farch_ev_init,
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.ev_fini = efx_farch_ev_fini,
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.ev_remove = efx_farch_ev_remove,
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.ev_process = efx_farch_ev_process,
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.ev_read_ack = efx_farch_ev_read_ack,
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.ev_test_generate = efx_farch_ev_test_generate,
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.revision = EFX_REV_FALCON_B0,
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/* Map everything up to and including the RSS indirection
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File diff suppressed because it is too large
Load Diff
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@ -971,7 +971,7 @@ static inline unsigned int efx_port_num(struct efx_nic *efx)
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* @get_wol: Get WoL configuration from driver state
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* @set_wol: Push WoL configuration to the NIC
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* @resume_wol: Synchronise WoL state between driver and MC (e.g. after resume)
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* @test_chip: Test registers. Should use efx_nic_test_registers(), and is
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* @test_chip: Test registers. May use efx_farch_test_registers(), and is
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* expected to reset the NIC.
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* @test_nvram: Test validity of NVRAM contents
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* @mcdi_request: Send an MCDI request with the given header and SDU.
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@ -985,6 +985,32 @@ static inline unsigned int efx_port_num(struct efx_nic *efx)
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* @mcdi_poll_reboot: Test whether the MCDI has rebooted. If so,
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* return an appropriate error code for aborting any current
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* request; otherwise return 0.
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* @irq_enable_master: Enable IRQs on the NIC. Each event queue must
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* be separately enabled after this.
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* @irq_test_generate: Generate a test IRQ
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* @irq_disable_non_ev: Disable non-event IRQs on the NIC. Each event
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* queue must be separately disabled before this.
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* @irq_handle_msi: Handle MSI for a channel. The @dev_id argument is
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* a pointer to the &struct efx_msi_context for the channel.
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* @irq_handle_legacy: Handle legacy interrupt. The @dev_id argument
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* is a pointer to the &struct efx_nic.
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* @tx_probe: Allocate resources for TX queue
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* @tx_init: Initialise TX queue on the NIC
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* @tx_remove: Free resources for TX queue
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* @tx_write: Write TX descriptors and doorbell
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* @rx_push_indir_table: Write RSS indirection table to the NIC
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* @rx_probe: Allocate resources for RX queue
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* @rx_init: Initialise RX queue on the NIC
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* @rx_remove: Free resources for RX queue
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* @rx_write: Write RX descriptors and doorbell
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* @rx_defer_refill: Generate a refill reminder event
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* @ev_probe: Allocate resources for event queue
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* @ev_init: Initialise event queue on the NIC
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* @ev_fini: Deinitialise event queue on the NIC
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* @ev_remove: Free resources for event queue
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* @ev_process: Process events for a queue, up to the given NAPI quota
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* @ev_read_ack: Acknowledge read events on a queue, rearming its IRQ
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* @ev_test_generate: Generate a test event
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* @revision: Hardware architecture revision
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* @mem_map_size: Memory BAR mapped size
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* @txd_ptr_tbl_base: TX descriptor ring base address
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@ -1041,6 +1067,28 @@ struct efx_nic_type {
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void (*mcdi_read_response)(struct efx_nic *efx, efx_dword_t *pdu,
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size_t pdu_offset, size_t pdu_len);
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int (*mcdi_poll_reboot)(struct efx_nic *efx);
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void (*irq_enable_master)(struct efx_nic *efx);
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void (*irq_test_generate)(struct efx_nic *efx);
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void (*irq_disable_non_ev)(struct efx_nic *efx);
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irqreturn_t (*irq_handle_msi)(int irq, void *dev_id);
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irqreturn_t (*irq_handle_legacy)(int irq, void *dev_id);
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int (*tx_probe)(struct efx_tx_queue *tx_queue);
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void (*tx_init)(struct efx_tx_queue *tx_queue);
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void (*tx_remove)(struct efx_tx_queue *tx_queue);
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void (*tx_write)(struct efx_tx_queue *tx_queue);
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void (*rx_push_indir_table)(struct efx_nic *efx);
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int (*rx_probe)(struct efx_rx_queue *rx_queue);
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void (*rx_init)(struct efx_rx_queue *rx_queue);
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void (*rx_remove)(struct efx_rx_queue *rx_queue);
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void (*rx_write)(struct efx_rx_queue *rx_queue);
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void (*rx_defer_refill)(struct efx_rx_queue *rx_queue);
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int (*ev_probe)(struct efx_channel *channel);
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void (*ev_init)(struct efx_channel *channel);
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void (*ev_fini)(struct efx_channel *channel);
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void (*ev_remove)(struct efx_channel *channel);
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int (*ev_process)(struct efx_channel *channel, int quota);
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void (*ev_read_ack)(struct efx_channel *channel);
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void (*ev_test_generate)(struct efx_channel *channel);
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int revision;
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unsigned int mem_map_size;
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File diff suppressed because it is too large
Load Diff
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@ -34,7 +34,7 @@ static inline int efx_nic_rev(struct efx_nic *efx)
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return efx->type->revision;
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}
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extern u32 efx_nic_fpga_ver(struct efx_nic *efx);
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extern u32 efx_farch_fpga_ver(struct efx_nic *efx);
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/* NIC has two interlinked PCI functions for the same port. */
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static inline bool efx_nic_is_dual_func(struct efx_nic *efx)
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@ -42,6 +42,65 @@ static inline bool efx_nic_is_dual_func(struct efx_nic *efx)
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return efx_nic_rev(efx) < EFX_REV_FALCON_B0;
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}
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/* Read the current event from the event queue */
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static inline efx_qword_t *efx_event(struct efx_channel *channel,
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unsigned int index)
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{
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return ((efx_qword_t *) (channel->eventq.buf.addr)) +
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(index & channel->eventq_mask);
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}
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/* See if an event is present
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*
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* We check both the high and low dword of the event for all ones. We
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* wrote all ones when we cleared the event, and no valid event can
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* have all ones in either its high or low dwords. This approach is
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* robust against reordering.
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*
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* Note that using a single 64-bit comparison is incorrect; even
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* though the CPU read will be atomic, the DMA write may not be.
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*/
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static inline int efx_event_present(efx_qword_t *event)
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{
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return !(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
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EFX_DWORD_IS_ALL_ONES(event->dword[1]));
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}
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/* Returns a pointer to the specified transmit descriptor in the TX
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* descriptor queue belonging to the specified channel.
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*/
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static inline efx_qword_t *
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efx_tx_desc(struct efx_tx_queue *tx_queue, unsigned int index)
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{
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return ((efx_qword_t *) (tx_queue->txd.buf.addr)) + index;
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}
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/* Decide whether to push a TX descriptor to the NIC vs merely writing
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* the doorbell. This can reduce latency when we are adding a single
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* descriptor to an empty queue, but is otherwise pointless. Further,
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* Falcon and Siena have hardware bugs (SF bug 33851) that may be
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* triggered if we don't check this.
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*/
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static inline bool efx_nic_may_push_tx_desc(struct efx_tx_queue *tx_queue,
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unsigned int write_count)
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{
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unsigned empty_read_count = ACCESS_ONCE(tx_queue->empty_read_count);
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if (empty_read_count == 0)
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return false;
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tx_queue->empty_read_count = 0;
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return ((empty_read_count ^ write_count) & ~EFX_EMPTY_COUNT_VALID) == 0
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&& tx_queue->write_count - write_count == 1;
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}
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/* Returns a pointer to the specified descriptor in the RX descriptor queue */
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static inline efx_qword_t *
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efx_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
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{
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return ((efx_qword_t *) (rx_queue->rxd.buf.addr)) + index;
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}
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enum {
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PHY_TYPE_NONE = 0,
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PHY_TYPE_TXC43128 = 1,
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@ -258,25 +317,93 @@ extern const struct efx_nic_type siena_a0_nic_type;
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extern int falcon_probe_board(struct efx_nic *efx, u16 revision_info);
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/* TX data path */
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extern int efx_nic_probe_tx(struct efx_tx_queue *tx_queue);
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extern void efx_nic_init_tx(struct efx_tx_queue *tx_queue);
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extern void efx_nic_remove_tx(struct efx_tx_queue *tx_queue);
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extern void efx_nic_push_buffers(struct efx_tx_queue *tx_queue);
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static inline int efx_nic_probe_tx(struct efx_tx_queue *tx_queue)
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{
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return tx_queue->efx->type->tx_probe(tx_queue);
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}
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static inline void efx_nic_init_tx(struct efx_tx_queue *tx_queue)
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{
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tx_queue->efx->type->tx_init(tx_queue);
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}
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static inline void efx_nic_remove_tx(struct efx_tx_queue *tx_queue)
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{
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tx_queue->efx->type->tx_remove(tx_queue);
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}
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static inline void efx_nic_push_buffers(struct efx_tx_queue *tx_queue)
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{
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tx_queue->efx->type->tx_write(tx_queue);
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}
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/* RX data path */
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extern int efx_nic_probe_rx(struct efx_rx_queue *rx_queue);
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extern void efx_nic_init_rx(struct efx_rx_queue *rx_queue);
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extern void efx_nic_remove_rx(struct efx_rx_queue *rx_queue);
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extern void efx_nic_notify_rx_desc(struct efx_rx_queue *rx_queue);
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extern void efx_nic_generate_fill_event(struct efx_rx_queue *rx_queue);
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static inline int efx_nic_probe_rx(struct efx_rx_queue *rx_queue)
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{
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return rx_queue->efx->type->rx_probe(rx_queue);
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}
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static inline void efx_nic_init_rx(struct efx_rx_queue *rx_queue)
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{
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rx_queue->efx->type->rx_init(rx_queue);
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}
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static inline void efx_nic_remove_rx(struct efx_rx_queue *rx_queue)
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{
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rx_queue->efx->type->rx_remove(rx_queue);
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}
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static inline void efx_nic_notify_rx_desc(struct efx_rx_queue *rx_queue)
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{
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rx_queue->efx->type->rx_write(rx_queue);
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}
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static inline void efx_nic_generate_fill_event(struct efx_rx_queue *rx_queue)
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{
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rx_queue->efx->type->rx_defer_refill(rx_queue);
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}
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/* Event data path */
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extern int efx_nic_probe_eventq(struct efx_channel *channel);
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extern void efx_nic_init_eventq(struct efx_channel *channel);
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extern void efx_nic_fini_eventq(struct efx_channel *channel);
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extern void efx_nic_remove_eventq(struct efx_channel *channel);
|
||||
extern int efx_nic_process_eventq(struct efx_channel *channel, int rx_quota);
|
||||
extern void efx_nic_eventq_read_ack(struct efx_channel *channel);
|
||||
static inline int efx_nic_probe_eventq(struct efx_channel *channel)
|
||||
{
|
||||
return channel->efx->type->ev_probe(channel);
|
||||
}
|
||||
static inline void efx_nic_init_eventq(struct efx_channel *channel)
|
||||
{
|
||||
channel->efx->type->ev_init(channel);
|
||||
}
|
||||
static inline void efx_nic_fini_eventq(struct efx_channel *channel)
|
||||
{
|
||||
channel->efx->type->ev_fini(channel);
|
||||
}
|
||||
static inline void efx_nic_remove_eventq(struct efx_channel *channel)
|
||||
{
|
||||
channel->efx->type->ev_remove(channel);
|
||||
}
|
||||
static inline int
|
||||
efx_nic_process_eventq(struct efx_channel *channel, int quota)
|
||||
{
|
||||
return channel->efx->type->ev_process(channel, quota);
|
||||
}
|
||||
static inline void efx_nic_eventq_read_ack(struct efx_channel *channel)
|
||||
{
|
||||
channel->efx->type->ev_read_ack(channel);
|
||||
}
|
||||
extern void efx_nic_event_test_start(struct efx_channel *channel);
|
||||
|
||||
/* Falcon/Siena queue operations */
|
||||
extern int efx_farch_tx_probe(struct efx_tx_queue *tx_queue);
|
||||
extern void efx_farch_tx_init(struct efx_tx_queue *tx_queue);
|
||||
extern void efx_farch_tx_fini(struct efx_tx_queue *tx_queue);
|
||||
extern void efx_farch_tx_remove(struct efx_tx_queue *tx_queue);
|
||||
extern void efx_farch_tx_write(struct efx_tx_queue *tx_queue);
|
||||
extern int efx_farch_rx_probe(struct efx_rx_queue *rx_queue);
|
||||
extern void efx_farch_rx_init(struct efx_rx_queue *rx_queue);
|
||||
extern void efx_farch_rx_fini(struct efx_rx_queue *rx_queue);
|
||||
extern void efx_farch_rx_remove(struct efx_rx_queue *rx_queue);
|
||||
extern void efx_farch_rx_write(struct efx_rx_queue *rx_queue);
|
||||
extern void efx_farch_rx_defer_refill(struct efx_rx_queue *rx_queue);
|
||||
extern int efx_farch_ev_probe(struct efx_channel *channel);
|
||||
extern void efx_farch_ev_init(struct efx_channel *channel);
|
||||
extern void efx_farch_ev_fini(struct efx_channel *channel);
|
||||
extern void efx_farch_ev_remove(struct efx_channel *channel);
|
||||
extern int efx_farch_ev_process(struct efx_channel *channel, int quota);
|
||||
extern void efx_farch_ev_read_ack(struct efx_channel *channel);
|
||||
extern void efx_farch_ev_test_generate(struct efx_channel *channel);
|
||||
|
||||
extern bool efx_nic_event_present(struct efx_channel *channel);
|
||||
|
||||
/* Some statistics are computed as A - B where A and B each increase
|
||||
|
|
@ -297,15 +424,18 @@ static inline void efx_update_diff_stat(u64 *stat, u64 diff)
|
|||
*stat = diff;
|
||||
}
|
||||
|
||||
/* Interrupts and test events */
|
||||
/* Interrupts */
|
||||
extern int efx_nic_init_interrupt(struct efx_nic *efx);
|
||||
extern void efx_nic_enable_interrupts(struct efx_nic *efx);
|
||||
extern void efx_nic_event_test_start(struct efx_channel *channel);
|
||||
extern void efx_nic_irq_test_start(struct efx_nic *efx);
|
||||
extern void efx_nic_disable_interrupts(struct efx_nic *efx);
|
||||
extern void efx_nic_fini_interrupt(struct efx_nic *efx);
|
||||
extern irqreturn_t efx_nic_fatal_interrupt(struct efx_nic *efx);
|
||||
extern irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id);
|
||||
|
||||
/* Falcon/Siena interrupts */
|
||||
extern void efx_farch_irq_enable_master(struct efx_nic *efx);
|
||||
extern void efx_farch_irq_test_generate(struct efx_nic *efx);
|
||||
extern void efx_farch_irq_disable_master(struct efx_nic *efx);
|
||||
extern irqreturn_t efx_farch_msi_interrupt(int irq, void *dev_id);
|
||||
extern irqreturn_t efx_farch_legacy_interrupt(int irq, void *dev_id);
|
||||
extern irqreturn_t efx_farch_fatal_interrupt(struct efx_nic *efx);
|
||||
|
||||
static inline int efx_nic_event_test_irq_cpu(struct efx_channel *channel)
|
||||
{
|
||||
|
|
@ -317,36 +447,40 @@ static inline int efx_nic_irq_test_irq_cpu(struct efx_nic *efx)
|
|||
}
|
||||
|
||||
/* Global Resources */
|
||||
extern int efx_farch_fini_dmaq(struct efx_nic *efx);
|
||||
extern int efx_nic_flush_queues(struct efx_nic *efx);
|
||||
extern void siena_prepare_flush(struct efx_nic *efx);
|
||||
extern int efx_farch_fini_dmaq(struct efx_nic *efx);
|
||||
extern void siena_finish_flush(struct efx_nic *efx);
|
||||
extern void falcon_start_nic_stats(struct efx_nic *efx);
|
||||
extern void falcon_stop_nic_stats(struct efx_nic *efx);
|
||||
extern int falcon_reset_xaui(struct efx_nic *efx);
|
||||
extern void
|
||||
efx_nic_dimension_resources(struct efx_nic *efx, unsigned sram_lim_qw);
|
||||
extern void efx_nic_init_common(struct efx_nic *efx);
|
||||
extern void efx_nic_push_rx_indir_table(struct efx_nic *efx);
|
||||
extern void efx_farch_dimension_resources(struct efx_nic *efx, unsigned sram_lim_qw);
|
||||
extern void efx_farch_init_common(struct efx_nic *efx);
|
||||
static inline void efx_nic_push_rx_indir_table(struct efx_nic *efx)
|
||||
{
|
||||
efx->type->rx_push_indir_table(efx);
|
||||
}
|
||||
extern void efx_farch_rx_push_indir_table(struct efx_nic *efx);
|
||||
|
||||
int efx_nic_alloc_buffer(struct efx_nic *efx, struct efx_buffer *buffer,
|
||||
unsigned int len, gfp_t gfp_flags);
|
||||
void efx_nic_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer);
|
||||
|
||||
/* Tests */
|
||||
struct efx_nic_register_test {
|
||||
struct efx_farch_register_test {
|
||||
unsigned address;
|
||||
efx_oword_t mask;
|
||||
};
|
||||
extern int efx_nic_test_registers(struct efx_nic *efx,
|
||||
const struct efx_nic_register_test *regs,
|
||||
size_t n_regs);
|
||||
extern int efx_farch_test_registers(struct efx_nic *efx,
|
||||
const struct efx_farch_register_test *regs,
|
||||
size_t n_regs);
|
||||
|
||||
extern size_t efx_nic_get_regs_len(struct efx_nic *efx);
|
||||
extern void efx_nic_get_regs(struct efx_nic *efx, void *buf);
|
||||
|
||||
#define EFX_MAX_FLUSH_TIME 5000
|
||||
|
||||
extern void efx_generate_event(struct efx_nic *efx, unsigned int evq,
|
||||
efx_qword_t *event);
|
||||
extern void efx_farch_generate_event(struct efx_nic *efx, unsigned int evq,
|
||||
efx_qword_t *event);
|
||||
|
||||
#endif /* EFX_NIC_H */
|
||||
|
|
|
|||
|
|
@ -63,7 +63,7 @@ void siena_finish_flush(struct efx_nic *efx)
|
|||
efx_mcdi_set_mac(efx);
|
||||
}
|
||||
|
||||
static const struct efx_nic_register_test siena_register_tests[] = {
|
||||
static const struct efx_farch_register_test siena_register_tests[] = {
|
||||
{ FR_AZ_ADR_REGION,
|
||||
EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
|
||||
{ FR_CZ_USR_EV_CFG,
|
||||
|
|
@ -107,8 +107,8 @@ static int siena_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
|
|||
goto out;
|
||||
|
||||
tests->registers =
|
||||
efx_nic_test_registers(efx, siena_register_tests,
|
||||
ARRAY_SIZE(siena_register_tests))
|
||||
efx_farch_test_registers(efx, siena_register_tests,
|
||||
ARRAY_SIZE(siena_register_tests))
|
||||
? -1 : 1;
|
||||
|
||||
rc = efx_mcdi_reset(efx, reset_method);
|
||||
|
|
@ -184,7 +184,7 @@ static void siena_dimension_resources(struct efx_nic *efx)
|
|||
* the buffer table and descriptor caches. In theory we can
|
||||
* map both blocks to one port, but we don't.
|
||||
*/
|
||||
efx_nic_dimension_resources(efx, FR_CZ_BUF_FULL_TBL_ROWS / 2);
|
||||
efx_farch_dimension_resources(efx, FR_CZ_BUF_FULL_TBL_ROWS / 2);
|
||||
}
|
||||
|
||||
static int siena_probe_nic(struct efx_nic *efx)
|
||||
|
|
@ -200,7 +200,7 @@ static int siena_probe_nic(struct efx_nic *efx)
|
|||
return -ENOMEM;
|
||||
efx->nic_data = nic_data;
|
||||
|
||||
if (efx_nic_fpga_ver(efx) != 0) {
|
||||
if (efx_farch_fpga_ver(efx) != 0) {
|
||||
netif_err(efx, probe, efx->net_dev,
|
||||
"Siena FPGA not supported\n");
|
||||
rc = -ENODEV;
|
||||
|
|
@ -351,7 +351,7 @@ static int siena_init_nic(struct efx_nic *efx)
|
|||
EFX_POPULATE_OWORD_1(temp, FRF_CZ_USREV_DIS, 1);
|
||||
efx_writeo(efx, &temp, FR_CZ_USR_EV_CFG);
|
||||
|
||||
efx_nic_init_common(efx);
|
||||
efx_farch_init_common(efx);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -705,6 +705,28 @@ const struct efx_nic_type siena_a0_nic_type = {
|
|||
.mcdi_poll_response = siena_mcdi_poll_response,
|
||||
.mcdi_read_response = siena_mcdi_read_response,
|
||||
.mcdi_poll_reboot = siena_mcdi_poll_reboot,
|
||||
.irq_enable_master = efx_farch_irq_enable_master,
|
||||
.irq_test_generate = efx_farch_irq_test_generate,
|
||||
.irq_disable_non_ev = efx_farch_irq_disable_master,
|
||||
.irq_handle_msi = efx_farch_msi_interrupt,
|
||||
.irq_handle_legacy = efx_farch_legacy_interrupt,
|
||||
.tx_probe = efx_farch_tx_probe,
|
||||
.tx_init = efx_farch_tx_init,
|
||||
.tx_remove = efx_farch_tx_remove,
|
||||
.tx_write = efx_farch_tx_write,
|
||||
.rx_push_indir_table = efx_farch_rx_push_indir_table,
|
||||
.rx_probe = efx_farch_rx_probe,
|
||||
.rx_init = efx_farch_rx_init,
|
||||
.rx_remove = efx_farch_rx_remove,
|
||||
.rx_write = efx_farch_rx_write,
|
||||
.rx_defer_refill = efx_farch_rx_defer_refill,
|
||||
.ev_probe = efx_farch_ev_probe,
|
||||
.ev_init = efx_farch_ev_init,
|
||||
.ev_fini = efx_farch_ev_fini,
|
||||
.ev_remove = efx_farch_ev_remove,
|
||||
.ev_process = efx_farch_ev_process,
|
||||
.ev_read_ack = efx_farch_ev_read_ack,
|
||||
.ev_test_generate = efx_farch_ev_test_generate,
|
||||
|
||||
.revision = EFX_REV_SIENA_A0,
|
||||
.mem_map_size = (FR_CZ_MC_TREG_SMEM +
|
||||
|
|
|
|||
|
|
@ -464,8 +464,9 @@ static void __efx_sriov_push_vf_status(struct efx_vf *vf)
|
|||
VFDI_EV_SEQ, (vf->msg_seqno & 0xff),
|
||||
VFDI_EV_TYPE, VFDI_EV_TYPE_STATUS);
|
||||
++vf->msg_seqno;
|
||||
efx_generate_event(efx, EFX_VI_BASE + vf->index * efx_vf_size(efx),
|
||||
&event);
|
||||
efx_farch_generate_event(efx,
|
||||
EFX_VI_BASE + vf->index * efx_vf_size(efx),
|
||||
&event);
|
||||
}
|
||||
|
||||
static void efx_sriov_bufs(struct efx_nic *efx, unsigned offset,
|
||||
|
|
|
|||
Loading…
Reference in New Issue