hpt366: merge set_dma_mode() methods
Group the array of pointers to the timing tables with the timing register masks which allows us to merge HPT36x/HPT37x set_dma_mode() methods into one. Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
This commit is contained in:
Sergei Shtylyov
Bartlomiej Zolnierkiewicz
parent
a488f34e0d
commit
866664d79f
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@ -1,5 +1,5 @@
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/*
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* linux/drivers/ide/pci/hpt366.c Version 1.24 Dec 8, 2007
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* linux/drivers/ide/pci/hpt366.c Version 1.30 Dec 12, 2007
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*
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* Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
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* Portions Copyright (C) 2001 Sun Microsystems, Inc.
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@ -88,7 +88,7 @@
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* - rename all the register related variables consistently
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* - move all the interrupt twiddling code from the speedproc handlers into
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* init_hwif_hpt366(), also grouping all the DMA related code together there
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* - merge two HPT37x speedproc handlers, fix the PIO timing register mask and
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* - merge HPT36x/HPT37x speedproc handlers, fix PIO timing register mask and
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* separate the UltraDMA and MWDMA masks there to avoid changing PIO timings
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* when setting an UltraDMA mode
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* - fix hpt3xx_tune_drive() to set the PIO mode requested, not always select
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@ -458,6 +458,13 @@ enum ata_clock {
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NUM_ATA_CLOCKS
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};
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struct hpt_timings {
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u32 pio_mask;
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u32 dma_mask;
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u32 ultra_mask;
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u32 *clock_table[NUM_ATA_CLOCKS];
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};
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/*
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* Hold all the HighPoint chip information in one place.
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*/
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@ -468,7 +475,8 @@ struct hpt_info {
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u8 udma_mask; /* Allowed UltraDMA modes mask. */
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u8 dpll_clk; /* DPLL clock in MHz */
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u8 pci_clk; /* PCI clock in MHz */
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u32 **settings; /* Chipset settings table */
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struct hpt_timings *timings; /* Chipset timing data */
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u8 clock; /* ATA clock selected */
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};
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/* Supported HighPoint chips */
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@ -486,20 +494,30 @@ enum {
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HPT371N
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};
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static u32 *hpt36x_settings[NUM_ATA_CLOCKS] = {
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twenty_five_base_hpt36x,
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thirty_three_base_hpt36x,
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forty_base_hpt36x,
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NULL,
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NULL
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static struct hpt_timings hpt36x_timings = {
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.pio_mask = 0xc1f8ffff,
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.dma_mask = 0x303800ff,
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.ultra_mask = 0x30070000,
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.clock_table = {
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[ATA_CLOCK_25MHZ] = twenty_five_base_hpt36x,
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[ATA_CLOCK_33MHZ] = thirty_three_base_hpt36x,
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[ATA_CLOCK_40MHZ] = forty_base_hpt36x,
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[ATA_CLOCK_50MHZ] = NULL,
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[ATA_CLOCK_66MHZ] = NULL
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}
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};
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static u32 *hpt37x_settings[NUM_ATA_CLOCKS] = {
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NULL,
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thirty_three_base_hpt37x,
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NULL,
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fifty_base_hpt37x,
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sixty_six_base_hpt37x
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static struct hpt_timings hpt37x_timings = {
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.pio_mask = 0xcfc3ffff,
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.dma_mask = 0x31c001ff,
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.ultra_mask = 0x303c0000,
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.clock_table = {
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[ATA_CLOCK_25MHZ] = NULL,
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[ATA_CLOCK_33MHZ] = thirty_three_base_hpt37x,
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[ATA_CLOCK_40MHZ] = NULL,
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[ATA_CLOCK_50MHZ] = fifty_base_hpt37x,
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[ATA_CLOCK_66MHZ] = sixty_six_base_hpt37x
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}
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};
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static const struct hpt_info hpt36x __devinitdata = {
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@ -507,7 +525,7 @@ static const struct hpt_info hpt36x __devinitdata = {
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.chip_type = HPT36x,
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.udma_mask = HPT366_ALLOW_ATA66_3 ? (HPT366_ALLOW_ATA66_4 ? ATA_UDMA4 : ATA_UDMA3) : ATA_UDMA2,
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.dpll_clk = 0, /* no DPLL */
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.settings = hpt36x_settings
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.timings = &hpt36x_timings
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};
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static const struct hpt_info hpt370 __devinitdata = {
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@ -515,7 +533,7 @@ static const struct hpt_info hpt370 __devinitdata = {
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.chip_type = HPT370,
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.udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4,
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.dpll_clk = 48,
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.settings = hpt37x_settings
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.timings = &hpt37x_timings
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};
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static const struct hpt_info hpt370a __devinitdata = {
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@ -523,7 +541,7 @@ static const struct hpt_info hpt370a __devinitdata = {
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.chip_type = HPT370A,
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.udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4,
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.dpll_clk = 48,
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.settings = hpt37x_settings
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.timings = &hpt37x_timings
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};
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static const struct hpt_info hpt374 __devinitdata = {
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@ -531,7 +549,7 @@ static const struct hpt_info hpt374 __devinitdata = {
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.chip_type = HPT374,
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.udma_mask = ATA_UDMA5,
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.dpll_clk = 48,
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.settings = hpt37x_settings
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.timings = &hpt37x_timings
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};
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static const struct hpt_info hpt372 __devinitdata = {
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@ -539,7 +557,7 @@ static const struct hpt_info hpt372 __devinitdata = {
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.chip_type = HPT372,
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.udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
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.dpll_clk = 55,
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.settings = hpt37x_settings
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.timings = &hpt37x_timings
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};
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static const struct hpt_info hpt372a __devinitdata = {
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@ -547,7 +565,7 @@ static const struct hpt_info hpt372a __devinitdata = {
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.chip_type = HPT372A,
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.udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
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.dpll_clk = 66,
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.settings = hpt37x_settings
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.timings = &hpt37x_timings
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};
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static const struct hpt_info hpt302 __devinitdata = {
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@ -555,7 +573,7 @@ static const struct hpt_info hpt302 __devinitdata = {
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.chip_type = HPT302,
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.udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
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.dpll_clk = 66,
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.settings = hpt37x_settings
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.timings = &hpt37x_timings
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};
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static const struct hpt_info hpt371 __devinitdata = {
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@ -563,7 +581,7 @@ static const struct hpt_info hpt371 __devinitdata = {
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.chip_type = HPT371,
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.udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
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.dpll_clk = 66,
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.settings = hpt37x_settings
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.timings = &hpt37x_timings
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};
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static const struct hpt_info hpt372n __devinitdata = {
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@ -571,7 +589,7 @@ static const struct hpt_info hpt372n __devinitdata = {
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.chip_type = HPT372N,
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.udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
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.dpll_clk = 77,
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.settings = hpt37x_settings
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.timings = &hpt37x_timings
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};
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static const struct hpt_info hpt302n __devinitdata = {
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@ -579,7 +597,7 @@ static const struct hpt_info hpt302n __devinitdata = {
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.chip_type = HPT302N,
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.udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
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.dpll_clk = 77,
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.settings = hpt37x_settings
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.timings = &hpt37x_timings
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};
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static const struct hpt_info hpt371n __devinitdata = {
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@ -587,7 +605,7 @@ static const struct hpt_info hpt371n __devinitdata = {
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.chip_type = HPT371N,
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.udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
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.dpll_clk = 77,
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.settings = hpt37x_settings
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.timings = &hpt37x_timings
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};
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static int check_in_drive_list(ide_drive_t *drive, const char **list)
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@ -675,24 +693,21 @@ static u32 get_speed_setting(u8 speed, struct hpt_info *info)
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for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++)
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if (xfer_speeds[i] == speed)
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break;
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/*
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* NOTE: info->settings only points to the pointer
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* to the list of the actual register values
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*/
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return (*info->settings)[i];
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return info->timings->clock_table[info->clock][i];
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}
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static void hpt36x_set_mode(ide_drive_t *drive, const u8 speed)
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static void hpt3xx_set_mode(ide_drive_t *drive, const u8 speed)
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{
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ide_hwif_t *hwif = HWIF(drive);
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struct pci_dev *dev = hwif->pci_dev;
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struct pci_dev *dev = HWIF(drive)->pci_dev;
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struct hpt_info *info = pci_get_drvdata(dev);
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u8 itr_addr = drive->dn ? 0x44 : 0x40;
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struct hpt_timings *t = info->timings;
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u8 itr_addr = 0x40 + (drive->dn * 4);
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u32 old_itr = 0;
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u32 new_itr = get_speed_setting(speed, info);
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u32 itr_mask = speed < XFER_MW_DMA_0 ? 0xc1f8ffff :
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(speed < XFER_UDMA_0 ? 0x303800ff :
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0x30070000);
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u32 itr_mask = speed < XFER_MW_DMA_0 ? t->pio_mask :
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(speed < XFER_UDMA_0 ? t->dma_mask :
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t->ultra_mask);
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pci_read_config_dword(dev, itr_addr, &old_itr);
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new_itr = (old_itr & ~itr_mask) | (new_itr & itr_mask);
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@ -705,29 +720,9 @@ static void hpt36x_set_mode(ide_drive_t *drive, const u8 speed)
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pci_write_config_dword(dev, itr_addr, new_itr);
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}
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static void hpt37x_set_mode(ide_drive_t *drive, const u8 speed)
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{
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ide_hwif_t *hwif = HWIF(drive);
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struct pci_dev *dev = hwif->pci_dev;
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struct hpt_info *info = pci_get_drvdata(dev);
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u8 itr_addr = 0x40 + (drive->dn * 4);
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u32 old_itr = 0;
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u32 new_itr = get_speed_setting(speed, info);
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u32 itr_mask = speed < XFER_MW_DMA_0 ? 0xcfc3ffff :
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(speed < XFER_UDMA_0 ? 0x31c001ff :
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0x303c0000);
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pci_read_config_dword(dev, itr_addr, &old_itr);
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new_itr = (old_itr & ~itr_mask) | (new_itr & itr_mask);
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if (speed < XFER_MW_DMA_0)
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new_itr &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
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pci_write_config_dword(dev, itr_addr, new_itr);
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}
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static void hpt3xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
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{
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HWIF(drive)->set_dma_mode(drive, XFER_PIO_0 + pio);
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hpt3xx_set_mode(drive, XFER_PIO_0 + pio);
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}
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static int hpt3xx_quirkproc(ide_drive_t *drive)
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@ -1195,7 +1190,7 @@ static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const cha
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* We also don't like using the DPLL because this causes glitches
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* on PRST-/SRST- when the state engine gets reset...
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*/
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if (chip_type >= HPT374 || info->settings[clock] == NULL) {
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if (chip_type >= HPT374 || info->timings->clock_table[clock] == NULL) {
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u16 f_low, delta = pci_clk < 50 ? 2 : 4;
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int adjust;
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@ -1211,7 +1206,7 @@ static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const cha
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clock = ATA_CLOCK_50MHZ;
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}
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if (info->settings[clock] == NULL) {
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if (info->timings->clock_table[clock] == NULL) {
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printk(KERN_ERR "%s: unknown bus timing!\n", name);
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kfree(info);
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return -EIO;
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@ -1252,15 +1247,10 @@ static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const cha
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printk("%s: using %d MHz PCI clock\n", name, pci_clk);
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}
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/*
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* Advance the table pointer to a slot which points to the list
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* of the register values settings matching the clock being used.
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*/
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info->settings += clock;
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/* Store the clock frequencies. */
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info->dpll_clk = dpll_clk;
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info->pci_clk = pci_clk;
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info->clock = clock;
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/* Point to this chip's own instance of the hpt_info structure. */
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pci_set_drvdata(dev, info);
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@ -1304,10 +1294,7 @@ static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
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hwif->select_data = hwif->channel ? 0x54 : 0x50;
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hwif->set_pio_mode = &hpt3xx_set_pio_mode;
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if (chip_type >= HPT370)
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hwif->set_dma_mode = &hpt37x_set_mode;
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else
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hwif->set_dma_mode = &hpt36x_set_mode;
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hwif->set_dma_mode = &hpt3xx_set_mode;
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hwif->quirkproc = &hpt3xx_quirkproc;
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hwif->intrproc = &hpt3xx_intrproc;
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