From ce427c384ea4b7ec48c7e6367b7b64457eba87b3 Mon Sep 17 00:00:00 2001 From: David Brown Date: Thu, 12 May 2011 00:33:38 -0700 Subject: [PATCH 1/8] msm: gpio: Remove unsupported devices The MSM7x25 and MSM7x27 devices are not yet supported in the kernel. Remove #ifdef-based tables supporting these chips for now. Change-Id: I4d9f5abc4cc0942ce75a067097b072489493c1b8 Signed-off-by: David Brown Acked-by: Linus Walleij Acked-by: Nicolas Pitre --- arch/arm/mach-msm/gpio.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/arch/arm/mach-msm/gpio.c b/arch/arm/mach-msm/gpio.c index 5ea273b00da8..c358cedcda97 100644 --- a/arch/arm/mach-msm/gpio.c +++ b/arch/arm/mach-msm/gpio.c @@ -197,13 +197,6 @@ struct msm_gpio_chip msm_gpio_chips[] = { MSM_GPIO_BANK(3, 68, 94), MSM_GPIO_BANK(4, 95, 106), MSM_GPIO_BANK(5, 107, 121), -#elif defined(CONFIG_ARCH_MSM7X25) || defined(CONFIG_ARCH_MSM7X27) - MSM_GPIO_BANK(0, 0, 15), - MSM_GPIO_BANK(1, 16, 42), - MSM_GPIO_BANK(2, 43, 67), - MSM_GPIO_BANK(3, 68, 94), - MSM_GPIO_BANK(4, 95, 106), - MSM_GPIO_BANK(5, 107, 132), #elif defined(CONFIG_ARCH_MSM7X30) MSM_GPIO_BANK(0, 0, 15), MSM_GPIO_BANK(1, 16, 43), From 03db0729b7603202f7d3a2bf2ec7e89a1ad44a17 Mon Sep 17 00:00:00 2001 From: David Brown Date: Thu, 12 May 2011 00:54:36 -0700 Subject: [PATCH 2/8] msm: Remove chip-ifdefs for GPIO io mappings The two GPIO controllers are always mapped to the same virtual address across all MSM devices. Instead of selecting this at compile time, determine the physical address at runtime, eliminating yet something else preventing multiple MSM targets from being compiled into the same kernel. Change-Id: I1672219d978ab6243526adeda6badf49472baa27 Signed-off-by: David Brown Acked-by: Linus Walleij Acked-by: Nicolas Pitre --- arch/arm/mach-msm/include/mach/msm_iomap-7x00.h | 10 ++++------ arch/arm/mach-msm/include/mach/msm_iomap-7x30.h | 10 ++++------ arch/arm/mach-msm/include/mach/msm_iomap-8x50.h | 10 ++++------ arch/arm/mach-msm/include/mach/msm_iomap.h | 2 ++ arch/arm/mach-msm/io.c | 12 ++++++------ 5 files changed, 20 insertions(+), 24 deletions(-) diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h index 8f99d97615a0..94fe9fe6feb3 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h @@ -55,13 +55,11 @@ #define MSM_DMOV_PHYS 0xA9700000 #define MSM_DMOV_SIZE SZ_4K -#define MSM_GPIO1_BASE IOMEM(0xE0003000) -#define MSM_GPIO1_PHYS 0xA9200000 -#define MSM_GPIO1_SIZE SZ_4K +#define MSM7X00_GPIO1_PHYS 0xA9200000 +#define MSM7X00_GPIO1_SIZE SZ_4K -#define MSM_GPIO2_BASE IOMEM(0xE0004000) -#define MSM_GPIO2_PHYS 0xA9300000 -#define MSM_GPIO2_SIZE SZ_4K +#define MSM7X00_GPIO2_PHYS 0xA9300000 +#define MSM7X00_GPIO2_SIZE SZ_4K #define MSM_CLK_CTL_BASE IOMEM(0xE0005000) #define MSM_CLK_CTL_PHYS 0xA8600000 diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h index 4d84be15955e..37694442d1bd 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h @@ -46,13 +46,11 @@ #define MSM_DMOV_PHYS 0xAC400000 #define MSM_DMOV_SIZE SZ_4K -#define MSM_GPIO1_BASE IOMEM(0xE0003000) -#define MSM_GPIO1_PHYS 0xAC001000 -#define MSM_GPIO1_SIZE SZ_4K +#define MSM7X30_GPIO1_PHYS 0xAC001000 +#define MSM7X30_GPIO1_SIZE SZ_4K -#define MSM_GPIO2_BASE IOMEM(0xE0004000) -#define MSM_GPIO2_PHYS 0xAC101000 -#define MSM_GPIO2_SIZE SZ_4K +#define MSM7X30_GPIO2_PHYS 0xAC101000 +#define MSM7X30_GPIO2_SIZE SZ_4K #define MSM_CLK_CTL_BASE IOMEM(0xE0005000) #define MSM_CLK_CTL_PHYS 0xAB800000 diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h index d4143201999f..d67cd73316f4 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h @@ -46,13 +46,11 @@ #define MSM_DMOV_PHYS 0xA9700000 #define MSM_DMOV_SIZE SZ_4K -#define MSM_GPIO1_BASE IOMEM(0xE0003000) -#define MSM_GPIO1_PHYS 0xA9000000 -#define MSM_GPIO1_SIZE SZ_4K +#define QSD8X50_GPIO1_PHYS 0xA9000000 +#define QSD8X50_GPIO1_SIZE SZ_4K -#define MSM_GPIO2_BASE IOMEM(0xE0004000) -#define MSM_GPIO2_PHYS 0xA9100000 -#define MSM_GPIO2_SIZE SZ_4K +#define QSD8X50_GPIO2_PHYS 0xA9100000 +#define QSD8X50_GPIO2_SIZE SZ_4K #define MSM_CLK_CTL_BASE IOMEM(0xE0005000) #define MSM_CLK_CTL_PHYS 0xA8600000 diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h index 2f494b6a9d0a..4ded15238b60 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap.h @@ -61,5 +61,7 @@ #define MSM_QGIC_CPU_BASE IOMEM(0xF0001000) #define MSM_TMR_BASE IOMEM(0xF0200000) #define MSM_TMR0_BASE IOMEM(0xF0201000) +#define MSM_GPIO1_BASE IOMEM(0xE0003000) +#define MSM_GPIO2_BASE IOMEM(0xE0004000) #endif diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c index cec6ed1c91d3..140ddbbc3a8a 100644 --- a/arch/arm/mach-msm/io.c +++ b/arch/arm/mach-msm/io.c @@ -43,8 +43,8 @@ static struct map_desc msm_io_desc[] __initdata = { MSM_DEVICE(VIC), MSM_CHIP_DEVICE(CSR, MSM7X00), MSM_DEVICE(DMOV), - MSM_DEVICE(GPIO1), - MSM_DEVICE(GPIO2), + MSM_CHIP_DEVICE(GPIO1, MSM7X00), + MSM_CHIP_DEVICE(GPIO2, MSM7X00), MSM_DEVICE(CLK_CTL), #ifdef CONFIG_MSM_DEBUG_UART MSM_DEVICE(DEBUG_UART), @@ -76,8 +76,8 @@ static struct map_desc qsd8x50_io_desc[] __initdata = { MSM_DEVICE(VIC), MSM_CHIP_DEVICE(CSR, QSD8X50), MSM_DEVICE(DMOV), - MSM_DEVICE(GPIO1), - MSM_DEVICE(GPIO2), + MSM_CHIP_DEVICE(GPIO1, QSD8X50), + MSM_CHIP_DEVICE(GPIO2, QSD8X50), MSM_DEVICE(CLK_CTL), MSM_DEVICE(SIRC), MSM_DEVICE(SCPLL), @@ -135,8 +135,8 @@ static struct map_desc msm7x30_io_desc[] __initdata = { MSM_DEVICE(VIC), MSM_CHIP_DEVICE(CSR, MSM7X30), MSM_DEVICE(DMOV), - MSM_DEVICE(GPIO1), - MSM_DEVICE(GPIO2), + MSM_CHIP_DEVICE(GPIO1, MSM7X30), + MSM_CHIP_DEVICE(GPIO2, MSM7X30), MSM_DEVICE(CLK_CTL), MSM_DEVICE(CLK_CTL_SH2), MSM_DEVICE(AD5), From 2e01d2c593d1cc5ed48cab6c07493185e4ac7a68 Mon Sep 17 00:00:00 2001 From: David Brown Date: Thu, 12 May 2011 01:16:46 -0700 Subject: [PATCH 3/8] msm: gpio: Remove chip-specific register definitions Put an SOC prefix on each GPIO register definition, eliminating the need to have SOC ifdefs around the definitions. Change-Id: I5a01fd328a89ce1be610847934d6e118f5465e42 Signed-off-by: David Brown Acked-by: Linus Walleij Acked-by: Nicolas Pitre --- arch/arm/mach-msm/gpio.c | 62 +++--- arch/arm/mach-msm/gpio_hw.h | 380 ++++++++++++++++++------------------ 2 files changed, 218 insertions(+), 224 deletions(-) diff --git a/arch/arm/mach-msm/gpio.c b/arch/arm/mach-msm/gpio.c index c358cedcda97..335afbd97c1d 100644 --- a/arch/arm/mach-msm/gpio.c +++ b/arch/arm/mach-msm/gpio.c @@ -25,17 +25,17 @@ #define FIRST_GPIO_IRQ MSM_GPIO_TO_INT(0) -#define MSM_GPIO_BANK(bank, first, last) \ +#define MSM_GPIO_BANK(soc, bank, first, last) \ { \ .regs = { \ - .out = MSM_GPIO_OUT_##bank, \ - .in = MSM_GPIO_IN_##bank, \ - .int_status = MSM_GPIO_INT_STATUS_##bank, \ - .int_clear = MSM_GPIO_INT_CLEAR_##bank, \ - .int_en = MSM_GPIO_INT_EN_##bank, \ - .int_edge = MSM_GPIO_INT_EDGE_##bank, \ - .int_pos = MSM_GPIO_INT_POS_##bank, \ - .oe = MSM_GPIO_OE_##bank, \ + .out = soc##_GPIO_OUT_##bank, \ + .in = soc##_GPIO_IN_##bank, \ + .int_status = soc##_GPIO_INT_STATUS_##bank, \ + .int_clear = soc##_GPIO_INT_CLEAR_##bank, \ + .int_en = soc##_GPIO_INT_EN_##bank, \ + .int_edge = soc##_GPIO_INT_EDGE_##bank, \ + .int_pos = soc##_GPIO_INT_POS_##bank, \ + .oe = soc##_GPIO_OE_##bank, \ }, \ .chip = { \ .base = (first), \ @@ -191,30 +191,30 @@ static void msm_gpio_free(struct gpio_chip *chip, unsigned offset) struct msm_gpio_chip msm_gpio_chips[] = { #if defined(CONFIG_ARCH_MSM7X00A) - MSM_GPIO_BANK(0, 0, 15), - MSM_GPIO_BANK(1, 16, 42), - MSM_GPIO_BANK(2, 43, 67), - MSM_GPIO_BANK(3, 68, 94), - MSM_GPIO_BANK(4, 95, 106), - MSM_GPIO_BANK(5, 107, 121), + MSM_GPIO_BANK(MSM7X00, 0, 0, 15), + MSM_GPIO_BANK(MSM7X00, 1, 16, 42), + MSM_GPIO_BANK(MSM7X00, 2, 43, 67), + MSM_GPIO_BANK(MSM7X00, 3, 68, 94), + MSM_GPIO_BANK(MSM7X00, 4, 95, 106), + MSM_GPIO_BANK(MSM7X00, 5, 107, 121), #elif defined(CONFIG_ARCH_MSM7X30) - MSM_GPIO_BANK(0, 0, 15), - MSM_GPIO_BANK(1, 16, 43), - MSM_GPIO_BANK(2, 44, 67), - MSM_GPIO_BANK(3, 68, 94), - MSM_GPIO_BANK(4, 95, 106), - MSM_GPIO_BANK(5, 107, 133), - MSM_GPIO_BANK(6, 134, 150), - MSM_GPIO_BANK(7, 151, 181), + MSM_GPIO_BANK(MSM7X30, 0, 0, 15), + MSM_GPIO_BANK(MSM7X30, 1, 16, 43), + MSM_GPIO_BANK(MSM7X30, 2, 44, 67), + MSM_GPIO_BANK(MSM7X30, 3, 68, 94), + MSM_GPIO_BANK(MSM7X30, 4, 95, 106), + MSM_GPIO_BANK(MSM7X30, 5, 107, 133), + MSM_GPIO_BANK(MSM7X30, 6, 134, 150), + MSM_GPIO_BANK(MSM7X30, 7, 151, 181), #elif defined(CONFIG_ARCH_QSD8X50) - MSM_GPIO_BANK(0, 0, 15), - MSM_GPIO_BANK(1, 16, 42), - MSM_GPIO_BANK(2, 43, 67), - MSM_GPIO_BANK(3, 68, 94), - MSM_GPIO_BANK(4, 95, 103), - MSM_GPIO_BANK(5, 104, 121), - MSM_GPIO_BANK(6, 122, 152), - MSM_GPIO_BANK(7, 153, 164), + MSM_GPIO_BANK(QSD8X50, 0, 0, 15), + MSM_GPIO_BANK(QSD8X50, 1, 16, 42), + MSM_GPIO_BANK(QSD8X50, 2, 43, 67), + MSM_GPIO_BANK(QSD8X50, 3, 68, 94), + MSM_GPIO_BANK(QSD8X50, 4, 95, 103), + MSM_GPIO_BANK(QSD8X50, 5, 104, 121), + MSM_GPIO_BANK(QSD8X50, 6, 122, 152), + MSM_GPIO_BANK(QSD8X50, 7, 153, 164), #endif }; diff --git a/arch/arm/mach-msm/gpio_hw.h b/arch/arm/mach-msm/gpio_hw.h index 6b5066038baa..ba7972ade8c5 100644 --- a/arch/arm/mach-msm/gpio_hw.h +++ b/arch/arm/mach-msm/gpio_hw.h @@ -31,248 +31,242 @@ ** macros. */ -#if defined(CONFIG_ARCH_MSM7X30) #define MSM_GPIO1_REG(off) (MSM_GPIO1_BASE + (off)) #define MSM_GPIO2_REG(off) (MSM_GPIO2_BASE + 0x400 + (off)) -#else -#define MSM_GPIO1_REG(off) (MSM_GPIO1_BASE + 0x800 + (off)) -#define MSM_GPIO2_REG(off) (MSM_GPIO2_BASE + 0xC00 + (off)) -#endif - -#if defined(CONFIG_ARCH_MSM7X00A) || defined(CONFIG_ARCH_MSM7X25) ||\ - defined(CONFIG_ARCH_MSM7X27) +#define MSM_GPIO1_SHADOW_REG(off) (MSM_GPIO1_BASE + 0x800 + (off)) +#define MSM_GPIO2_SHADOW_REG(off) (MSM_GPIO2_BASE + 0xC00 + (off)) +/* + * MSM7X00 registers + */ /* output value */ -#define MSM_GPIO_OUT_0 MSM_GPIO1_REG(0x00) /* gpio 15-0 */ -#define MSM_GPIO_OUT_1 MSM_GPIO2_REG(0x00) /* gpio 42-16 */ -#define MSM_GPIO_OUT_2 MSM_GPIO1_REG(0x04) /* gpio 67-43 */ -#define MSM_GPIO_OUT_3 MSM_GPIO1_REG(0x08) /* gpio 94-68 */ -#define MSM_GPIO_OUT_4 MSM_GPIO1_REG(0x0C) /* gpio 106-95 */ -#define MSM_GPIO_OUT_5 MSM_GPIO1_REG(0x50) /* gpio 107-121 */ +#define MSM7X00_GPIO_OUT_0 MSM_GPIO1_SHADOW_REG(0x00) /* gpio 15-0 */ +#define MSM7X00_GPIO_OUT_1 MSM_GPIO2_SHADOW_REG(0x00) /* gpio 42-16 */ +#define MSM7X00_GPIO_OUT_2 MSM_GPIO1_SHADOW_REG(0x04) /* gpio 67-43 */ +#define MSM7X00_GPIO_OUT_3 MSM_GPIO1_SHADOW_REG(0x08) /* gpio 94-68 */ +#define MSM7X00_GPIO_OUT_4 MSM_GPIO1_SHADOW_REG(0x0C) /* gpio 106-95 */ +#define MSM7X00_GPIO_OUT_5 MSM_GPIO1_SHADOW_REG(0x50) /* gpio 107-121 */ /* same pin map as above, output enable */ -#define MSM_GPIO_OE_0 MSM_GPIO1_REG(0x10) -#define MSM_GPIO_OE_1 MSM_GPIO2_REG(0x08) -#define MSM_GPIO_OE_2 MSM_GPIO1_REG(0x14) -#define MSM_GPIO_OE_3 MSM_GPIO1_REG(0x18) -#define MSM_GPIO_OE_4 MSM_GPIO1_REG(0x1C) -#define MSM_GPIO_OE_5 MSM_GPIO1_REG(0x54) +#define MSM7X00_GPIO_OE_0 MSM_GPIO1_SHADOW_REG(0x10) +#define MSM7X00_GPIO_OE_1 MSM_GPIO2_SHADOW_REG(0x08) +#define MSM7X00_GPIO_OE_2 MSM_GPIO1_SHADOW_REG(0x14) +#define MSM7X00_GPIO_OE_3 MSM_GPIO1_SHADOW_REG(0x18) +#define MSM7X00_GPIO_OE_4 MSM_GPIO1_SHADOW_REG(0x1C) +#define MSM7X00_GPIO_OE_5 MSM_GPIO1_SHADOW_REG(0x54) /* same pin map as above, input read */ -#define MSM_GPIO_IN_0 MSM_GPIO1_REG(0x34) -#define MSM_GPIO_IN_1 MSM_GPIO2_REG(0x20) -#define MSM_GPIO_IN_2 MSM_GPIO1_REG(0x38) -#define MSM_GPIO_IN_3 MSM_GPIO1_REG(0x3C) -#define MSM_GPIO_IN_4 MSM_GPIO1_REG(0x40) -#define MSM_GPIO_IN_5 MSM_GPIO1_REG(0x44) +#define MSM7X00_GPIO_IN_0 MSM_GPIO1_SHADOW_REG(0x34) +#define MSM7X00_GPIO_IN_1 MSM_GPIO2_SHADOW_REG(0x20) +#define MSM7X00_GPIO_IN_2 MSM_GPIO1_SHADOW_REG(0x38) +#define MSM7X00_GPIO_IN_3 MSM_GPIO1_SHADOW_REG(0x3C) +#define MSM7X00_GPIO_IN_4 MSM_GPIO1_SHADOW_REG(0x40) +#define MSM7X00_GPIO_IN_5 MSM_GPIO1_SHADOW_REG(0x44) /* same pin map as above, 1=edge 0=level interrup */ -#define MSM_GPIO_INT_EDGE_0 MSM_GPIO1_REG(0x60) -#define MSM_GPIO_INT_EDGE_1 MSM_GPIO2_REG(0x50) -#define MSM_GPIO_INT_EDGE_2 MSM_GPIO1_REG(0x64) -#define MSM_GPIO_INT_EDGE_3 MSM_GPIO1_REG(0x68) -#define MSM_GPIO_INT_EDGE_4 MSM_GPIO1_REG(0x6C) -#define MSM_GPIO_INT_EDGE_5 MSM_GPIO1_REG(0xC0) +#define MSM7X00_GPIO_INT_EDGE_0 MSM_GPIO1_SHADOW_REG(0x60) +#define MSM7X00_GPIO_INT_EDGE_1 MSM_GPIO2_SHADOW_REG(0x50) +#define MSM7X00_GPIO_INT_EDGE_2 MSM_GPIO1_SHADOW_REG(0x64) +#define MSM7X00_GPIO_INT_EDGE_3 MSM_GPIO1_SHADOW_REG(0x68) +#define MSM7X00_GPIO_INT_EDGE_4 MSM_GPIO1_SHADOW_REG(0x6C) +#define MSM7X00_GPIO_INT_EDGE_5 MSM_GPIO1_SHADOW_REG(0xC0) /* same pin map as above, 1=positive 0=negative */ -#define MSM_GPIO_INT_POS_0 MSM_GPIO1_REG(0x70) -#define MSM_GPIO_INT_POS_1 MSM_GPIO2_REG(0x58) -#define MSM_GPIO_INT_POS_2 MSM_GPIO1_REG(0x74) -#define MSM_GPIO_INT_POS_3 MSM_GPIO1_REG(0x78) -#define MSM_GPIO_INT_POS_4 MSM_GPIO1_REG(0x7C) -#define MSM_GPIO_INT_POS_5 MSM_GPIO1_REG(0xBC) +#define MSM7X00_GPIO_INT_POS_0 MSM_GPIO1_SHADOW_REG(0x70) +#define MSM7X00_GPIO_INT_POS_1 MSM_GPIO2_SHADOW_REG(0x58) +#define MSM7X00_GPIO_INT_POS_2 MSM_GPIO1_SHADOW_REG(0x74) +#define MSM7X00_GPIO_INT_POS_3 MSM_GPIO1_SHADOW_REG(0x78) +#define MSM7X00_GPIO_INT_POS_4 MSM_GPIO1_SHADOW_REG(0x7C) +#define MSM7X00_GPIO_INT_POS_5 MSM_GPIO1_SHADOW_REG(0xBC) /* same pin map as above, interrupt enable */ -#define MSM_GPIO_INT_EN_0 MSM_GPIO1_REG(0x80) -#define MSM_GPIO_INT_EN_1 MSM_GPIO2_REG(0x60) -#define MSM_GPIO_INT_EN_2 MSM_GPIO1_REG(0x84) -#define MSM_GPIO_INT_EN_3 MSM_GPIO1_REG(0x88) -#define MSM_GPIO_INT_EN_4 MSM_GPIO1_REG(0x8C) -#define MSM_GPIO_INT_EN_5 MSM_GPIO1_REG(0xB8) +#define MSM7X00_GPIO_INT_EN_0 MSM_GPIO1_SHADOW_REG(0x80) +#define MSM7X00_GPIO_INT_EN_1 MSM_GPIO2_SHADOW_REG(0x60) +#define MSM7X00_GPIO_INT_EN_2 MSM_GPIO1_SHADOW_REG(0x84) +#define MSM7X00_GPIO_INT_EN_3 MSM_GPIO1_SHADOW_REG(0x88) +#define MSM7X00_GPIO_INT_EN_4 MSM_GPIO1_SHADOW_REG(0x8C) +#define MSM7X00_GPIO_INT_EN_5 MSM_GPIO1_SHADOW_REG(0xB8) /* same pin map as above, write 1 to clear interrupt */ -#define MSM_GPIO_INT_CLEAR_0 MSM_GPIO1_REG(0x90) -#define MSM_GPIO_INT_CLEAR_1 MSM_GPIO2_REG(0x68) -#define MSM_GPIO_INT_CLEAR_2 MSM_GPIO1_REG(0x94) -#define MSM_GPIO_INT_CLEAR_3 MSM_GPIO1_REG(0x98) -#define MSM_GPIO_INT_CLEAR_4 MSM_GPIO1_REG(0x9C) -#define MSM_GPIO_INT_CLEAR_5 MSM_GPIO1_REG(0xB4) +#define MSM7X00_GPIO_INT_CLEAR_0 MSM_GPIO1_SHADOW_REG(0x90) +#define MSM7X00_GPIO_INT_CLEAR_1 MSM_GPIO2_SHADOW_REG(0x68) +#define MSM7X00_GPIO_INT_CLEAR_2 MSM_GPIO1_SHADOW_REG(0x94) +#define MSM7X00_GPIO_INT_CLEAR_3 MSM_GPIO1_SHADOW_REG(0x98) +#define MSM7X00_GPIO_INT_CLEAR_4 MSM_GPIO1_SHADOW_REG(0x9C) +#define MSM7X00_GPIO_INT_CLEAR_5 MSM_GPIO1_SHADOW_REG(0xB4) /* same pin map as above, 1=interrupt pending */ -#define MSM_GPIO_INT_STATUS_0 MSM_GPIO1_REG(0xA0) -#define MSM_GPIO_INT_STATUS_1 MSM_GPIO2_REG(0x70) -#define MSM_GPIO_INT_STATUS_2 MSM_GPIO1_REG(0xA4) -#define MSM_GPIO_INT_STATUS_3 MSM_GPIO1_REG(0xA8) -#define MSM_GPIO_INT_STATUS_4 MSM_GPIO1_REG(0xAC) -#define MSM_GPIO_INT_STATUS_5 MSM_GPIO1_REG(0xB0) +#define MSM7X00_GPIO_INT_STATUS_0 MSM_GPIO1_SHADOW_REG(0xA0) +#define MSM7X00_GPIO_INT_STATUS_1 MSM_GPIO2_SHADOW_REG(0x70) +#define MSM7X00_GPIO_INT_STATUS_2 MSM_GPIO1_SHADOW_REG(0xA4) +#define MSM7X00_GPIO_INT_STATUS_3 MSM_GPIO1_SHADOW_REG(0xA8) +#define MSM7X00_GPIO_INT_STATUS_4 MSM_GPIO1_SHADOW_REG(0xAC) +#define MSM7X00_GPIO_INT_STATUS_5 MSM_GPIO1_SHADOW_REG(0xB0) -#endif - -#if defined(CONFIG_ARCH_QSD8X50) +/* + * QSD8X50 registers + */ /* output value */ -#define MSM_GPIO_OUT_0 MSM_GPIO1_REG(0x00) /* gpio 15-0 */ -#define MSM_GPIO_OUT_1 MSM_GPIO2_REG(0x00) /* gpio 42-16 */ -#define MSM_GPIO_OUT_2 MSM_GPIO1_REG(0x04) /* gpio 67-43 */ -#define MSM_GPIO_OUT_3 MSM_GPIO1_REG(0x08) /* gpio 94-68 */ -#define MSM_GPIO_OUT_4 MSM_GPIO1_REG(0x0C) /* gpio 103-95 */ -#define MSM_GPIO_OUT_5 MSM_GPIO1_REG(0x10) /* gpio 121-104 */ -#define MSM_GPIO_OUT_6 MSM_GPIO1_REG(0x14) /* gpio 152-122 */ -#define MSM_GPIO_OUT_7 MSM_GPIO1_REG(0x18) /* gpio 164-153 */ +#define QSD8X50_GPIO_OUT_0 MSM_GPIO1_SHADOW_REG(0x00) /* gpio 15-0 */ +#define QSD8X50_GPIO_OUT_1 MSM_GPIO2_SHADOW_REG(0x00) /* gpio 42-16 */ +#define QSD8X50_GPIO_OUT_2 MSM_GPIO1_SHADOW_REG(0x04) /* gpio 67-43 */ +#define QSD8X50_GPIO_OUT_3 MSM_GPIO1_SHADOW_REG(0x08) /* gpio 94-68 */ +#define QSD8X50_GPIO_OUT_4 MSM_GPIO1_SHADOW_REG(0x0C) /* gpio 103-95 */ +#define QSD8X50_GPIO_OUT_5 MSM_GPIO1_SHADOW_REG(0x10) /* gpio 121-104 */ +#define QSD8X50_GPIO_OUT_6 MSM_GPIO1_SHADOW_REG(0x14) /* gpio 152-122 */ +#define QSD8X50_GPIO_OUT_7 MSM_GPIO1_SHADOW_REG(0x18) /* gpio 164-153 */ /* same pin map as above, output enable */ -#define MSM_GPIO_OE_0 MSM_GPIO1_REG(0x20) -#define MSM_GPIO_OE_1 MSM_GPIO2_REG(0x08) -#define MSM_GPIO_OE_2 MSM_GPIO1_REG(0x24) -#define MSM_GPIO_OE_3 MSM_GPIO1_REG(0x28) -#define MSM_GPIO_OE_4 MSM_GPIO1_REG(0x2C) -#define MSM_GPIO_OE_5 MSM_GPIO1_REG(0x30) -#define MSM_GPIO_OE_6 MSM_GPIO1_REG(0x34) -#define MSM_GPIO_OE_7 MSM_GPIO1_REG(0x38) +#define QSD8X50_GPIO_OE_0 MSM_GPIO1_SHADOW_REG(0x20) +#define QSD8X50_GPIO_OE_1 MSM_GPIO2_SHADOW_REG(0x08) +#define QSD8X50_GPIO_OE_2 MSM_GPIO1_SHADOW_REG(0x24) +#define QSD8X50_GPIO_OE_3 MSM_GPIO1_SHADOW_REG(0x28) +#define QSD8X50_GPIO_OE_4 MSM_GPIO1_SHADOW_REG(0x2C) +#define QSD8X50_GPIO_OE_5 MSM_GPIO1_SHADOW_REG(0x30) +#define QSD8X50_GPIO_OE_6 MSM_GPIO1_SHADOW_REG(0x34) +#define QSD8X50_GPIO_OE_7 MSM_GPIO1_SHADOW_REG(0x38) /* same pin map as above, input read */ -#define MSM_GPIO_IN_0 MSM_GPIO1_REG(0x50) -#define MSM_GPIO_IN_1 MSM_GPIO2_REG(0x20) -#define MSM_GPIO_IN_2 MSM_GPIO1_REG(0x54) -#define MSM_GPIO_IN_3 MSM_GPIO1_REG(0x58) -#define MSM_GPIO_IN_4 MSM_GPIO1_REG(0x5C) -#define MSM_GPIO_IN_5 MSM_GPIO1_REG(0x60) -#define MSM_GPIO_IN_6 MSM_GPIO1_REG(0x64) -#define MSM_GPIO_IN_7 MSM_GPIO1_REG(0x68) +#define QSD8X50_GPIO_IN_0 MSM_GPIO1_SHADOW_REG(0x50) +#define QSD8X50_GPIO_IN_1 MSM_GPIO2_SHADOW_REG(0x20) +#define QSD8X50_GPIO_IN_2 MSM_GPIO1_SHADOW_REG(0x54) +#define QSD8X50_GPIO_IN_3 MSM_GPIO1_SHADOW_REG(0x58) +#define QSD8X50_GPIO_IN_4 MSM_GPIO1_SHADOW_REG(0x5C) +#define QSD8X50_GPIO_IN_5 MSM_GPIO1_SHADOW_REG(0x60) +#define QSD8X50_GPIO_IN_6 MSM_GPIO1_SHADOW_REG(0x64) +#define QSD8X50_GPIO_IN_7 MSM_GPIO1_SHADOW_REG(0x68) /* same pin map as above, 1=edge 0=level interrup */ -#define MSM_GPIO_INT_EDGE_0 MSM_GPIO1_REG(0x70) -#define MSM_GPIO_INT_EDGE_1 MSM_GPIO2_REG(0x50) -#define MSM_GPIO_INT_EDGE_2 MSM_GPIO1_REG(0x74) -#define MSM_GPIO_INT_EDGE_3 MSM_GPIO1_REG(0x78) -#define MSM_GPIO_INT_EDGE_4 MSM_GPIO1_REG(0x7C) -#define MSM_GPIO_INT_EDGE_5 MSM_GPIO1_REG(0x80) -#define MSM_GPIO_INT_EDGE_6 MSM_GPIO1_REG(0x84) -#define MSM_GPIO_INT_EDGE_7 MSM_GPIO1_REG(0x88) +#define QSD8X50_GPIO_INT_EDGE_0 MSM_GPIO1_SHADOW_REG(0x70) +#define QSD8X50_GPIO_INT_EDGE_1 MSM_GPIO2_SHADOW_REG(0x50) +#define QSD8X50_GPIO_INT_EDGE_2 MSM_GPIO1_SHADOW_REG(0x74) +#define QSD8X50_GPIO_INT_EDGE_3 MSM_GPIO1_SHADOW_REG(0x78) +#define QSD8X50_GPIO_INT_EDGE_4 MSM_GPIO1_SHADOW_REG(0x7C) +#define QSD8X50_GPIO_INT_EDGE_5 MSM_GPIO1_SHADOW_REG(0x80) +#define QSD8X50_GPIO_INT_EDGE_6 MSM_GPIO1_SHADOW_REG(0x84) +#define QSD8X50_GPIO_INT_EDGE_7 MSM_GPIO1_SHADOW_REG(0x88) /* same pin map as above, 1=positive 0=negative */ -#define MSM_GPIO_INT_POS_0 MSM_GPIO1_REG(0x90) -#define MSM_GPIO_INT_POS_1 MSM_GPIO2_REG(0x58) -#define MSM_GPIO_INT_POS_2 MSM_GPIO1_REG(0x94) -#define MSM_GPIO_INT_POS_3 MSM_GPIO1_REG(0x98) -#define MSM_GPIO_INT_POS_4 MSM_GPIO1_REG(0x9C) -#define MSM_GPIO_INT_POS_5 MSM_GPIO1_REG(0xA0) -#define MSM_GPIO_INT_POS_6 MSM_GPIO1_REG(0xA4) -#define MSM_GPIO_INT_POS_7 MSM_GPIO1_REG(0xA8) +#define QSD8X50_GPIO_INT_POS_0 MSM_GPIO1_SHADOW_REG(0x90) +#define QSD8X50_GPIO_INT_POS_1 MSM_GPIO2_SHADOW_REG(0x58) +#define QSD8X50_GPIO_INT_POS_2 MSM_GPIO1_SHADOW_REG(0x94) +#define QSD8X50_GPIO_INT_POS_3 MSM_GPIO1_SHADOW_REG(0x98) +#define QSD8X50_GPIO_INT_POS_4 MSM_GPIO1_SHADOW_REG(0x9C) +#define QSD8X50_GPIO_INT_POS_5 MSM_GPIO1_SHADOW_REG(0xA0) +#define QSD8X50_GPIO_INT_POS_6 MSM_GPIO1_SHADOW_REG(0xA4) +#define QSD8X50_GPIO_INT_POS_7 MSM_GPIO1_SHADOW_REG(0xA8) /* same pin map as above, interrupt enable */ -#define MSM_GPIO_INT_EN_0 MSM_GPIO1_REG(0xB0) -#define MSM_GPIO_INT_EN_1 MSM_GPIO2_REG(0x60) -#define MSM_GPIO_INT_EN_2 MSM_GPIO1_REG(0xB4) -#define MSM_GPIO_INT_EN_3 MSM_GPIO1_REG(0xB8) -#define MSM_GPIO_INT_EN_4 MSM_GPIO1_REG(0xBC) -#define MSM_GPIO_INT_EN_5 MSM_GPIO1_REG(0xC0) -#define MSM_GPIO_INT_EN_6 MSM_GPIO1_REG(0xC4) -#define MSM_GPIO_INT_EN_7 MSM_GPIO1_REG(0xC8) +#define QSD8X50_GPIO_INT_EN_0 MSM_GPIO1_SHADOW_REG(0xB0) +#define QSD8X50_GPIO_INT_EN_1 MSM_GPIO2_SHADOW_REG(0x60) +#define QSD8X50_GPIO_INT_EN_2 MSM_GPIO1_SHADOW_REG(0xB4) +#define QSD8X50_GPIO_INT_EN_3 MSM_GPIO1_SHADOW_REG(0xB8) +#define QSD8X50_GPIO_INT_EN_4 MSM_GPIO1_SHADOW_REG(0xBC) +#define QSD8X50_GPIO_INT_EN_5 MSM_GPIO1_SHADOW_REG(0xC0) +#define QSD8X50_GPIO_INT_EN_6 MSM_GPIO1_SHADOW_REG(0xC4) +#define QSD8X50_GPIO_INT_EN_7 MSM_GPIO1_SHADOW_REG(0xC8) /* same pin map as above, write 1 to clear interrupt */ -#define MSM_GPIO_INT_CLEAR_0 MSM_GPIO1_REG(0xD0) -#define MSM_GPIO_INT_CLEAR_1 MSM_GPIO2_REG(0x68) -#define MSM_GPIO_INT_CLEAR_2 MSM_GPIO1_REG(0xD4) -#define MSM_GPIO_INT_CLEAR_3 MSM_GPIO1_REG(0xD8) -#define MSM_GPIO_INT_CLEAR_4 MSM_GPIO1_REG(0xDC) -#define MSM_GPIO_INT_CLEAR_5 MSM_GPIO1_REG(0xE0) -#define MSM_GPIO_INT_CLEAR_6 MSM_GPIO1_REG(0xE4) -#define MSM_GPIO_INT_CLEAR_7 MSM_GPIO1_REG(0xE8) +#define QSD8X50_GPIO_INT_CLEAR_0 MSM_GPIO1_SHADOW_REG(0xD0) +#define QSD8X50_GPIO_INT_CLEAR_1 MSM_GPIO2_SHADOW_REG(0x68) +#define QSD8X50_GPIO_INT_CLEAR_2 MSM_GPIO1_SHADOW_REG(0xD4) +#define QSD8X50_GPIO_INT_CLEAR_3 MSM_GPIO1_SHADOW_REG(0xD8) +#define QSD8X50_GPIO_INT_CLEAR_4 MSM_GPIO1_SHADOW_REG(0xDC) +#define QSD8X50_GPIO_INT_CLEAR_5 MSM_GPIO1_SHADOW_REG(0xE0) +#define QSD8X50_GPIO_INT_CLEAR_6 MSM_GPIO1_SHADOW_REG(0xE4) +#define QSD8X50_GPIO_INT_CLEAR_7 MSM_GPIO1_SHADOW_REG(0xE8) /* same pin map as above, 1=interrupt pending */ -#define MSM_GPIO_INT_STATUS_0 MSM_GPIO1_REG(0xF0) -#define MSM_GPIO_INT_STATUS_1 MSM_GPIO2_REG(0x70) -#define MSM_GPIO_INT_STATUS_2 MSM_GPIO1_REG(0xF4) -#define MSM_GPIO_INT_STATUS_3 MSM_GPIO1_REG(0xF8) -#define MSM_GPIO_INT_STATUS_4 MSM_GPIO1_REG(0xFC) -#define MSM_GPIO_INT_STATUS_5 MSM_GPIO1_REG(0x100) -#define MSM_GPIO_INT_STATUS_6 MSM_GPIO1_REG(0x104) -#define MSM_GPIO_INT_STATUS_7 MSM_GPIO1_REG(0x108) - -#endif - -#if defined(CONFIG_ARCH_MSM7X30) +#define QSD8X50_GPIO_INT_STATUS_0 MSM_GPIO1_SHADOW_REG(0xF0) +#define QSD8X50_GPIO_INT_STATUS_1 MSM_GPIO2_SHADOW_REG(0x70) +#define QSD8X50_GPIO_INT_STATUS_2 MSM_GPIO1_SHADOW_REG(0xF4) +#define QSD8X50_GPIO_INT_STATUS_3 MSM_GPIO1_SHADOW_REG(0xF8) +#define QSD8X50_GPIO_INT_STATUS_4 MSM_GPIO1_SHADOW_REG(0xFC) +#define QSD8X50_GPIO_INT_STATUS_5 MSM_GPIO1_SHADOW_REG(0x100) +#define QSD8X50_GPIO_INT_STATUS_6 MSM_GPIO1_SHADOW_REG(0x104) +#define QSD8X50_GPIO_INT_STATUS_7 MSM_GPIO1_SHADOW_REG(0x108) +/* + * MSM7X30 registers + */ /* output value */ -#define MSM_GPIO_OUT_0 MSM_GPIO1_REG(0x00) /* gpio 15-0 */ -#define MSM_GPIO_OUT_1 MSM_GPIO2_REG(0x00) /* gpio 43-16 */ -#define MSM_GPIO_OUT_2 MSM_GPIO1_REG(0x04) /* gpio 67-44 */ -#define MSM_GPIO_OUT_3 MSM_GPIO1_REG(0x08) /* gpio 94-68 */ -#define MSM_GPIO_OUT_4 MSM_GPIO1_REG(0x0C) /* gpio 106-95 */ -#define MSM_GPIO_OUT_5 MSM_GPIO1_REG(0x50) /* gpio 133-107 */ -#define MSM_GPIO_OUT_6 MSM_GPIO1_REG(0xC4) /* gpio 150-134 */ -#define MSM_GPIO_OUT_7 MSM_GPIO1_REG(0x214) /* gpio 181-151 */ +#define MSM7X30_GPIO_OUT_0 MSM_GPIO1_REG(0x00) /* gpio 15-0 */ +#define MSM7X30_GPIO_OUT_1 MSM_GPIO2_REG(0x00) /* gpio 43-16 */ +#define MSM7X30_GPIO_OUT_2 MSM_GPIO1_REG(0x04) /* gpio 67-44 */ +#define MSM7X30_GPIO_OUT_3 MSM_GPIO1_REG(0x08) /* gpio 94-68 */ +#define MSM7X30_GPIO_OUT_4 MSM_GPIO1_REG(0x0C) /* gpio 106-95 */ +#define MSM7X30_GPIO_OUT_5 MSM_GPIO1_REG(0x50) /* gpio 133-107 */ +#define MSM7X30_GPIO_OUT_6 MSM_GPIO1_REG(0xC4) /* gpio 150-134 */ +#define MSM7X30_GPIO_OUT_7 MSM_GPIO1_REG(0x214) /* gpio 181-151 */ /* same pin map as above, output enable */ -#define MSM_GPIO_OE_0 MSM_GPIO1_REG(0x10) -#define MSM_GPIO_OE_1 MSM_GPIO2_REG(0x08) -#define MSM_GPIO_OE_2 MSM_GPIO1_REG(0x14) -#define MSM_GPIO_OE_3 MSM_GPIO1_REG(0x18) -#define MSM_GPIO_OE_4 MSM_GPIO1_REG(0x1C) -#define MSM_GPIO_OE_5 MSM_GPIO1_REG(0x54) -#define MSM_GPIO_OE_6 MSM_GPIO1_REG(0xC8) -#define MSM_GPIO_OE_7 MSM_GPIO1_REG(0x218) +#define MSM7X30_GPIO_OE_0 MSM_GPIO1_REG(0x10) +#define MSM7X30_GPIO_OE_1 MSM_GPIO2_REG(0x08) +#define MSM7X30_GPIO_OE_2 MSM_GPIO1_REG(0x14) +#define MSM7X30_GPIO_OE_3 MSM_GPIO1_REG(0x18) +#define MSM7X30_GPIO_OE_4 MSM_GPIO1_REG(0x1C) +#define MSM7X30_GPIO_OE_5 MSM_GPIO1_REG(0x54) +#define MSM7X30_GPIO_OE_6 MSM_GPIO1_REG(0xC8) +#define MSM7X30_GPIO_OE_7 MSM_GPIO1_REG(0x218) /* same pin map as above, input read */ -#define MSM_GPIO_IN_0 MSM_GPIO1_REG(0x34) -#define MSM_GPIO_IN_1 MSM_GPIO2_REG(0x20) -#define MSM_GPIO_IN_2 MSM_GPIO1_REG(0x38) -#define MSM_GPIO_IN_3 MSM_GPIO1_REG(0x3C) -#define MSM_GPIO_IN_4 MSM_GPIO1_REG(0x40) -#define MSM_GPIO_IN_5 MSM_GPIO1_REG(0x44) -#define MSM_GPIO_IN_6 MSM_GPIO1_REG(0xCC) -#define MSM_GPIO_IN_7 MSM_GPIO1_REG(0x21C) +#define MSM7X30_GPIO_IN_0 MSM_GPIO1_REG(0x34) +#define MSM7X30_GPIO_IN_1 MSM_GPIO2_REG(0x20) +#define MSM7X30_GPIO_IN_2 MSM_GPIO1_REG(0x38) +#define MSM7X30_GPIO_IN_3 MSM_GPIO1_REG(0x3C) +#define MSM7X30_GPIO_IN_4 MSM_GPIO1_REG(0x40) +#define MSM7X30_GPIO_IN_5 MSM_GPIO1_REG(0x44) +#define MSM7X30_GPIO_IN_6 MSM_GPIO1_REG(0xCC) +#define MSM7X30_GPIO_IN_7 MSM_GPIO1_REG(0x21C) /* same pin map as above, 1=edge 0=level interrup */ -#define MSM_GPIO_INT_EDGE_0 MSM_GPIO1_REG(0x60) -#define MSM_GPIO_INT_EDGE_1 MSM_GPIO2_REG(0x50) -#define MSM_GPIO_INT_EDGE_2 MSM_GPIO1_REG(0x64) -#define MSM_GPIO_INT_EDGE_3 MSM_GPIO1_REG(0x68) -#define MSM_GPIO_INT_EDGE_4 MSM_GPIO1_REG(0x6C) -#define MSM_GPIO_INT_EDGE_5 MSM_GPIO1_REG(0xC0) -#define MSM_GPIO_INT_EDGE_6 MSM_GPIO1_REG(0xD0) -#define MSM_GPIO_INT_EDGE_7 MSM_GPIO1_REG(0x240) +#define MSM7X30_GPIO_INT_EDGE_0 MSM_GPIO1_REG(0x60) +#define MSM7X30_GPIO_INT_EDGE_1 MSM_GPIO2_REG(0x50) +#define MSM7X30_GPIO_INT_EDGE_2 MSM_GPIO1_REG(0x64) +#define MSM7X30_GPIO_INT_EDGE_3 MSM_GPIO1_REG(0x68) +#define MSM7X30_GPIO_INT_EDGE_4 MSM_GPIO1_REG(0x6C) +#define MSM7X30_GPIO_INT_EDGE_5 MSM_GPIO1_REG(0xC0) +#define MSM7X30_GPIO_INT_EDGE_6 MSM_GPIO1_REG(0xD0) +#define MSM7X30_GPIO_INT_EDGE_7 MSM_GPIO1_REG(0x240) /* same pin map as above, 1=positive 0=negative */ -#define MSM_GPIO_INT_POS_0 MSM_GPIO1_REG(0x70) -#define MSM_GPIO_INT_POS_1 MSM_GPIO2_REG(0x58) -#define MSM_GPIO_INT_POS_2 MSM_GPIO1_REG(0x74) -#define MSM_GPIO_INT_POS_3 MSM_GPIO1_REG(0x78) -#define MSM_GPIO_INT_POS_4 MSM_GPIO1_REG(0x7C) -#define MSM_GPIO_INT_POS_5 MSM_GPIO1_REG(0xBC) -#define MSM_GPIO_INT_POS_6 MSM_GPIO1_REG(0xD4) -#define MSM_GPIO_INT_POS_7 MSM_GPIO1_REG(0x228) +#define MSM7X30_GPIO_INT_POS_0 MSM_GPIO1_REG(0x70) +#define MSM7X30_GPIO_INT_POS_1 MSM_GPIO2_REG(0x58) +#define MSM7X30_GPIO_INT_POS_2 MSM_GPIO1_REG(0x74) +#define MSM7X30_GPIO_INT_POS_3 MSM_GPIO1_REG(0x78) +#define MSM7X30_GPIO_INT_POS_4 MSM_GPIO1_REG(0x7C) +#define MSM7X30_GPIO_INT_POS_5 MSM_GPIO1_REG(0xBC) +#define MSM7X30_GPIO_INT_POS_6 MSM_GPIO1_REG(0xD4) +#define MSM7X30_GPIO_INT_POS_7 MSM_GPIO1_REG(0x228) /* same pin map as above, interrupt enable */ -#define MSM_GPIO_INT_EN_0 MSM_GPIO1_REG(0x80) -#define MSM_GPIO_INT_EN_1 MSM_GPIO2_REG(0x60) -#define MSM_GPIO_INT_EN_2 MSM_GPIO1_REG(0x84) -#define MSM_GPIO_INT_EN_3 MSM_GPIO1_REG(0x88) -#define MSM_GPIO_INT_EN_4 MSM_GPIO1_REG(0x8C) -#define MSM_GPIO_INT_EN_5 MSM_GPIO1_REG(0xB8) -#define MSM_GPIO_INT_EN_6 MSM_GPIO1_REG(0xD8) -#define MSM_GPIO_INT_EN_7 MSM_GPIO1_REG(0x22C) +#define MSM7X30_GPIO_INT_EN_0 MSM_GPIO1_REG(0x80) +#define MSM7X30_GPIO_INT_EN_1 MSM_GPIO2_REG(0x60) +#define MSM7X30_GPIO_INT_EN_2 MSM_GPIO1_REG(0x84) +#define MSM7X30_GPIO_INT_EN_3 MSM_GPIO1_REG(0x88) +#define MSM7X30_GPIO_INT_EN_4 MSM_GPIO1_REG(0x8C) +#define MSM7X30_GPIO_INT_EN_5 MSM_GPIO1_REG(0xB8) +#define MSM7X30_GPIO_INT_EN_6 MSM_GPIO1_REG(0xD8) +#define MSM7X30_GPIO_INT_EN_7 MSM_GPIO1_REG(0x22C) /* same pin map as above, write 1 to clear interrupt */ -#define MSM_GPIO_INT_CLEAR_0 MSM_GPIO1_REG(0x90) -#define MSM_GPIO_INT_CLEAR_1 MSM_GPIO2_REG(0x68) -#define MSM_GPIO_INT_CLEAR_2 MSM_GPIO1_REG(0x94) -#define MSM_GPIO_INT_CLEAR_3 MSM_GPIO1_REG(0x98) -#define MSM_GPIO_INT_CLEAR_4 MSM_GPIO1_REG(0x9C) -#define MSM_GPIO_INT_CLEAR_5 MSM_GPIO1_REG(0xB4) -#define MSM_GPIO_INT_CLEAR_6 MSM_GPIO1_REG(0xDC) -#define MSM_GPIO_INT_CLEAR_7 MSM_GPIO1_REG(0x230) +#define MSM7X30_GPIO_INT_CLEAR_0 MSM_GPIO1_REG(0x90) +#define MSM7X30_GPIO_INT_CLEAR_1 MSM_GPIO2_REG(0x68) +#define MSM7X30_GPIO_INT_CLEAR_2 MSM_GPIO1_REG(0x94) +#define MSM7X30_GPIO_INT_CLEAR_3 MSM_GPIO1_REG(0x98) +#define MSM7X30_GPIO_INT_CLEAR_4 MSM_GPIO1_REG(0x9C) +#define MSM7X30_GPIO_INT_CLEAR_5 MSM_GPIO1_REG(0xB4) +#define MSM7X30_GPIO_INT_CLEAR_6 MSM_GPIO1_REG(0xDC) +#define MSM7X30_GPIO_INT_CLEAR_7 MSM_GPIO1_REG(0x230) /* same pin map as above, 1=interrupt pending */ -#define MSM_GPIO_INT_STATUS_0 MSM_GPIO1_REG(0xA0) -#define MSM_GPIO_INT_STATUS_1 MSM_GPIO2_REG(0x70) -#define MSM_GPIO_INT_STATUS_2 MSM_GPIO1_REG(0xA4) -#define MSM_GPIO_INT_STATUS_3 MSM_GPIO1_REG(0xA8) -#define MSM_GPIO_INT_STATUS_4 MSM_GPIO1_REG(0xAC) -#define MSM_GPIO_INT_STATUS_5 MSM_GPIO1_REG(0xB0) -#define MSM_GPIO_INT_STATUS_6 MSM_GPIO1_REG(0xE0) -#define MSM_GPIO_INT_STATUS_7 MSM_GPIO1_REG(0x234) - -#endif +#define MSM7X30_GPIO_INT_STATUS_0 MSM_GPIO1_REG(0xA0) +#define MSM7X30_GPIO_INT_STATUS_1 MSM_GPIO2_REG(0x70) +#define MSM7X30_GPIO_INT_STATUS_2 MSM_GPIO1_REG(0xA4) +#define MSM7X30_GPIO_INT_STATUS_3 MSM_GPIO1_REG(0xA8) +#define MSM7X30_GPIO_INT_STATUS_4 MSM_GPIO1_REG(0xAC) +#define MSM7X30_GPIO_INT_STATUS_5 MSM_GPIO1_REG(0xB0) +#define MSM7X30_GPIO_INT_STATUS_6 MSM_GPIO1_REG(0xE0) +#define MSM7X30_GPIO_INT_STATUS_7 MSM_GPIO1_REG(0x234) #endif From 10eb5f6bcbdc5e460e5500e1dbc39b2e7713ebfd Mon Sep 17 00:00:00 2001 From: David Brown Date: Thu, 12 May 2011 01:28:01 -0700 Subject: [PATCH 4/8] msm: gpio: Remove ifdefs on gpio chip registers Select the GPIO register configuration at runtime rather than through idefs. Change-Id: I02ea0a3d61bc81669f32097c32420f0688552231 Signed-off-by: David Brown Acked-by: Linus Walleij Acked-by: Nicolas Pitre --- arch/arm/mach-msm/gpio.c | 33 ++++++++++++++++++++++++++------- 1 file changed, 26 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-msm/gpio.c b/arch/arm/mach-msm/gpio.c index 335afbd97c1d..e96199dd14d0 100644 --- a/arch/arm/mach-msm/gpio.c +++ b/arch/arm/mach-msm/gpio.c @@ -20,6 +20,7 @@ #include #include #include +#include #include "gpio_hw.h" #include "gpiomux.h" @@ -189,15 +190,19 @@ static void msm_gpio_free(struct gpio_chip *chip, unsigned offset) #define msm_gpio_free NULL #endif -struct msm_gpio_chip msm_gpio_chips[] = { -#if defined(CONFIG_ARCH_MSM7X00A) +static struct msm_gpio_chip *msm_gpio_chips; +static int msm_gpio_count; + +static struct msm_gpio_chip msm_gpio_chips_msm7x01[] = { MSM_GPIO_BANK(MSM7X00, 0, 0, 15), MSM_GPIO_BANK(MSM7X00, 1, 16, 42), MSM_GPIO_BANK(MSM7X00, 2, 43, 67), MSM_GPIO_BANK(MSM7X00, 3, 68, 94), MSM_GPIO_BANK(MSM7X00, 4, 95, 106), MSM_GPIO_BANK(MSM7X00, 5, 107, 121), -#elif defined(CONFIG_ARCH_MSM7X30) +}; + +static struct msm_gpio_chip msm_gpio_chips_msm7x30[] = { MSM_GPIO_BANK(MSM7X30, 0, 0, 15), MSM_GPIO_BANK(MSM7X30, 1, 16, 43), MSM_GPIO_BANK(MSM7X30, 2, 44, 67), @@ -206,7 +211,9 @@ struct msm_gpio_chip msm_gpio_chips[] = { MSM_GPIO_BANK(MSM7X30, 5, 107, 133), MSM_GPIO_BANK(MSM7X30, 6, 134, 150), MSM_GPIO_BANK(MSM7X30, 7, 151, 181), -#elif defined(CONFIG_ARCH_QSD8X50) +}; + +static struct msm_gpio_chip msm_gpio_chips_qsd8x50[] = { MSM_GPIO_BANK(QSD8X50, 0, 0, 15), MSM_GPIO_BANK(QSD8X50, 1, 16, 42), MSM_GPIO_BANK(QSD8X50, 2, 43, 67), @@ -215,7 +222,6 @@ struct msm_gpio_chip msm_gpio_chips[] = { MSM_GPIO_BANK(QSD8X50, 5, 104, 121), MSM_GPIO_BANK(QSD8X50, 6, 122, 152), MSM_GPIO_BANK(QSD8X50, 7, 153, 164), -#endif }; static void msm_gpio_irq_ack(struct irq_data *d) @@ -311,7 +317,7 @@ static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) int i, j, mask; unsigned val; - for (i = 0; i < ARRAY_SIZE(msm_gpio_chips); i++) { + for (i = 0; i < msm_gpio_count; i++) { struct msm_gpio_chip *msm_chip = &msm_gpio_chips[i]; val = readl(msm_chip->regs.int_status); val &= msm_chip->int_enable[0]; @@ -342,6 +348,19 @@ static int __init msm_init_gpio(void) { int i, j = 0; + if (cpu_is_msm7x01()) { + msm_gpio_chips = msm_gpio_chips_msm7x01; + msm_gpio_count = ARRAY_SIZE(msm_gpio_chips_msm7x01); + } else if (cpu_is_msm7x30()) { + msm_gpio_chips = msm_gpio_chips_msm7x30; + msm_gpio_count = ARRAY_SIZE(msm_gpio_chips_msm7x30); + } else if (cpu_is_qsd8x50()) { + msm_gpio_chips = msm_gpio_chips_qsd8x50; + msm_gpio_count = ARRAY_SIZE(msm_gpio_chips_qsd8x50); + } else { + return 0; + } + for (i = FIRST_GPIO_IRQ; i < FIRST_GPIO_IRQ + NR_GPIO_IRQS; i++) { if (i - FIRST_GPIO_IRQ >= msm_gpio_chips[j].chip.base + @@ -353,7 +372,7 @@ static int __init msm_init_gpio(void) set_irq_flags(i, IRQF_VALID); } - for (i = 0; i < ARRAY_SIZE(msm_gpio_chips); i++) { + for (i = 0; i < msm_gpio_count; i++) { spin_lock_init(&msm_gpio_chips[i].lock); writel(0, msm_gpio_chips[i].regs.int_en); gpiochip_add(&msm_gpio_chips[i].chip); From 030a77fc9b805a38a2ffaea42728557282b81275 Mon Sep 17 00:00:00 2001 From: David Brown Date: Mon, 16 May 2011 13:32:15 -0700 Subject: [PATCH 5/8] msm: gpiomux: Move public API to public header The gpiomux.h header contains some SOC ifdefs. However, the API that is actually used by the GPIO driver only uses two functions that are general. Move these general definitions into a public header file. Change-Id: Ia5df8af87dba268225598d56908e523bcfc24ef6 Signed-off-by: David Brown Acked-by: Linus Walleij Acked-by: Nicolas Pitre --- arch/arm/mach-msm/gpio.c | 2 +- arch/arm/mach-msm/gpiomux.h | 17 +-------- arch/arm/mach-msm/include/mach/msm_gpiomux.h | 38 ++++++++++++++++++++ 3 files changed, 40 insertions(+), 17 deletions(-) create mode 100644 arch/arm/mach-msm/include/mach/msm_gpiomux.h diff --git a/arch/arm/mach-msm/gpio.c b/arch/arm/mach-msm/gpio.c index e96199dd14d0..6767deb79cd0 100644 --- a/arch/arm/mach-msm/gpio.c +++ b/arch/arm/mach-msm/gpio.c @@ -21,8 +21,8 @@ #include #include #include +#include #include "gpio_hw.h" -#include "gpiomux.h" #define FIRST_GPIO_IRQ MSM_GPIO_TO_INT(0) diff --git a/arch/arm/mach-msm/gpiomux.h b/arch/arm/mach-msm/gpiomux.h index b178d9cb742f..00459f6ee13c 100644 --- a/arch/arm/mach-msm/gpiomux.h +++ b/arch/arm/mach-msm/gpiomux.h @@ -19,6 +19,7 @@ #include #include +#include #if defined(CONFIG_MSM_V2_TLMM) #include "gpiomux-v2.h" @@ -71,12 +72,6 @@ enum { */ extern struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS]; -/* Increment a gpio's reference count, possibly activating the line. */ -int __must_check msm_gpiomux_get(unsigned gpio); - -/* Decrement a gpio's reference count, possibly suspending the line. */ -int msm_gpiomux_put(unsigned gpio); - /* Install a new configuration to the gpio line. To avoid overwriting * a configuration, leave the VALID bit out. */ @@ -94,16 +89,6 @@ int msm_gpiomux_write(unsigned gpio, */ void __msm_gpiomux_write(unsigned gpio, gpiomux_config_t val); #else -static inline int __must_check msm_gpiomux_get(unsigned gpio) -{ - return -ENOSYS; -} - -static inline int msm_gpiomux_put(unsigned gpio) -{ - return -ENOSYS; -} - static inline int msm_gpiomux_write(unsigned gpio, gpiomux_config_t active, gpiomux_config_t suspended) diff --git a/arch/arm/mach-msm/include/mach/msm_gpiomux.h b/arch/arm/mach-msm/include/mach/msm_gpiomux.h new file mode 100644 index 000000000000..0c7d3936e02f --- /dev/null +++ b/arch/arm/mach-msm/include/mach/msm_gpiomux.h @@ -0,0 +1,38 @@ +/* Copyright (c) 2011, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _LINUX_MSM_GPIOMUX_H +#define _LINUX_MSM_GPIOMUX_H + +#ifdef CONFIG_MSM_GPIOMUX + +/* Increment a gpio's reference count, possibly activating the line. */ +int __must_check msm_gpiomux_get(unsigned gpio); + +/* Decrement a gpio's reference count, possibly suspending the line. */ +int msm_gpiomux_put(unsigned gpio); + +#else + +static inline int __must_check msm_gpiomux_get(unsigned gpio) +{ + return -ENOSYS; +} + +static inline int msm_gpiomux_put(unsigned gpio) +{ + return -ENOSYS; +} + +#endif + +#endif /* _LINUX_MSM_GPIOMUX_H */ From 9def3efc4856597bc6bb9611f444defc898d2e0d Mon Sep 17 00:00:00 2001 From: David Brown Date: Mon, 6 Jun 2011 14:09:45 -0700 Subject: [PATCH 6/8] msm: gpio: Fold register defs into C file No need to have a separate header file containing only register definitions that are used by a single driver. Fold these into the gpio driver. Signed-off-by: David Brown --- arch/arm/mach-msm/gpio.c | 251 ++++++++++++++++++++++++++++++++- arch/arm/mach-msm/gpio_hw.h | 272 ------------------------------------ 2 files changed, 250 insertions(+), 273 deletions(-) delete mode 100644 arch/arm/mach-msm/gpio_hw.h diff --git a/arch/arm/mach-msm/gpio.c b/arch/arm/mach-msm/gpio.c index 6767deb79cd0..3bbf50ed2b42 100644 --- a/arch/arm/mach-msm/gpio.c +++ b/arch/arm/mach-msm/gpio.c @@ -22,7 +22,256 @@ #include #include #include -#include "gpio_hw.h" +#include + +/* see 80-VA736-2 Rev C pp 695-751 +** +** These are actually the *shadow* gpio registers, since the +** real ones (which allow full access) are only available to the +** ARM9 side of the world. +** +** Since the _BASE need to be page-aligned when we're mapping them +** to virtual addresses, adjust for the additional offset in these +** macros. +*/ + +#define MSM_GPIO1_REG(off) (MSM_GPIO1_BASE + (off)) +#define MSM_GPIO2_REG(off) (MSM_GPIO2_BASE + 0x400 + (off)) +#define MSM_GPIO1_SHADOW_REG(off) (MSM_GPIO1_BASE + 0x800 + (off)) +#define MSM_GPIO2_SHADOW_REG(off) (MSM_GPIO2_BASE + 0xC00 + (off)) + +/* + * MSM7X00 registers + */ +/* output value */ +#define MSM7X00_GPIO_OUT_0 MSM_GPIO1_SHADOW_REG(0x00) /* gpio 15-0 */ +#define MSM7X00_GPIO_OUT_1 MSM_GPIO2_SHADOW_REG(0x00) /* gpio 42-16 */ +#define MSM7X00_GPIO_OUT_2 MSM_GPIO1_SHADOW_REG(0x04) /* gpio 67-43 */ +#define MSM7X00_GPIO_OUT_3 MSM_GPIO1_SHADOW_REG(0x08) /* gpio 94-68 */ +#define MSM7X00_GPIO_OUT_4 MSM_GPIO1_SHADOW_REG(0x0C) /* gpio 106-95 */ +#define MSM7X00_GPIO_OUT_5 MSM_GPIO1_SHADOW_REG(0x50) /* gpio 107-121 */ + +/* same pin map as above, output enable */ +#define MSM7X00_GPIO_OE_0 MSM_GPIO1_SHADOW_REG(0x10) +#define MSM7X00_GPIO_OE_1 MSM_GPIO2_SHADOW_REG(0x08) +#define MSM7X00_GPIO_OE_2 MSM_GPIO1_SHADOW_REG(0x14) +#define MSM7X00_GPIO_OE_3 MSM_GPIO1_SHADOW_REG(0x18) +#define MSM7X00_GPIO_OE_4 MSM_GPIO1_SHADOW_REG(0x1C) +#define MSM7X00_GPIO_OE_5 MSM_GPIO1_SHADOW_REG(0x54) + +/* same pin map as above, input read */ +#define MSM7X00_GPIO_IN_0 MSM_GPIO1_SHADOW_REG(0x34) +#define MSM7X00_GPIO_IN_1 MSM_GPIO2_SHADOW_REG(0x20) +#define MSM7X00_GPIO_IN_2 MSM_GPIO1_SHADOW_REG(0x38) +#define MSM7X00_GPIO_IN_3 MSM_GPIO1_SHADOW_REG(0x3C) +#define MSM7X00_GPIO_IN_4 MSM_GPIO1_SHADOW_REG(0x40) +#define MSM7X00_GPIO_IN_5 MSM_GPIO1_SHADOW_REG(0x44) + +/* same pin map as above, 1=edge 0=level interrup */ +#define MSM7X00_GPIO_INT_EDGE_0 MSM_GPIO1_SHADOW_REG(0x60) +#define MSM7X00_GPIO_INT_EDGE_1 MSM_GPIO2_SHADOW_REG(0x50) +#define MSM7X00_GPIO_INT_EDGE_2 MSM_GPIO1_SHADOW_REG(0x64) +#define MSM7X00_GPIO_INT_EDGE_3 MSM_GPIO1_SHADOW_REG(0x68) +#define MSM7X00_GPIO_INT_EDGE_4 MSM_GPIO1_SHADOW_REG(0x6C) +#define MSM7X00_GPIO_INT_EDGE_5 MSM_GPIO1_SHADOW_REG(0xC0) + +/* same pin map as above, 1=positive 0=negative */ +#define MSM7X00_GPIO_INT_POS_0 MSM_GPIO1_SHADOW_REG(0x70) +#define MSM7X00_GPIO_INT_POS_1 MSM_GPIO2_SHADOW_REG(0x58) +#define MSM7X00_GPIO_INT_POS_2 MSM_GPIO1_SHADOW_REG(0x74) +#define MSM7X00_GPIO_INT_POS_3 MSM_GPIO1_SHADOW_REG(0x78) +#define MSM7X00_GPIO_INT_POS_4 MSM_GPIO1_SHADOW_REG(0x7C) +#define MSM7X00_GPIO_INT_POS_5 MSM_GPIO1_SHADOW_REG(0xBC) + +/* same pin map as above, interrupt enable */ +#define MSM7X00_GPIO_INT_EN_0 MSM_GPIO1_SHADOW_REG(0x80) +#define MSM7X00_GPIO_INT_EN_1 MSM_GPIO2_SHADOW_REG(0x60) +#define MSM7X00_GPIO_INT_EN_2 MSM_GPIO1_SHADOW_REG(0x84) +#define MSM7X00_GPIO_INT_EN_3 MSM_GPIO1_SHADOW_REG(0x88) +#define MSM7X00_GPIO_INT_EN_4 MSM_GPIO1_SHADOW_REG(0x8C) +#define MSM7X00_GPIO_INT_EN_5 MSM_GPIO1_SHADOW_REG(0xB8) + +/* same pin map as above, write 1 to clear interrupt */ +#define MSM7X00_GPIO_INT_CLEAR_0 MSM_GPIO1_SHADOW_REG(0x90) +#define MSM7X00_GPIO_INT_CLEAR_1 MSM_GPIO2_SHADOW_REG(0x68) +#define MSM7X00_GPIO_INT_CLEAR_2 MSM_GPIO1_SHADOW_REG(0x94) +#define MSM7X00_GPIO_INT_CLEAR_3 MSM_GPIO1_SHADOW_REG(0x98) +#define MSM7X00_GPIO_INT_CLEAR_4 MSM_GPIO1_SHADOW_REG(0x9C) +#define MSM7X00_GPIO_INT_CLEAR_5 MSM_GPIO1_SHADOW_REG(0xB4) + +/* same pin map as above, 1=interrupt pending */ +#define MSM7X00_GPIO_INT_STATUS_0 MSM_GPIO1_SHADOW_REG(0xA0) +#define MSM7X00_GPIO_INT_STATUS_1 MSM_GPIO2_SHADOW_REG(0x70) +#define MSM7X00_GPIO_INT_STATUS_2 MSM_GPIO1_SHADOW_REG(0xA4) +#define MSM7X00_GPIO_INT_STATUS_3 MSM_GPIO1_SHADOW_REG(0xA8) +#define MSM7X00_GPIO_INT_STATUS_4 MSM_GPIO1_SHADOW_REG(0xAC) +#define MSM7X00_GPIO_INT_STATUS_5 MSM_GPIO1_SHADOW_REG(0xB0) + +/* + * QSD8X50 registers + */ +/* output value */ +#define QSD8X50_GPIO_OUT_0 MSM_GPIO1_SHADOW_REG(0x00) /* gpio 15-0 */ +#define QSD8X50_GPIO_OUT_1 MSM_GPIO2_SHADOW_REG(0x00) /* gpio 42-16 */ +#define QSD8X50_GPIO_OUT_2 MSM_GPIO1_SHADOW_REG(0x04) /* gpio 67-43 */ +#define QSD8X50_GPIO_OUT_3 MSM_GPIO1_SHADOW_REG(0x08) /* gpio 94-68 */ +#define QSD8X50_GPIO_OUT_4 MSM_GPIO1_SHADOW_REG(0x0C) /* gpio 103-95 */ +#define QSD8X50_GPIO_OUT_5 MSM_GPIO1_SHADOW_REG(0x10) /* gpio 121-104 */ +#define QSD8X50_GPIO_OUT_6 MSM_GPIO1_SHADOW_REG(0x14) /* gpio 152-122 */ +#define QSD8X50_GPIO_OUT_7 MSM_GPIO1_SHADOW_REG(0x18) /* gpio 164-153 */ + +/* same pin map as above, output enable */ +#define QSD8X50_GPIO_OE_0 MSM_GPIO1_SHADOW_REG(0x20) +#define QSD8X50_GPIO_OE_1 MSM_GPIO2_SHADOW_REG(0x08) +#define QSD8X50_GPIO_OE_2 MSM_GPIO1_SHADOW_REG(0x24) +#define QSD8X50_GPIO_OE_3 MSM_GPIO1_SHADOW_REG(0x28) +#define QSD8X50_GPIO_OE_4 MSM_GPIO1_SHADOW_REG(0x2C) +#define QSD8X50_GPIO_OE_5 MSM_GPIO1_SHADOW_REG(0x30) +#define QSD8X50_GPIO_OE_6 MSM_GPIO1_SHADOW_REG(0x34) +#define QSD8X50_GPIO_OE_7 MSM_GPIO1_SHADOW_REG(0x38) + +/* same pin map as above, input read */ +#define QSD8X50_GPIO_IN_0 MSM_GPIO1_SHADOW_REG(0x50) +#define QSD8X50_GPIO_IN_1 MSM_GPIO2_SHADOW_REG(0x20) +#define QSD8X50_GPIO_IN_2 MSM_GPIO1_SHADOW_REG(0x54) +#define QSD8X50_GPIO_IN_3 MSM_GPIO1_SHADOW_REG(0x58) +#define QSD8X50_GPIO_IN_4 MSM_GPIO1_SHADOW_REG(0x5C) +#define QSD8X50_GPIO_IN_5 MSM_GPIO1_SHADOW_REG(0x60) +#define QSD8X50_GPIO_IN_6 MSM_GPIO1_SHADOW_REG(0x64) +#define QSD8X50_GPIO_IN_7 MSM_GPIO1_SHADOW_REG(0x68) + +/* same pin map as above, 1=edge 0=level interrup */ +#define QSD8X50_GPIO_INT_EDGE_0 MSM_GPIO1_SHADOW_REG(0x70) +#define QSD8X50_GPIO_INT_EDGE_1 MSM_GPIO2_SHADOW_REG(0x50) +#define QSD8X50_GPIO_INT_EDGE_2 MSM_GPIO1_SHADOW_REG(0x74) +#define QSD8X50_GPIO_INT_EDGE_3 MSM_GPIO1_SHADOW_REG(0x78) +#define QSD8X50_GPIO_INT_EDGE_4 MSM_GPIO1_SHADOW_REG(0x7C) +#define QSD8X50_GPIO_INT_EDGE_5 MSM_GPIO1_SHADOW_REG(0x80) +#define QSD8X50_GPIO_INT_EDGE_6 MSM_GPIO1_SHADOW_REG(0x84) +#define QSD8X50_GPIO_INT_EDGE_7 MSM_GPIO1_SHADOW_REG(0x88) + +/* same pin map as above, 1=positive 0=negative */ +#define QSD8X50_GPIO_INT_POS_0 MSM_GPIO1_SHADOW_REG(0x90) +#define QSD8X50_GPIO_INT_POS_1 MSM_GPIO2_SHADOW_REG(0x58) +#define QSD8X50_GPIO_INT_POS_2 MSM_GPIO1_SHADOW_REG(0x94) +#define QSD8X50_GPIO_INT_POS_3 MSM_GPIO1_SHADOW_REG(0x98) +#define QSD8X50_GPIO_INT_POS_4 MSM_GPIO1_SHADOW_REG(0x9C) +#define QSD8X50_GPIO_INT_POS_5 MSM_GPIO1_SHADOW_REG(0xA0) +#define QSD8X50_GPIO_INT_POS_6 MSM_GPIO1_SHADOW_REG(0xA4) +#define QSD8X50_GPIO_INT_POS_7 MSM_GPIO1_SHADOW_REG(0xA8) + +/* same pin map as above, interrupt enable */ +#define QSD8X50_GPIO_INT_EN_0 MSM_GPIO1_SHADOW_REG(0xB0) +#define QSD8X50_GPIO_INT_EN_1 MSM_GPIO2_SHADOW_REG(0x60) +#define QSD8X50_GPIO_INT_EN_2 MSM_GPIO1_SHADOW_REG(0xB4) +#define QSD8X50_GPIO_INT_EN_3 MSM_GPIO1_SHADOW_REG(0xB8) +#define QSD8X50_GPIO_INT_EN_4 MSM_GPIO1_SHADOW_REG(0xBC) +#define QSD8X50_GPIO_INT_EN_5 MSM_GPIO1_SHADOW_REG(0xC0) +#define QSD8X50_GPIO_INT_EN_6 MSM_GPIO1_SHADOW_REG(0xC4) +#define QSD8X50_GPIO_INT_EN_7 MSM_GPIO1_SHADOW_REG(0xC8) + +/* same pin map as above, write 1 to clear interrupt */ +#define QSD8X50_GPIO_INT_CLEAR_0 MSM_GPIO1_SHADOW_REG(0xD0) +#define QSD8X50_GPIO_INT_CLEAR_1 MSM_GPIO2_SHADOW_REG(0x68) +#define QSD8X50_GPIO_INT_CLEAR_2 MSM_GPIO1_SHADOW_REG(0xD4) +#define QSD8X50_GPIO_INT_CLEAR_3 MSM_GPIO1_SHADOW_REG(0xD8) +#define QSD8X50_GPIO_INT_CLEAR_4 MSM_GPIO1_SHADOW_REG(0xDC) +#define QSD8X50_GPIO_INT_CLEAR_5 MSM_GPIO1_SHADOW_REG(0xE0) +#define QSD8X50_GPIO_INT_CLEAR_6 MSM_GPIO1_SHADOW_REG(0xE4) +#define QSD8X50_GPIO_INT_CLEAR_7 MSM_GPIO1_SHADOW_REG(0xE8) + +/* same pin map as above, 1=interrupt pending */ +#define QSD8X50_GPIO_INT_STATUS_0 MSM_GPIO1_SHADOW_REG(0xF0) +#define QSD8X50_GPIO_INT_STATUS_1 MSM_GPIO2_SHADOW_REG(0x70) +#define QSD8X50_GPIO_INT_STATUS_2 MSM_GPIO1_SHADOW_REG(0xF4) +#define QSD8X50_GPIO_INT_STATUS_3 MSM_GPIO1_SHADOW_REG(0xF8) +#define QSD8X50_GPIO_INT_STATUS_4 MSM_GPIO1_SHADOW_REG(0xFC) +#define QSD8X50_GPIO_INT_STATUS_5 MSM_GPIO1_SHADOW_REG(0x100) +#define QSD8X50_GPIO_INT_STATUS_6 MSM_GPIO1_SHADOW_REG(0x104) +#define QSD8X50_GPIO_INT_STATUS_7 MSM_GPIO1_SHADOW_REG(0x108) + +/* + * MSM7X30 registers + */ +/* output value */ +#define MSM7X30_GPIO_OUT_0 MSM_GPIO1_REG(0x00) /* gpio 15-0 */ +#define MSM7X30_GPIO_OUT_1 MSM_GPIO2_REG(0x00) /* gpio 43-16 */ +#define MSM7X30_GPIO_OUT_2 MSM_GPIO1_REG(0x04) /* gpio 67-44 */ +#define MSM7X30_GPIO_OUT_3 MSM_GPIO1_REG(0x08) /* gpio 94-68 */ +#define MSM7X30_GPIO_OUT_4 MSM_GPIO1_REG(0x0C) /* gpio 106-95 */ +#define MSM7X30_GPIO_OUT_5 MSM_GPIO1_REG(0x50) /* gpio 133-107 */ +#define MSM7X30_GPIO_OUT_6 MSM_GPIO1_REG(0xC4) /* gpio 150-134 */ +#define MSM7X30_GPIO_OUT_7 MSM_GPIO1_REG(0x214) /* gpio 181-151 */ + +/* same pin map as above, output enable */ +#define MSM7X30_GPIO_OE_0 MSM_GPIO1_REG(0x10) +#define MSM7X30_GPIO_OE_1 MSM_GPIO2_REG(0x08) +#define MSM7X30_GPIO_OE_2 MSM_GPIO1_REG(0x14) +#define MSM7X30_GPIO_OE_3 MSM_GPIO1_REG(0x18) +#define MSM7X30_GPIO_OE_4 MSM_GPIO1_REG(0x1C) +#define MSM7X30_GPIO_OE_5 MSM_GPIO1_REG(0x54) +#define MSM7X30_GPIO_OE_6 MSM_GPIO1_REG(0xC8) +#define MSM7X30_GPIO_OE_7 MSM_GPIO1_REG(0x218) + +/* same pin map as above, input read */ +#define MSM7X30_GPIO_IN_0 MSM_GPIO1_REG(0x34) +#define MSM7X30_GPIO_IN_1 MSM_GPIO2_REG(0x20) +#define MSM7X30_GPIO_IN_2 MSM_GPIO1_REG(0x38) +#define MSM7X30_GPIO_IN_3 MSM_GPIO1_REG(0x3C) +#define MSM7X30_GPIO_IN_4 MSM_GPIO1_REG(0x40) +#define MSM7X30_GPIO_IN_5 MSM_GPIO1_REG(0x44) +#define MSM7X30_GPIO_IN_6 MSM_GPIO1_REG(0xCC) +#define MSM7X30_GPIO_IN_7 MSM_GPIO1_REG(0x21C) + +/* same pin map as above, 1=edge 0=level interrup */ +#define MSM7X30_GPIO_INT_EDGE_0 MSM_GPIO1_REG(0x60) +#define MSM7X30_GPIO_INT_EDGE_1 MSM_GPIO2_REG(0x50) +#define MSM7X30_GPIO_INT_EDGE_2 MSM_GPIO1_REG(0x64) +#define MSM7X30_GPIO_INT_EDGE_3 MSM_GPIO1_REG(0x68) +#define MSM7X30_GPIO_INT_EDGE_4 MSM_GPIO1_REG(0x6C) +#define MSM7X30_GPIO_INT_EDGE_5 MSM_GPIO1_REG(0xC0) +#define MSM7X30_GPIO_INT_EDGE_6 MSM_GPIO1_REG(0xD0) +#define MSM7X30_GPIO_INT_EDGE_7 MSM_GPIO1_REG(0x240) + +/* same pin map as above, 1=positive 0=negative */ +#define MSM7X30_GPIO_INT_POS_0 MSM_GPIO1_REG(0x70) +#define MSM7X30_GPIO_INT_POS_1 MSM_GPIO2_REG(0x58) +#define MSM7X30_GPIO_INT_POS_2 MSM_GPIO1_REG(0x74) +#define MSM7X30_GPIO_INT_POS_3 MSM_GPIO1_REG(0x78) +#define MSM7X30_GPIO_INT_POS_4 MSM_GPIO1_REG(0x7C) +#define MSM7X30_GPIO_INT_POS_5 MSM_GPIO1_REG(0xBC) +#define MSM7X30_GPIO_INT_POS_6 MSM_GPIO1_REG(0xD4) +#define MSM7X30_GPIO_INT_POS_7 MSM_GPIO1_REG(0x228) + +/* same pin map as above, interrupt enable */ +#define MSM7X30_GPIO_INT_EN_0 MSM_GPIO1_REG(0x80) +#define MSM7X30_GPIO_INT_EN_1 MSM_GPIO2_REG(0x60) +#define MSM7X30_GPIO_INT_EN_2 MSM_GPIO1_REG(0x84) +#define MSM7X30_GPIO_INT_EN_3 MSM_GPIO1_REG(0x88) +#define MSM7X30_GPIO_INT_EN_4 MSM_GPIO1_REG(0x8C) +#define MSM7X30_GPIO_INT_EN_5 MSM_GPIO1_REG(0xB8) +#define MSM7X30_GPIO_INT_EN_6 MSM_GPIO1_REG(0xD8) +#define MSM7X30_GPIO_INT_EN_7 MSM_GPIO1_REG(0x22C) + +/* same pin map as above, write 1 to clear interrupt */ +#define MSM7X30_GPIO_INT_CLEAR_0 MSM_GPIO1_REG(0x90) +#define MSM7X30_GPIO_INT_CLEAR_1 MSM_GPIO2_REG(0x68) +#define MSM7X30_GPIO_INT_CLEAR_2 MSM_GPIO1_REG(0x94) +#define MSM7X30_GPIO_INT_CLEAR_3 MSM_GPIO1_REG(0x98) +#define MSM7X30_GPIO_INT_CLEAR_4 MSM_GPIO1_REG(0x9C) +#define MSM7X30_GPIO_INT_CLEAR_5 MSM_GPIO1_REG(0xB4) +#define MSM7X30_GPIO_INT_CLEAR_6 MSM_GPIO1_REG(0xDC) +#define MSM7X30_GPIO_INT_CLEAR_7 MSM_GPIO1_REG(0x230) + +/* same pin map as above, 1=interrupt pending */ +#define MSM7X30_GPIO_INT_STATUS_0 MSM_GPIO1_REG(0xA0) +#define MSM7X30_GPIO_INT_STATUS_1 MSM_GPIO2_REG(0x70) +#define MSM7X30_GPIO_INT_STATUS_2 MSM_GPIO1_REG(0xA4) +#define MSM7X30_GPIO_INT_STATUS_3 MSM_GPIO1_REG(0xA8) +#define MSM7X30_GPIO_INT_STATUS_4 MSM_GPIO1_REG(0xAC) +#define MSM7X30_GPIO_INT_STATUS_5 MSM_GPIO1_REG(0xB0) +#define MSM7X30_GPIO_INT_STATUS_6 MSM_GPIO1_REG(0xE0) +#define MSM7X30_GPIO_INT_STATUS_7 MSM_GPIO1_REG(0x234) #define FIRST_GPIO_IRQ MSM_GPIO_TO_INT(0) diff --git a/arch/arm/mach-msm/gpio_hw.h b/arch/arm/mach-msm/gpio_hw.h deleted file mode 100644 index ba7972ade8c5..000000000000 --- a/arch/arm/mach-msm/gpio_hw.h +++ /dev/null @@ -1,272 +0,0 @@ -/* arch/arm/mach-msm/gpio_hw.h - * - * Copyright (C) 2007 Google, Inc. - * Author: Brian Swetland - * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __ARCH_ARM_MACH_MSM_GPIO_HW_H -#define __ARCH_ARM_MACH_MSM_GPIO_HW_H - -#include - -/* see 80-VA736-2 Rev C pp 695-751 -** -** These are actually the *shadow* gpio registers, since the -** real ones (which allow full access) are only available to the -** ARM9 side of the world. -** -** Since the _BASE need to be page-aligned when we're mapping them -** to virtual addresses, adjust for the additional offset in these -** macros. -*/ - -#define MSM_GPIO1_REG(off) (MSM_GPIO1_BASE + (off)) -#define MSM_GPIO2_REG(off) (MSM_GPIO2_BASE + 0x400 + (off)) -#define MSM_GPIO1_SHADOW_REG(off) (MSM_GPIO1_BASE + 0x800 + (off)) -#define MSM_GPIO2_SHADOW_REG(off) (MSM_GPIO2_BASE + 0xC00 + (off)) - -/* - * MSM7X00 registers - */ -/* output value */ -#define MSM7X00_GPIO_OUT_0 MSM_GPIO1_SHADOW_REG(0x00) /* gpio 15-0 */ -#define MSM7X00_GPIO_OUT_1 MSM_GPIO2_SHADOW_REG(0x00) /* gpio 42-16 */ -#define MSM7X00_GPIO_OUT_2 MSM_GPIO1_SHADOW_REG(0x04) /* gpio 67-43 */ -#define MSM7X00_GPIO_OUT_3 MSM_GPIO1_SHADOW_REG(0x08) /* gpio 94-68 */ -#define MSM7X00_GPIO_OUT_4 MSM_GPIO1_SHADOW_REG(0x0C) /* gpio 106-95 */ -#define MSM7X00_GPIO_OUT_5 MSM_GPIO1_SHADOW_REG(0x50) /* gpio 107-121 */ - -/* same pin map as above, output enable */ -#define MSM7X00_GPIO_OE_0 MSM_GPIO1_SHADOW_REG(0x10) -#define MSM7X00_GPIO_OE_1 MSM_GPIO2_SHADOW_REG(0x08) -#define MSM7X00_GPIO_OE_2 MSM_GPIO1_SHADOW_REG(0x14) -#define MSM7X00_GPIO_OE_3 MSM_GPIO1_SHADOW_REG(0x18) -#define MSM7X00_GPIO_OE_4 MSM_GPIO1_SHADOW_REG(0x1C) -#define MSM7X00_GPIO_OE_5 MSM_GPIO1_SHADOW_REG(0x54) - -/* same pin map as above, input read */ -#define MSM7X00_GPIO_IN_0 MSM_GPIO1_SHADOW_REG(0x34) -#define MSM7X00_GPIO_IN_1 MSM_GPIO2_SHADOW_REG(0x20) -#define MSM7X00_GPIO_IN_2 MSM_GPIO1_SHADOW_REG(0x38) -#define MSM7X00_GPIO_IN_3 MSM_GPIO1_SHADOW_REG(0x3C) -#define MSM7X00_GPIO_IN_4 MSM_GPIO1_SHADOW_REG(0x40) -#define MSM7X00_GPIO_IN_5 MSM_GPIO1_SHADOW_REG(0x44) - -/* same pin map as above, 1=edge 0=level interrup */ -#define MSM7X00_GPIO_INT_EDGE_0 MSM_GPIO1_SHADOW_REG(0x60) -#define MSM7X00_GPIO_INT_EDGE_1 MSM_GPIO2_SHADOW_REG(0x50) -#define MSM7X00_GPIO_INT_EDGE_2 MSM_GPIO1_SHADOW_REG(0x64) -#define MSM7X00_GPIO_INT_EDGE_3 MSM_GPIO1_SHADOW_REG(0x68) -#define MSM7X00_GPIO_INT_EDGE_4 MSM_GPIO1_SHADOW_REG(0x6C) -#define MSM7X00_GPIO_INT_EDGE_5 MSM_GPIO1_SHADOW_REG(0xC0) - -/* same pin map as above, 1=positive 0=negative */ -#define MSM7X00_GPIO_INT_POS_0 MSM_GPIO1_SHADOW_REG(0x70) -#define MSM7X00_GPIO_INT_POS_1 MSM_GPIO2_SHADOW_REG(0x58) -#define MSM7X00_GPIO_INT_POS_2 MSM_GPIO1_SHADOW_REG(0x74) -#define MSM7X00_GPIO_INT_POS_3 MSM_GPIO1_SHADOW_REG(0x78) -#define MSM7X00_GPIO_INT_POS_4 MSM_GPIO1_SHADOW_REG(0x7C) -#define MSM7X00_GPIO_INT_POS_5 MSM_GPIO1_SHADOW_REG(0xBC) - -/* same pin map as above, interrupt enable */ -#define MSM7X00_GPIO_INT_EN_0 MSM_GPIO1_SHADOW_REG(0x80) -#define MSM7X00_GPIO_INT_EN_1 MSM_GPIO2_SHADOW_REG(0x60) -#define MSM7X00_GPIO_INT_EN_2 MSM_GPIO1_SHADOW_REG(0x84) -#define MSM7X00_GPIO_INT_EN_3 MSM_GPIO1_SHADOW_REG(0x88) -#define MSM7X00_GPIO_INT_EN_4 MSM_GPIO1_SHADOW_REG(0x8C) -#define MSM7X00_GPIO_INT_EN_5 MSM_GPIO1_SHADOW_REG(0xB8) - -/* same pin map as above, write 1 to clear interrupt */ -#define MSM7X00_GPIO_INT_CLEAR_0 MSM_GPIO1_SHADOW_REG(0x90) -#define MSM7X00_GPIO_INT_CLEAR_1 MSM_GPIO2_SHADOW_REG(0x68) -#define MSM7X00_GPIO_INT_CLEAR_2 MSM_GPIO1_SHADOW_REG(0x94) -#define MSM7X00_GPIO_INT_CLEAR_3 MSM_GPIO1_SHADOW_REG(0x98) -#define MSM7X00_GPIO_INT_CLEAR_4 MSM_GPIO1_SHADOW_REG(0x9C) -#define MSM7X00_GPIO_INT_CLEAR_5 MSM_GPIO1_SHADOW_REG(0xB4) - -/* same pin map as above, 1=interrupt pending */ -#define MSM7X00_GPIO_INT_STATUS_0 MSM_GPIO1_SHADOW_REG(0xA0) -#define MSM7X00_GPIO_INT_STATUS_1 MSM_GPIO2_SHADOW_REG(0x70) -#define MSM7X00_GPIO_INT_STATUS_2 MSM_GPIO1_SHADOW_REG(0xA4) -#define MSM7X00_GPIO_INT_STATUS_3 MSM_GPIO1_SHADOW_REG(0xA8) -#define MSM7X00_GPIO_INT_STATUS_4 MSM_GPIO1_SHADOW_REG(0xAC) -#define MSM7X00_GPIO_INT_STATUS_5 MSM_GPIO1_SHADOW_REG(0xB0) - -/* - * QSD8X50 registers - */ -/* output value */ -#define QSD8X50_GPIO_OUT_0 MSM_GPIO1_SHADOW_REG(0x00) /* gpio 15-0 */ -#define QSD8X50_GPIO_OUT_1 MSM_GPIO2_SHADOW_REG(0x00) /* gpio 42-16 */ -#define QSD8X50_GPIO_OUT_2 MSM_GPIO1_SHADOW_REG(0x04) /* gpio 67-43 */ -#define QSD8X50_GPIO_OUT_3 MSM_GPIO1_SHADOW_REG(0x08) /* gpio 94-68 */ -#define QSD8X50_GPIO_OUT_4 MSM_GPIO1_SHADOW_REG(0x0C) /* gpio 103-95 */ -#define QSD8X50_GPIO_OUT_5 MSM_GPIO1_SHADOW_REG(0x10) /* gpio 121-104 */ -#define QSD8X50_GPIO_OUT_6 MSM_GPIO1_SHADOW_REG(0x14) /* gpio 152-122 */ -#define QSD8X50_GPIO_OUT_7 MSM_GPIO1_SHADOW_REG(0x18) /* gpio 164-153 */ - -/* same pin map as above, output enable */ -#define QSD8X50_GPIO_OE_0 MSM_GPIO1_SHADOW_REG(0x20) -#define QSD8X50_GPIO_OE_1 MSM_GPIO2_SHADOW_REG(0x08) -#define QSD8X50_GPIO_OE_2 MSM_GPIO1_SHADOW_REG(0x24) -#define QSD8X50_GPIO_OE_3 MSM_GPIO1_SHADOW_REG(0x28) -#define QSD8X50_GPIO_OE_4 MSM_GPIO1_SHADOW_REG(0x2C) -#define QSD8X50_GPIO_OE_5 MSM_GPIO1_SHADOW_REG(0x30) -#define QSD8X50_GPIO_OE_6 MSM_GPIO1_SHADOW_REG(0x34) -#define QSD8X50_GPIO_OE_7 MSM_GPIO1_SHADOW_REG(0x38) - -/* same pin map as above, input read */ -#define QSD8X50_GPIO_IN_0 MSM_GPIO1_SHADOW_REG(0x50) -#define QSD8X50_GPIO_IN_1 MSM_GPIO2_SHADOW_REG(0x20) -#define QSD8X50_GPIO_IN_2 MSM_GPIO1_SHADOW_REG(0x54) -#define QSD8X50_GPIO_IN_3 MSM_GPIO1_SHADOW_REG(0x58) -#define QSD8X50_GPIO_IN_4 MSM_GPIO1_SHADOW_REG(0x5C) -#define QSD8X50_GPIO_IN_5 MSM_GPIO1_SHADOW_REG(0x60) -#define QSD8X50_GPIO_IN_6 MSM_GPIO1_SHADOW_REG(0x64) -#define QSD8X50_GPIO_IN_7 MSM_GPIO1_SHADOW_REG(0x68) - -/* same pin map as above, 1=edge 0=level interrup */ -#define QSD8X50_GPIO_INT_EDGE_0 MSM_GPIO1_SHADOW_REG(0x70) -#define QSD8X50_GPIO_INT_EDGE_1 MSM_GPIO2_SHADOW_REG(0x50) -#define QSD8X50_GPIO_INT_EDGE_2 MSM_GPIO1_SHADOW_REG(0x74) -#define QSD8X50_GPIO_INT_EDGE_3 MSM_GPIO1_SHADOW_REG(0x78) -#define QSD8X50_GPIO_INT_EDGE_4 MSM_GPIO1_SHADOW_REG(0x7C) -#define QSD8X50_GPIO_INT_EDGE_5 MSM_GPIO1_SHADOW_REG(0x80) -#define QSD8X50_GPIO_INT_EDGE_6 MSM_GPIO1_SHADOW_REG(0x84) -#define QSD8X50_GPIO_INT_EDGE_7 MSM_GPIO1_SHADOW_REG(0x88) - -/* same pin map as above, 1=positive 0=negative */ -#define QSD8X50_GPIO_INT_POS_0 MSM_GPIO1_SHADOW_REG(0x90) -#define QSD8X50_GPIO_INT_POS_1 MSM_GPIO2_SHADOW_REG(0x58) -#define QSD8X50_GPIO_INT_POS_2 MSM_GPIO1_SHADOW_REG(0x94) -#define QSD8X50_GPIO_INT_POS_3 MSM_GPIO1_SHADOW_REG(0x98) -#define QSD8X50_GPIO_INT_POS_4 MSM_GPIO1_SHADOW_REG(0x9C) -#define QSD8X50_GPIO_INT_POS_5 MSM_GPIO1_SHADOW_REG(0xA0) -#define QSD8X50_GPIO_INT_POS_6 MSM_GPIO1_SHADOW_REG(0xA4) -#define QSD8X50_GPIO_INT_POS_7 MSM_GPIO1_SHADOW_REG(0xA8) - -/* same pin map as above, interrupt enable */ -#define QSD8X50_GPIO_INT_EN_0 MSM_GPIO1_SHADOW_REG(0xB0) -#define QSD8X50_GPIO_INT_EN_1 MSM_GPIO2_SHADOW_REG(0x60) -#define QSD8X50_GPIO_INT_EN_2 MSM_GPIO1_SHADOW_REG(0xB4) -#define QSD8X50_GPIO_INT_EN_3 MSM_GPIO1_SHADOW_REG(0xB8) -#define QSD8X50_GPIO_INT_EN_4 MSM_GPIO1_SHADOW_REG(0xBC) -#define QSD8X50_GPIO_INT_EN_5 MSM_GPIO1_SHADOW_REG(0xC0) -#define QSD8X50_GPIO_INT_EN_6 MSM_GPIO1_SHADOW_REG(0xC4) -#define QSD8X50_GPIO_INT_EN_7 MSM_GPIO1_SHADOW_REG(0xC8) - -/* same pin map as above, write 1 to clear interrupt */ -#define QSD8X50_GPIO_INT_CLEAR_0 MSM_GPIO1_SHADOW_REG(0xD0) -#define QSD8X50_GPIO_INT_CLEAR_1 MSM_GPIO2_SHADOW_REG(0x68) -#define QSD8X50_GPIO_INT_CLEAR_2 MSM_GPIO1_SHADOW_REG(0xD4) -#define QSD8X50_GPIO_INT_CLEAR_3 MSM_GPIO1_SHADOW_REG(0xD8) -#define QSD8X50_GPIO_INT_CLEAR_4 MSM_GPIO1_SHADOW_REG(0xDC) -#define QSD8X50_GPIO_INT_CLEAR_5 MSM_GPIO1_SHADOW_REG(0xE0) -#define QSD8X50_GPIO_INT_CLEAR_6 MSM_GPIO1_SHADOW_REG(0xE4) -#define QSD8X50_GPIO_INT_CLEAR_7 MSM_GPIO1_SHADOW_REG(0xE8) - -/* same pin map as above, 1=interrupt pending */ -#define QSD8X50_GPIO_INT_STATUS_0 MSM_GPIO1_SHADOW_REG(0xF0) -#define QSD8X50_GPIO_INT_STATUS_1 MSM_GPIO2_SHADOW_REG(0x70) -#define QSD8X50_GPIO_INT_STATUS_2 MSM_GPIO1_SHADOW_REG(0xF4) -#define QSD8X50_GPIO_INT_STATUS_3 MSM_GPIO1_SHADOW_REG(0xF8) -#define QSD8X50_GPIO_INT_STATUS_4 MSM_GPIO1_SHADOW_REG(0xFC) -#define QSD8X50_GPIO_INT_STATUS_5 MSM_GPIO1_SHADOW_REG(0x100) -#define QSD8X50_GPIO_INT_STATUS_6 MSM_GPIO1_SHADOW_REG(0x104) -#define QSD8X50_GPIO_INT_STATUS_7 MSM_GPIO1_SHADOW_REG(0x108) - -/* - * MSM7X30 registers - */ -/* output value */ -#define MSM7X30_GPIO_OUT_0 MSM_GPIO1_REG(0x00) /* gpio 15-0 */ -#define MSM7X30_GPIO_OUT_1 MSM_GPIO2_REG(0x00) /* gpio 43-16 */ -#define MSM7X30_GPIO_OUT_2 MSM_GPIO1_REG(0x04) /* gpio 67-44 */ -#define MSM7X30_GPIO_OUT_3 MSM_GPIO1_REG(0x08) /* gpio 94-68 */ -#define MSM7X30_GPIO_OUT_4 MSM_GPIO1_REG(0x0C) /* gpio 106-95 */ -#define MSM7X30_GPIO_OUT_5 MSM_GPIO1_REG(0x50) /* gpio 133-107 */ -#define MSM7X30_GPIO_OUT_6 MSM_GPIO1_REG(0xC4) /* gpio 150-134 */ -#define MSM7X30_GPIO_OUT_7 MSM_GPIO1_REG(0x214) /* gpio 181-151 */ - -/* same pin map as above, output enable */ -#define MSM7X30_GPIO_OE_0 MSM_GPIO1_REG(0x10) -#define MSM7X30_GPIO_OE_1 MSM_GPIO2_REG(0x08) -#define MSM7X30_GPIO_OE_2 MSM_GPIO1_REG(0x14) -#define MSM7X30_GPIO_OE_3 MSM_GPIO1_REG(0x18) -#define MSM7X30_GPIO_OE_4 MSM_GPIO1_REG(0x1C) -#define MSM7X30_GPIO_OE_5 MSM_GPIO1_REG(0x54) -#define MSM7X30_GPIO_OE_6 MSM_GPIO1_REG(0xC8) -#define MSM7X30_GPIO_OE_7 MSM_GPIO1_REG(0x218) - -/* same pin map as above, input read */ -#define MSM7X30_GPIO_IN_0 MSM_GPIO1_REG(0x34) -#define MSM7X30_GPIO_IN_1 MSM_GPIO2_REG(0x20) -#define MSM7X30_GPIO_IN_2 MSM_GPIO1_REG(0x38) -#define MSM7X30_GPIO_IN_3 MSM_GPIO1_REG(0x3C) -#define MSM7X30_GPIO_IN_4 MSM_GPIO1_REG(0x40) -#define MSM7X30_GPIO_IN_5 MSM_GPIO1_REG(0x44) -#define MSM7X30_GPIO_IN_6 MSM_GPIO1_REG(0xCC) -#define MSM7X30_GPIO_IN_7 MSM_GPIO1_REG(0x21C) - -/* same pin map as above, 1=edge 0=level interrup */ -#define MSM7X30_GPIO_INT_EDGE_0 MSM_GPIO1_REG(0x60) -#define MSM7X30_GPIO_INT_EDGE_1 MSM_GPIO2_REG(0x50) -#define MSM7X30_GPIO_INT_EDGE_2 MSM_GPIO1_REG(0x64) -#define MSM7X30_GPIO_INT_EDGE_3 MSM_GPIO1_REG(0x68) -#define MSM7X30_GPIO_INT_EDGE_4 MSM_GPIO1_REG(0x6C) -#define MSM7X30_GPIO_INT_EDGE_5 MSM_GPIO1_REG(0xC0) -#define MSM7X30_GPIO_INT_EDGE_6 MSM_GPIO1_REG(0xD0) -#define MSM7X30_GPIO_INT_EDGE_7 MSM_GPIO1_REG(0x240) - -/* same pin map as above, 1=positive 0=negative */ -#define MSM7X30_GPIO_INT_POS_0 MSM_GPIO1_REG(0x70) -#define MSM7X30_GPIO_INT_POS_1 MSM_GPIO2_REG(0x58) -#define MSM7X30_GPIO_INT_POS_2 MSM_GPIO1_REG(0x74) -#define MSM7X30_GPIO_INT_POS_3 MSM_GPIO1_REG(0x78) -#define MSM7X30_GPIO_INT_POS_4 MSM_GPIO1_REG(0x7C) -#define MSM7X30_GPIO_INT_POS_5 MSM_GPIO1_REG(0xBC) -#define MSM7X30_GPIO_INT_POS_6 MSM_GPIO1_REG(0xD4) -#define MSM7X30_GPIO_INT_POS_7 MSM_GPIO1_REG(0x228) - -/* same pin map as above, interrupt enable */ -#define MSM7X30_GPIO_INT_EN_0 MSM_GPIO1_REG(0x80) -#define MSM7X30_GPIO_INT_EN_1 MSM_GPIO2_REG(0x60) -#define MSM7X30_GPIO_INT_EN_2 MSM_GPIO1_REG(0x84) -#define MSM7X30_GPIO_INT_EN_3 MSM_GPIO1_REG(0x88) -#define MSM7X30_GPIO_INT_EN_4 MSM_GPIO1_REG(0x8C) -#define MSM7X30_GPIO_INT_EN_5 MSM_GPIO1_REG(0xB8) -#define MSM7X30_GPIO_INT_EN_6 MSM_GPIO1_REG(0xD8) -#define MSM7X30_GPIO_INT_EN_7 MSM_GPIO1_REG(0x22C) - -/* same pin map as above, write 1 to clear interrupt */ -#define MSM7X30_GPIO_INT_CLEAR_0 MSM_GPIO1_REG(0x90) -#define MSM7X30_GPIO_INT_CLEAR_1 MSM_GPIO2_REG(0x68) -#define MSM7X30_GPIO_INT_CLEAR_2 MSM_GPIO1_REG(0x94) -#define MSM7X30_GPIO_INT_CLEAR_3 MSM_GPIO1_REG(0x98) -#define MSM7X30_GPIO_INT_CLEAR_4 MSM_GPIO1_REG(0x9C) -#define MSM7X30_GPIO_INT_CLEAR_5 MSM_GPIO1_REG(0xB4) -#define MSM7X30_GPIO_INT_CLEAR_6 MSM_GPIO1_REG(0xDC) -#define MSM7X30_GPIO_INT_CLEAR_7 MSM_GPIO1_REG(0x230) - -/* same pin map as above, 1=interrupt pending */ -#define MSM7X30_GPIO_INT_STATUS_0 MSM_GPIO1_REG(0xA0) -#define MSM7X30_GPIO_INT_STATUS_1 MSM_GPIO2_REG(0x70) -#define MSM7X30_GPIO_INT_STATUS_2 MSM_GPIO1_REG(0xA4) -#define MSM7X30_GPIO_INT_STATUS_3 MSM_GPIO1_REG(0xA8) -#define MSM7X30_GPIO_INT_STATUS_4 MSM_GPIO1_REG(0xAC) -#define MSM7X30_GPIO_INT_STATUS_5 MSM_GPIO1_REG(0xB0) -#define MSM7X30_GPIO_INT_STATUS_6 MSM_GPIO1_REG(0xE0) -#define MSM7X30_GPIO_INT_STATUS_7 MSM_GPIO1_REG(0x234) - -#endif From 74d10d7461693ad001f81f0a380b44d526d3f1de Mon Sep 17 00:00:00 2001 From: David Brown Date: Mon, 16 May 2011 13:57:39 -0700 Subject: [PATCH 7/8] gpio_msm: Move Qualcomm v6 MSM driver into drivers Migrate the driver for the v6-based MSM chips into drivers/gpio. The driver is unchanged, only moved. Change-Id: I03ba597b95b4d62b42da112a8efac88d67aa40f9 Signed-off-by: David Brown Acked-by: Linus Walleij Acked-by: Nicolas Pitre --- arch/arm/mach-msm/Kconfig | 3 +++ arch/arm/mach-msm/Makefile | 2 -- drivers/gpio/Kconfig | 8 ++++++++ drivers/gpio/Makefile | 1 + arch/arm/mach-msm/gpio.c => drivers/gpio/gpio-msm-v1.c | 5 ++--- 5 files changed, 14 insertions(+), 5 deletions(-) rename arch/arm/mach-msm/gpio.c => drivers/gpio/gpio-msm-v1.c (99%) diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig index 1516896e8d17..cc7c0b21e2b8 100644 --- a/arch/arm/mach-msm/Kconfig +++ b/arch/arm/mach-msm/Kconfig @@ -11,6 +11,7 @@ config ARCH_MSM7X00A select MSM_SMD select MSM_SMD_PKG3 select CPU_V6 + select GPIO_MSM_V1 select MSM_PROC_COMM select HAS_MSM_DEBUG_UART_PHYS @@ -22,6 +23,7 @@ config ARCH_MSM7X30 select MSM_VIC select CPU_V7 select MSM_GPIOMUX + select GPIO_MSM_V1 select MSM_PROC_COMM select HAS_MSM_DEBUG_UART_PHYS @@ -33,6 +35,7 @@ config ARCH_QSD8X50 select MSM_VIC select CPU_V7 select MSM_GPIOMUX + select GPIO_MSM_V1 select MSM_PROC_COMM select HAS_MSM_DEBUG_UART_PHYS diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile index 9519fd28a025..c0709afd2130 100644 --- a/arch/arm/mach-msm/Makefile +++ b/arch/arm/mach-msm/Makefile @@ -34,6 +34,4 @@ ifndef CONFIG_ARCH_MSM8960 # TODO: TLMM Mapping issues need to be resolved obj-y += gpio-v2.o endif -else -obj-y += gpio.o endif diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 2967002a9f82..382c67c66070 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -90,6 +90,14 @@ config GPIO_EXYNOS4 def_bool y depends on CPU_EXYNOS4210 +config GPIO_MSM_V1 + tristate "Qualcomm MSM GPIO v1" + depends on GPIOLIB && ARCH_MSM + help + Say yes here to support the GPIO interface on ARM v6 based + Qualcomm MSM chips. Most of the pins on the MSM can be + selected for GPIO, and are controlled by this driver. + config GPIO_PLAT_SAMSUNG def_bool y depends on SAMSUNG_GPIOLIB_4BIT diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index b605f8ec6fbe..72d4e5056773 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_GPIO_MAX7301) += max7301.o obj-$(CONFIG_GPIO_MAX732X) += max732x.o obj-$(CONFIG_GPIO_MC33880) += mc33880.o obj-$(CONFIG_GPIO_MCP23S08) += mcp23s08.o +obj-$(CONFIG_GPIO_MSM_V1) += gpio-msm-v1.o obj-$(CONFIG_GPIO_74X164) += 74x164.o obj-$(CONFIG_ARCH_OMAP) += gpio-omap.o obj-$(CONFIG_GPIO_PCA953X) += pca953x.o diff --git a/arch/arm/mach-msm/gpio.c b/drivers/gpio/gpio-msm-v1.c similarity index 99% rename from arch/arm/mach-msm/gpio.c rename to drivers/gpio/gpio-msm-v1.c index 3bbf50ed2b42..52a4d4286eba 100644 --- a/arch/arm/mach-msm/gpio.c +++ b/drivers/gpio/gpio-msm-v1.c @@ -1,7 +1,6 @@ -/* linux/arch/arm/mach-msm/gpio.c - * +/* * Copyright (C) 2007 Google, Inc. - * Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved. + * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and From 1a5ab4b3e6087726dfc00207b36c91d3061468e8 Mon Sep 17 00:00:00 2001 From: David Brown Date: Mon, 16 May 2011 15:53:38 -0700 Subject: [PATCH 8/8] gpio_msm: Move Qualcomm MSM v2 gpio driver into drivers Migrate the driver for the v7-based MSM chips into drivers/gpio. The driver is unchanged, only moved. Change-Id: I810db5b50b71cdca4e869aa0d0310f7f48781a55 Signed-off-by: David Brown Acked-by: Linus Walleij Acked-by: Nicolas Pitre --- arch/arm/mach-msm/Kconfig | 1 + arch/arm/mach-msm/Makefile | 6 ------ drivers/gpio/Kconfig | 8 ++++++++ drivers/gpio/Makefile | 1 + arch/arm/mach-msm/gpio-v2.c => drivers/gpio/gpio-msm-v2.c | 4 ++-- 5 files changed, 12 insertions(+), 8 deletions(-) rename arch/arm/mach-msm/gpio-v2.c => drivers/gpio/gpio-msm-v2.c (99%) diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig index cc7c0b21e2b8..f5cce3fe351a 100644 --- a/arch/arm/mach-msm/Kconfig +++ b/arch/arm/mach-msm/Kconfig @@ -47,6 +47,7 @@ config ARCH_MSM8X60 select ARM_GIC select CPU_V7 select MSM_V2_TLMM + select GPIO_MSM_V2 select MSM_GPIOMUX select MSM_SCM if SMP diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile index c0709afd2130..7a227d1c144d 100644 --- a/arch/arm/mach-msm/Makefile +++ b/arch/arm/mach-msm/Makefile @@ -29,9 +29,3 @@ obj-$(CONFIG_ARCH_MSM8960) += board-msm8960.o devices-msm8960.o obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-v1.o gpiomux.o obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o gpiomux-v1.o gpiomux.o obj-$(CONFIG_ARCH_MSM8X60) += gpiomux-8x60.o gpiomux-v2.o gpiomux.o -ifdef CONFIG_MSM_V2_TLMM -ifndef CONFIG_ARCH_MSM8960 -# TODO: TLMM Mapping issues need to be resolved -obj-y += gpio-v2.o -endif -endif diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 382c67c66070..30e14e8b5bc1 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -98,6 +98,14 @@ config GPIO_MSM_V1 Qualcomm MSM chips. Most of the pins on the MSM can be selected for GPIO, and are controlled by this driver. +config GPIO_MSM_V2 + tristate "Qualcomm MSM GPIO v2" + depends on GPIOLIB && ARCH_MSM + help + Say yes here to support the GPIO interface on ARM v7 based + Qualcomm MSM chips. Most of the pins on the MSM can be + selected for GPIO, and are controlled by this driver. + config GPIO_PLAT_SAMSUNG def_bool y depends on SAMSUNG_GPIOLIB_4BIT diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 72d4e5056773..3efbb995623f 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_GPIO_MAX732X) += max732x.o obj-$(CONFIG_GPIO_MC33880) += mc33880.o obj-$(CONFIG_GPIO_MCP23S08) += mcp23s08.o obj-$(CONFIG_GPIO_MSM_V1) += gpio-msm-v1.o +obj-$(CONFIG_GPIO_MSM_V2) += gpio-msm-v2.o obj-$(CONFIG_GPIO_74X164) += 74x164.o obj-$(CONFIG_ARCH_OMAP) += gpio-omap.o obj-$(CONFIG_GPIO_PCA953X) += pca953x.o diff --git a/arch/arm/mach-msm/gpio-v2.c b/drivers/gpio/gpio-msm-v2.c similarity index 99% rename from arch/arm/mach-msm/gpio-v2.c rename to drivers/gpio/gpio-msm-v2.c index cc9c4fd7cccc..5cb1227d69cf 100644 --- a/arch/arm/mach-msm/gpio-v2.c +++ b/drivers/gpio/gpio-msm-v2.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. +/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -30,8 +30,8 @@ #include +#include #include -#include "gpiomux.h" /* Bits of interest in the GPIO_IN_OUT register. */