Merge branches 'sh/serial-rework' and 'sh/oprofile'
This commit is contained in:
commit
86d758ef2c
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@ -255,10 +255,9 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
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return -ENODEV;
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return -ENODEV;
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ops = &sh7750_perf_counter_ops;
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ops = &sh7750_perf_counter_ops;
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ops->cpu_type = (char *)get_cpu_subtype(¤t_cpu_data);
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ops->cpu_type = "sh/sh7750";
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printk(KERN_INFO "oprofile: using SH-4 (%s) performance monitoring.\n",
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printk(KERN_INFO "oprofile: using SH-4 performance monitoring.\n");
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sh7750_perf_counter_ops.cpu_type);
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/* Clear the counters */
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/* Clear the counters */
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ctrl_outw(ctrl_inw(PMCR1) | PMCR_PMCLR, PMCR1);
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ctrl_outw(ctrl_inw(PMCR1) | PMCR_PMCLR, PMCR1);
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@ -270,4 +269,3 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
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void oprofile_arch_exit(void)
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void oprofile_arch_exit(void)
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{
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{
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}
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}
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@ -250,8 +250,7 @@ static inline void h8300_sci_disable(struct uart_port *port)
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}
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}
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#endif
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#endif
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#if defined(SCI_ONLY) || defined(SCI_AND_SCIF) && \
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#if defined(__H8300H__) || defined(__H8300S__)
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defined(__H8300H__) || defined(__H8300S__)
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static void sci_init_pins_sci(struct uart_port* port, unsigned int cflag)
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static void sci_init_pins_sci(struct uart_port* port, unsigned int cflag)
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{
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{
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int ch = (port->mapbase - SMR0) >> 3;
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int ch = (port->mapbase - SMR0) >> 3;
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@ -285,11 +284,6 @@ static void sci_init_pins_irda(struct uart_port *port, unsigned int cflag)
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#define sci_init_pins_irda NULL
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#define sci_init_pins_irda NULL
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#endif
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#endif
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#ifdef SCI_ONLY
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#define sci_init_pins_scif NULL
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#endif
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#if defined(SCIF_ONLY) || defined(SCI_AND_SCIF)
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#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
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#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
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static void sci_init_pins_scif(struct uart_port* port, unsigned int cflag)
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static void sci_init_pins_scif(struct uart_port* port, unsigned int cflag)
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{
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{
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@ -449,7 +443,6 @@ static inline int scif_rxroom(struct uart_port *port)
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return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
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return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
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}
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}
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#endif
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#endif
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#endif /* SCIF_ONLY || SCI_AND_SCIF */
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static inline int sci_txroom(struct uart_port *port)
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static inline int sci_txroom(struct uart_port *port)
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{
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{
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@ -485,11 +478,9 @@ static void sci_transmit_chars(struct uart_port *port)
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return;
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return;
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}
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}
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#ifndef SCI_ONLY
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if (port->type == PORT_SCIF)
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if (port->type == PORT_SCIF)
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count = scif_txroom(port);
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count = scif_txroom(port);
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else
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else
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#endif
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count = sci_txroom(port);
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count = sci_txroom(port);
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do {
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do {
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@ -519,12 +510,10 @@ static void sci_transmit_chars(struct uart_port *port)
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} else {
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} else {
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ctrl = sci_in(port, SCSCR);
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ctrl = sci_in(port, SCSCR);
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#if !defined(SCI_ONLY)
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if (port->type == PORT_SCIF) {
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if (port->type == PORT_SCIF) {
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sci_in(port, SCxSR); /* Dummy read */
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sci_in(port, SCxSR); /* Dummy read */
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sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
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sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
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}
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}
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#endif
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ctrl |= SCI_CTRL_FLAGS_TIE;
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ctrl |= SCI_CTRL_FLAGS_TIE;
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sci_out(port, SCSCR, ctrl);
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sci_out(port, SCSCR, ctrl);
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@ -547,11 +536,9 @@ static inline void sci_receive_chars(struct uart_port *port)
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return;
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return;
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while (1) {
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while (1) {
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#if !defined(SCI_ONLY)
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if (port->type == PORT_SCIF)
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if (port->type == PORT_SCIF)
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count = scif_rxroom(port);
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count = scif_rxroom(port);
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else
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else
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#endif
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count = sci_rxroom(port);
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count = sci_rxroom(port);
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/* Don't copy more bytes than there is room for in the buffer */
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/* Don't copy more bytes than there is room for in the buffer */
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@ -1054,10 +1041,8 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
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sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
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sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
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#if !defined(SCI_ONLY)
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if (port->type == PORT_SCIF)
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if (port->type == PORT_SCIF)
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sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
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sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
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#endif
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smr_val = sci_in(port, SCSMR) & 3;
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smr_val = sci_in(port, SCSMR) & 3;
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if ((termios->c_cflag & CSIZE) == CS7)
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if ((termios->c_cflag & CSIZE) == CS7)
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@ -16,7 +16,6 @@
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# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
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# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
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# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
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# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
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# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
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# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
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# define SCI_AND_SCIF
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#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
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#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
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# define SCIF0 0xA4400000
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# define SCIF0 0xA4400000
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# define SCIF2 0xA4410000
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# define SCIF2 0xA4410000
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@ -30,17 +29,14 @@
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* SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
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* SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
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*/
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*/
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# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
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# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
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# define SCIF_ONLY
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#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
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#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
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defined(CONFIG_CPU_SUBTYPE_SH7721)
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defined(CONFIG_CPU_SUBTYPE_SH7721)
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# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
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# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
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# define SCIF_ONLY
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#define SCIF_ORER 0x0200 /* overrun error bit */
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#define SCIF_ORER 0x0200 /* overrun error bit */
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#elif defined(CONFIG_SH_RTS7751R2D)
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#elif defined(CONFIG_SH_RTS7751R2D)
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# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
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# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
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# define SCIF_ORER 0x0001 /* overrun error bit */
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# define SCIF_ORER 0x0001 /* overrun error bit */
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# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
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# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
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# define SCIF_ONLY
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#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
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#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
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defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
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defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
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defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
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defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
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@ -53,28 +49,24 @@
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# define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
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# define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
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0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
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0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
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0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
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0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
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# define SCI_AND_SCIF
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#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
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#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
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# define SCSPTR0 0xfe600024 /* 16 bit SCIF */
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# define SCSPTR0 0xfe600024 /* 16 bit SCIF */
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# define SCSPTR1 0xfe610024 /* 16 bit SCIF */
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# define SCSPTR1 0xfe610024 /* 16 bit SCIF */
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# define SCSPTR2 0xfe620024 /* 16 bit SCIF */
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# define SCSPTR2 0xfe620024 /* 16 bit SCIF */
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# define SCIF_ORER 0x0001 /* overrun error bit */
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# define SCIF_ORER 0x0001 /* overrun error bit */
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# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
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# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
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# define SCIF_ONLY
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#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
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#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
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# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
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# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
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# define SCIF_ORER 0x0001 /* overrun error bit */
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# define SCIF_ORER 0x0001 /* overrun error bit */
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# define PACR 0xa4050100
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# define PACR 0xa4050100
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# define PBCR 0xa4050102
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# define PBCR 0xa4050102
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# define SCSCR_INIT(port) 0x3B
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# define SCSCR_INIT(port) 0x3B
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# define SCIF_ONLY
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#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
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#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
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# define SCSPTR0 0xffe00010 /* 16 bit SCIF */
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# define SCSPTR0 0xffe00010 /* 16 bit SCIF */
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# define SCSPTR1 0xffe10010 /* 16 bit SCIF */
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# define SCSPTR1 0xffe10010 /* 16 bit SCIF */
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# define SCSPTR2 0xffe20010 /* 16 bit SCIF */
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# define SCSPTR2 0xffe20010 /* 16 bit SCIF */
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# define SCSPTR3 0xffe30010 /* 16 bit SCIF */
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# define SCSPTR3 0xffe30010 /* 16 bit SCIF */
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# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
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# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
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# define SCIF_ONLY
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#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
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#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
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# define PADR 0xA4050120
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# define PADR 0xA4050120
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# define PSDR 0xA405013e
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# define PSDR 0xA405013e
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@ -82,7 +74,6 @@
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# define PSCR 0xA405011E
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# define PSCR 0xA405011E
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# define SCIF_ORER 0x0001 /* overrun error bit */
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# define SCIF_ORER 0x0001 /* overrun error bit */
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# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
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# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
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# define SCIF_ONLY
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#elif defined(CONFIG_CPU_SUBTYPE_SH7366)
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#elif defined(CONFIG_CPU_SUBTYPE_SH7366)
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# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
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# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
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# define SCSPTR0 SCPDR0
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# define SCSPTR0 SCPDR0
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@ -98,12 +89,10 @@
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# define SCSPTR5 0xa4050128
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# define SCSPTR5 0xa4050128
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# define SCIF_ORER 0x0001 /* overrun error bit */
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# define SCIF_ORER 0x0001 /* overrun error bit */
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# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
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# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
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# define SCIF_ONLY
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#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
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#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
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# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
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# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
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# define SCIF_ORER 0x0001 /* overrun error bit */
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# define SCIF_ORER 0x0001 /* overrun error bit */
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# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
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# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
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# define SCIF_ONLY
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#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
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#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
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# define SCIF_BASE_ADDR 0x01030000
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# define SCIF_BASE_ADDR 0x01030000
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# define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR
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# define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR
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@ -112,14 +101,11 @@
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# define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
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# define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
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# define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
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# define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
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# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */
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# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */
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# define SCIF_ONLY
|
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#elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
|
#elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
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||||||
# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
|
# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
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||||||
# define SCI_ONLY
|
|
||||||
# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
|
# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
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||||||
#elif defined(CONFIG_H8S2678)
|
#elif defined(CONFIG_H8S2678)
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||||||
# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
|
# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
|
||||||
# define SCI_ONLY
|
|
||||||
# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
|
# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
|
||||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
|
#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
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# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
|
# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
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||||||
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@ -127,20 +113,17 @@
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||||||
# define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */
|
# define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */
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||||||
# define SCIF_ORER 0x0001 /* overrun error bit */
|
# define SCIF_ORER 0x0001 /* overrun error bit */
|
||||||
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
|
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
|
||||||
# define SCIF_ONLY
|
|
||||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
|
#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
|
||||||
# define SCSPTR0 0xff923020 /* 16 bit SCIF */
|
# define SCSPTR0 0xff923020 /* 16 bit SCIF */
|
||||||
# define SCSPTR1 0xff924020 /* 16 bit SCIF */
|
# define SCSPTR1 0xff924020 /* 16 bit SCIF */
|
||||||
# define SCSPTR2 0xff925020 /* 16 bit SCIF */
|
# define SCSPTR2 0xff925020 /* 16 bit SCIF */
|
||||||
# define SCIF_ORER 0x0001 /* overrun error bit */
|
# define SCIF_ORER 0x0001 /* overrun error bit */
|
||||||
# define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
|
# define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
|
||||||
# define SCIF_ONLY
|
|
||||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
|
#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
|
||||||
# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
|
# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
|
||||||
# define SCSPTR1 0xffe10024 /* 16 bit SCIF */
|
# define SCSPTR1 0xffe10024 /* 16 bit SCIF */
|
||||||
# define SCIF_ORER 0x0001 /* Overrun error bit */
|
# define SCIF_ORER 0x0001 /* Overrun error bit */
|
||||||
# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
|
# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
|
||||||
# define SCIF_ONLY
|
|
||||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
|
#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
|
||||||
# define SCSPTR0 0xffea0024 /* 16 bit SCIF */
|
# define SCSPTR0 0xffea0024 /* 16 bit SCIF */
|
||||||
# define SCSPTR1 0xffeb0024 /* 16 bit SCIF */
|
# define SCSPTR1 0xffeb0024 /* 16 bit SCIF */
|
||||||
|
@ -150,7 +133,6 @@
|
||||||
# define SCSPTR5 0xffef0024 /* 16 bit SCIF */
|
# define SCSPTR5 0xffef0024 /* 16 bit SCIF */
|
||||||
# define SCIF_OPER 0x0001 /* Overrun error bit */
|
# define SCIF_OPER 0x0001 /* Overrun error bit */
|
||||||
# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
|
# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
|
||||||
# define SCIF_ONLY
|
|
||||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \
|
#elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \
|
||||||
defined(CONFIG_CPU_SUBTYPE_SH7206) || \
|
defined(CONFIG_CPU_SUBTYPE_SH7206) || \
|
||||||
defined(CONFIG_CPU_SUBTYPE_SH7263)
|
defined(CONFIG_CPU_SUBTYPE_SH7263)
|
||||||
|
@ -159,14 +141,12 @@
|
||||||
# define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
|
# define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
|
||||||
# define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
|
# define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
|
||||||
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
|
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
|
||||||
# define SCIF_ONLY
|
|
||||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
|
#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
|
||||||
# define SCSPTR0 0xf8400020 /* 16 bit SCIF */
|
# define SCSPTR0 0xf8400020 /* 16 bit SCIF */
|
||||||
# define SCSPTR1 0xf8410020 /* 16 bit SCIF */
|
# define SCSPTR1 0xf8410020 /* 16 bit SCIF */
|
||||||
# define SCSPTR2 0xf8420020 /* 16 bit SCIF */
|
# define SCSPTR2 0xf8420020 /* 16 bit SCIF */
|
||||||
# define SCIF_ORER 0x0001 /* overrun error bit */
|
# define SCIF_ORER 0x0001 /* overrun error bit */
|
||||||
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
|
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
|
||||||
# define SCIF_ONLY
|
|
||||||
#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
|
#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
|
||||||
# define SCSPTR0 0xffc30020 /* 16 bit SCIF */
|
# define SCSPTR0 0xffc30020 /* 16 bit SCIF */
|
||||||
# define SCSPTR1 0xffc40020 /* 16 bit SCIF */
|
# define SCSPTR1 0xffc40020 /* 16 bit SCIF */
|
||||||
|
@ -174,7 +154,6 @@
|
||||||
# define SCSPTR3 0xffc60020 /* 16 bit SCIF */
|
# define SCSPTR3 0xffc60020 /* 16 bit SCIF */
|
||||||
# define SCIF_ORER 0x0001 /* Overrun error bit */
|
# define SCIF_ORER 0x0001 /* Overrun error bit */
|
||||||
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
|
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
|
||||||
# define SCIF_ONLY
|
|
||||||
#else
|
#else
|
||||||
# error CPU subtype not defined
|
# error CPU subtype not defined
|
||||||
#endif
|
#endif
|
||||||
|
@ -245,55 +224,28 @@
|
||||||
# define SCIF_TXROOM_MAX 16
|
# define SCIF_TXROOM_MAX 16
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if defined(SCI_ONLY)
|
#define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
|
||||||
# define SCxSR_TEND(port) SCI_TEND
|
#define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
|
||||||
# define SCxSR_ERRORS(port) SCI_ERRORS
|
#define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
|
||||||
# define SCxSR_RDxF(port) SCI_RDRF
|
#define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
|
||||||
# define SCxSR_TDxE(port) SCI_TDRE
|
#define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
|
||||||
# define SCxSR_ORER(port) SCI_ORER
|
#define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
|
||||||
# define SCxSR_FER(port) SCI_FER
|
#define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
|
||||||
# define SCxSR_PER(port) SCI_PER
|
|
||||||
# define SCxSR_BRK(port) 0x00
|
|
||||||
# define SCxSR_RDxF_CLEAR(port) 0xbc
|
|
||||||
# define SCxSR_ERROR_CLEAR(port) 0xc4
|
|
||||||
# define SCxSR_TDxE_CLEAR(port) 0x78
|
|
||||||
# define SCxSR_BREAK_CLEAR(port) 0xc4
|
|
||||||
#elif defined(SCIF_ONLY)
|
|
||||||
# define SCxSR_TEND(port) SCIF_TEND
|
|
||||||
# define SCxSR_ERRORS(port) SCIF_ERRORS
|
|
||||||
# define SCxSR_RDxF(port) SCIF_RDF
|
|
||||||
# define SCxSR_TDxE(port) SCIF_TDFE
|
|
||||||
#if defined(CONFIG_CPU_SUBTYPE_SH7705)
|
#if defined(CONFIG_CPU_SUBTYPE_SH7705)
|
||||||
# define SCxSR_ORER(port) SCIF_ORER
|
# define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER)
|
||||||
#else
|
#else
|
||||||
# define SCxSR_ORER(port) 0x0000
|
# define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : 0x0000)
|
||||||
#endif
|
#endif
|
||||||
# define SCxSR_FER(port) SCIF_FER
|
|
||||||
# define SCxSR_PER(port) SCIF_PER
|
|
||||||
# define SCxSR_BRK(port) SCIF_BRK
|
|
||||||
#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
|
#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
|
||||||
defined(CONFIG_CPU_SUBTYPE_SH7720) || \
|
defined(CONFIG_CPU_SUBTYPE_SH7720) || \
|
||||||
defined(CONFIG_CPU_SUBTYPE_SH7721)
|
defined(CONFIG_CPU_SUBTYPE_SH7721)
|
||||||
# define SCxSR_RDxF_CLEAR(port) (sci_in(port,SCxSR)&0xfffc)
|
# define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc)
|
||||||
# define SCxSR_ERROR_CLEAR(port) (sci_in(port,SCxSR)&0xfd73)
|
# define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73)
|
||||||
# define SCxSR_TDxE_CLEAR(port) (sci_in(port,SCxSR)&0xffdf)
|
# define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf)
|
||||||
# define SCxSR_BREAK_CLEAR(port) (sci_in(port,SCxSR)&0xffe3)
|
# define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3)
|
||||||
#else
|
#else
|
||||||
/* SH7705 can also use this, clearing is same between 7705 and 7709 */
|
|
||||||
# define SCxSR_RDxF_CLEAR(port) 0x00fc
|
|
||||||
# define SCxSR_ERROR_CLEAR(port) 0x0073
|
|
||||||
# define SCxSR_TDxE_CLEAR(port) 0x00df
|
|
||||||
# define SCxSR_BREAK_CLEAR(port) 0x00e3
|
|
||||||
#endif
|
|
||||||
#else
|
|
||||||
# define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
|
|
||||||
# define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
|
|
||||||
# define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
|
|
||||||
# define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
|
|
||||||
# define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : 0x0000)
|
|
||||||
# define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
|
|
||||||
# define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
|
|
||||||
# define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
|
|
||||||
# define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
|
# define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
|
||||||
# define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
|
# define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
|
||||||
# define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
|
# define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
|
||||||
|
@ -579,14 +531,10 @@ static inline int sci_rxd_in(struct uart_port *port)
|
||||||
defined(CONFIG_CPU_SUBTYPE_SH4_202)
|
defined(CONFIG_CPU_SUBTYPE_SH4_202)
|
||||||
static inline int sci_rxd_in(struct uart_port *port)
|
static inline int sci_rxd_in(struct uart_port *port)
|
||||||
{
|
{
|
||||||
#ifndef SCIF_ONLY
|
|
||||||
if (port->mapbase == 0xffe00000)
|
if (port->mapbase == 0xffe00000)
|
||||||
return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
|
return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
|
||||||
#endif
|
|
||||||
#ifndef SCI_ONLY
|
|
||||||
if (port->mapbase == 0xffe80000)
|
if (port->mapbase == 0xffe80000)
|
||||||
return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
|
return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
|
||||||
#endif
|
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
|
#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
|
||||||
|
|
Loading…
Reference in New Issue