Merge branch 'for-upstream/juno-pcie' of git://linux-arm.org/linux-ld into next/arm64
* 'for-upstream/juno-pcie' of git://linux-arm.org/linux-ld: arm64: defconfig: Enable PCI generic host bridge by default arm64: Juno: Add support for the PCIe host bridge on Juno R1 Documentation: of: Document the bindings used by Juno R1 PCIe host bridge Signed-off-by: Olof Johansson <olof@lixom.net>
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* ARM Juno R1 PCIe interface
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This PCIe host controller is based on PLDA XpressRICH3-AXI IP
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and thus inherits all the common properties defined in plda,xpressrich3-axi.txt
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as well as the base properties defined in host-generic-pci.txt.
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Required properties:
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- compatible: "arm,juno-r1-pcie"
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- dma-coherent: The host controller bridges the AXI transactions into PCIe bus
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in a manner that makes the DMA operations to appear coherent to the CPUs.
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* PLDA XpressRICH3-AXI host controller
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The PLDA XpressRICH3-AXI host controller can be configured in a manner that
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makes it compliant with the SBSA[1] standard published by ARM Ltd. For those
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scenarios, the host-generic-pci.txt bindings apply with the following additions
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to the compatible property:
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Required properties:
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- compatible: should contain "plda,xpressrich3-axi" to identify the IP used.
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[1] http://infocenter.arm.com/help/topic/com.arm.doc.den0029a/
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@ -168,6 +168,7 @@ pericom Pericom Technology Inc.
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phytec PHYTEC Messtechnik GmbH
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picochip Picochip Ltd
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plathome Plat'Home Co., Ltd.
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plda PLDA
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pixcir PIXCIR MICROELECTRONICS Co., Ltd
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powervr PowerVR (deprecated, use img)
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qca Qualcomm Atheros, Inc.
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@ -109,6 +109,26 @@
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#include "juno-base.dtsi"
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pcie-controller@40000000 {
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compatible = "arm,juno-r1-pcie", "plda,xpressrich3-axi", "pci-host-ecam-generic";
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device_type = "pci";
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reg = <0 0x40000000 0 0x10000000>; /* ECAM config space */
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bus-range = <0 255>;
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linux,pci-domain = <0>;
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#address-cells = <3>;
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#size-cells = <2>;
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dma-coherent;
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ranges = <0x01000000 0x00 0x5f800000 0x00 0x5f800000 0x0 0x00800000>,
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<0x02000000 0x00 0x50000000 0x00 0x50000000 0x0 0x08000000>,
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<0x42000000 0x40 0x00000000 0x40 0x00000000 0x1 0x00000000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &gic 0 0 0 136 4>,
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<0 0 0 2 &gic 0 0 0 137 4>,
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<0 0 0 3 &gic 0 0 0 138 4>,
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<0 0 0 4 &gic 0 0 0 139 4>;
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msi-parent = <&v2m_0>;
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};
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};
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&memtimer {
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@ -49,6 +49,7 @@ CONFIG_ARCH_XGENE=y
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CONFIG_ARCH_ZYNQMP=y
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CONFIG_PCI=y
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CONFIG_PCI_MSI=y
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CONFIG_PCI_HOST_GENERIC=y
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CONFIG_PCI_XGENE=y
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CONFIG_SMP=y
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CONFIG_PREEMPT=y
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