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drm/i915: Do not rely on wm preservation for ILK watermarks

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The original intent was to preserve watermarks as much as possible
in intel_pipe_wm.raw_wm, and put the validated ones in intel_pipe_wm.wm.

It seems this approach is insufficient and we don't always preserve
the raw watermarks, so just use the atomic iterator we're already using
to get a const pointer to all bound planes on the crtc.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102373
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: stable@vger.kernel.org #v4.8+
Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171019151341.4579-1-maarten.lankhorst@linux.intel.com
(cherry picked from commit 28283f4f35)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This commit is contained in:
Maarten Lankhorst 2017-10-19 17:13:40 +02:00 committed by Rodrigo Vivi
parent 713946d16f
commit 8777b927b9
2 changed files with 21 additions and 31 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/gpu/drm/i915/intel_drv.h
View File

@ -496,7 +496,6 @@ struct intel_crtc_scaler_state {
struct intel_pipe_wm { struct intel_pipe_wm {
struct intel_wm_level wm[5]; struct intel_wm_level wm[5];
struct intel_wm_level raw_wm[5];
uint32_t linetime; uint32_t linetime;
bool fbc_wm_enabled; bool fbc_wm_enabled;
bool pipe_enabled; bool pipe_enabled;

51
drivers/gpu/drm/i915/intel_pm.c
View File

@ -2716,9 +2716,9 @@ static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
const struct intel_crtc *intel_crtc, const struct intel_crtc *intel_crtc,
int level, int level,
struct intel_crtc_state *cstate, struct intel_crtc_state *cstate,
struct intel_plane_state *pristate, const struct intel_plane_state *pristate,
struct intel_plane_state *sprstate, const struct intel_plane_state *sprstate,
struct intel_plane_state *curstate, const struct intel_plane_state *curstate,
struct intel_wm_level *result) struct intel_wm_level *result)
{ {
uint16_t pri_latency = dev_priv->wm.pri_latency[level]; uint16_t pri_latency = dev_priv->wm.pri_latency[level];
@ -3038,28 +3038,24 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
struct intel_pipe_wm *pipe_wm; struct intel_pipe_wm *pipe_wm;
struct drm_device *dev = state->dev; struct drm_device *dev = state->dev;
const struct drm_i915_private *dev_priv = to_i915(dev); const struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_plane *intel_plane; struct drm_plane *plane;
struct intel_plane_state *pristate = NULL; const struct drm_plane_state *plane_state;
struct intel_plane_state *sprstate = NULL; const struct intel_plane_state *pristate = NULL;
struct intel_plane_state *curstate = NULL; const struct intel_plane_state *sprstate = NULL;
const struct intel_plane_state *curstate = NULL;
int level, max_level = ilk_wm_max_level(dev_priv), usable_level; int level, max_level = ilk_wm_max_level(dev_priv), usable_level;
struct ilk_wm_maximums max; struct ilk_wm_maximums max;
pipe_wm = &cstate->wm.ilk.optimal; pipe_wm = &cstate->wm.ilk.optimal;
for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, &cstate->base) {
struct intel_plane_state *ps; const struct intel_plane_state *ps = to_intel_plane_state(plane_state);
ps = intel_atomic_get_existing_plane_state(state, if (plane->type == DRM_PLANE_TYPE_PRIMARY)
intel_plane);
if (!ps)
continue;
if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
pristate = ps; pristate = ps;
else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY) else if (plane->type == DRM_PLANE_TYPE_OVERLAY)
sprstate = ps; sprstate = ps;
else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR) else if (plane->type == DRM_PLANE_TYPE_CURSOR)
curstate = ps; curstate = ps;
} }
@ -3081,11 +3077,9 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
if (pipe_wm->sprites_scaled) if (pipe_wm->sprites_scaled)
usable_level = 0; usable_level = 0;
ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm)); memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
pipe_wm->wm[0] = pipe_wm->raw_wm[0]; ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
pristate, sprstate, curstate, &pipe_wm->wm[0]);
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
pipe_wm->linetime = hsw_compute_linetime_wm(cstate); pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
@ -3095,8 +3089,8 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
ilk_compute_wm_reg_maximums(dev_priv, 1, &max); ilk_compute_wm_reg_maximums(dev_priv, 1, &max);
for (level = 1; level <= max_level; level++) { for (level = 1; level <= usable_level; level++) {
struct intel_wm_level *wm = &pipe_wm->raw_wm[level]; struct intel_wm_level *wm = &pipe_wm->wm[level];
ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate, ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
pristate, sprstate, curstate, wm); pristate, sprstate, curstate, wm);
@ -3106,13 +3100,10 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
* register maximums since such watermarks are * register maximums since such watermarks are
* always invalid. * always invalid.
*/ */
if (level > usable_level) if (!ilk_validate_wm_level(level, &max, wm)) {
continue; memset(wm, 0, sizeof(*wm));
break;
if (ilk_validate_wm_level(level, &max, wm)) }
pipe_wm->wm[level] = *wm;
else
usable_level = level;
} }
return 0; return 0;