amd64_edac: Simplify scrubrate setting
Drop per-instance variable and compute min scrubrate dynamically. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
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cb293250c7
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@ -193,8 +193,12 @@ static int __amd64_set_scrub_rate(struct pci_dev *ctl, u32 new_bw, u32 min_rate)
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static int amd64_set_scrub_rate(struct mem_ctl_info *mci, u32 bw)
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static int amd64_set_scrub_rate(struct mem_ctl_info *mci, u32 bw)
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{
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{
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struct amd64_pvt *pvt = mci->pvt_info;
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struct amd64_pvt *pvt = mci->pvt_info;
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u32 min_scrubrate = 0x5;
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return __amd64_set_scrub_rate(pvt->F3, bw, pvt->min_scrubrate);
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if (boot_cpu_data.x86 == 0xf)
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min_scrubrate = 0x0;
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return __amd64_set_scrub_rate(pvt->F3, bw, min_scrubrate);
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}
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}
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static int amd64_get_scrub_rate(struct mem_ctl_info *mci)
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static int amd64_get_scrub_rate(struct mem_ctl_info *mci)
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@ -2399,13 +2403,11 @@ static struct amd64_family_type *amd64_per_family_init(struct amd64_pvt *pvt)
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fam_type = &amd64_family_types[K8_CPUS];
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fam_type = &amd64_family_types[K8_CPUS];
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pvt->ops = &amd64_family_types[K8_CPUS].ops;
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pvt->ops = &amd64_family_types[K8_CPUS].ops;
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pvt->ctl_name = fam_type->ctl_name;
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pvt->ctl_name = fam_type->ctl_name;
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pvt->min_scrubrate = K8_MIN_SCRUB_RATE_BITS;
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break;
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break;
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case 0x10:
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case 0x10:
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fam_type = &amd64_family_types[F10_CPUS];
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fam_type = &amd64_family_types[F10_CPUS];
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pvt->ops = &amd64_family_types[F10_CPUS].ops;
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pvt->ops = &amd64_family_types[F10_CPUS].ops;
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pvt->ctl_name = fam_type->ctl_name;
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pvt->ctl_name = fam_type->ctl_name;
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pvt->min_scrubrate = F10_MIN_SCRUB_RATE_BITS;
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break;
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break;
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default:
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default:
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@ -368,9 +368,6 @@ struct amd64_pvt {
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/* place to store error injection parameters prior to issue */
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/* place to store error injection parameters prior to issue */
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struct error_injection injection;
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struct error_injection injection;
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/* DCT per-family scrubrate setting */
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u32 min_scrubrate;
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/* family name this instance is running on */
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/* family name this instance is running on */
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const char *ctl_name;
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const char *ctl_name;
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@ -468,12 +465,5 @@ int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset,
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#define amd64_read_dct_pci_cfg(pvt, offset, val) \
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#define amd64_read_dct_pci_cfg(pvt, offset, val) \
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pvt->ops->read_dct_pci_cfg(pvt, offset, val, __func__)
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pvt->ops->read_dct_pci_cfg(pvt, offset, val, __func__)
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/*
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* For future CPU versions, verify the following as new 'slow' rates appear and
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* modify the necessary skip values for the supported CPU.
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*/
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#define K8_MIN_SCRUB_RATE_BITS 0x0
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#define F10_MIN_SCRUB_RATE_BITS 0x5
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int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base,
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int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base,
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u64 *hole_offset, u64 *hole_size);
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u64 *hole_offset, u64 *hole_size);
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