MIPS: ath79: fix GPIO function selection for AR934x SoCs
GPIO function selection is not working on the AR934x SoCs because the offset of the function selection register is different on those. Add a helper routine which returns the correct register address based on the SoC type, and use that in the 'ath79_gpio_function_*' routines. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4870/ Signed-off-by: John Crispin <blogic@openwrt.org>
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@ -137,47 +137,61 @@ static struct gpio_chip ath79_gpio_chip = {
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.base = 0,
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};
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static void __iomem *ath79_gpio_get_function_reg(void)
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{
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u32 reg = 0;
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if (soc_is_ar71xx() ||
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soc_is_ar724x() ||
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soc_is_ar913x() ||
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soc_is_ar933x())
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reg = AR71XX_GPIO_REG_FUNC;
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else if (soc_is_ar934x())
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reg = AR934X_GPIO_REG_FUNC;
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else
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BUG();
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return ath79_gpio_base + reg;
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}
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void ath79_gpio_function_enable(u32 mask)
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{
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void __iomem *base = ath79_gpio_base;
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void __iomem *reg = ath79_gpio_get_function_reg();
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unsigned long flags;
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spin_lock_irqsave(&ath79_gpio_lock, flags);
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__raw_writel(__raw_readl(base + AR71XX_GPIO_REG_FUNC) | mask,
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base + AR71XX_GPIO_REG_FUNC);
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__raw_writel(__raw_readl(reg) | mask, reg);
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/* flush write */
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__raw_readl(base + AR71XX_GPIO_REG_FUNC);
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__raw_readl(reg);
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spin_unlock_irqrestore(&ath79_gpio_lock, flags);
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}
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void ath79_gpio_function_disable(u32 mask)
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{
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void __iomem *base = ath79_gpio_base;
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void __iomem *reg = ath79_gpio_get_function_reg();
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unsigned long flags;
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spin_lock_irqsave(&ath79_gpio_lock, flags);
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__raw_writel(__raw_readl(base + AR71XX_GPIO_REG_FUNC) & ~mask,
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base + AR71XX_GPIO_REG_FUNC);
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__raw_writel(__raw_readl(reg) & ~mask, reg);
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/* flush write */
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__raw_readl(base + AR71XX_GPIO_REG_FUNC);
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__raw_readl(reg);
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spin_unlock_irqrestore(&ath79_gpio_lock, flags);
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}
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void ath79_gpio_function_setup(u32 set, u32 clear)
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{
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void __iomem *base = ath79_gpio_base;
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void __iomem *reg = ath79_gpio_get_function_reg();
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unsigned long flags;
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spin_lock_irqsave(&ath79_gpio_lock, flags);
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__raw_writel((__raw_readl(base + AR71XX_GPIO_REG_FUNC) & ~clear) | set,
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base + AR71XX_GPIO_REG_FUNC);
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__raw_writel((__raw_readl(reg) & ~clear) | set, reg);
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/* flush write */
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__raw_readl(base + AR71XX_GPIO_REG_FUNC);
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__raw_readl(reg);
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spin_unlock_irqrestore(&ath79_gpio_lock, flags);
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}
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@ -401,6 +401,8 @@
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#define AR71XX_GPIO_REG_INT_ENABLE 0x24
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#define AR71XX_GPIO_REG_FUNC 0x28
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#define AR934X_GPIO_REG_FUNC 0x6c
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#define AR71XX_GPIO_COUNT 16
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#define AR7240_GPIO_COUNT 18
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#define AR7241_GPIO_COUNT 20
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