ath9k_hw: remove direct accesses to channel mode flags
Use wrappers where available. Simplifies code and helps with further improvements to the channel data structure Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
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1a04d59d3e
commit
8896934c16
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@ -338,10 +338,9 @@ void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning)
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aniState->cckNoiseImmunityLevel !=
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ATH9K_ANI_CCK_DEF_LEVEL) {
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ath_dbg(common, ANI,
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"Restore defaults: opmode %u chan %d Mhz/0x%x is_scanning=%d ofdm:%d cck:%d\n",
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"Restore defaults: opmode %u chan %d Mhz is_scanning=%d ofdm:%d cck:%d\n",
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ah->opmode,
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chan->channel,
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chan->channelFlags,
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is_scanning,
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aniState->ofdmNoiseImmunityLevel,
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aniState->cckNoiseImmunityLevel);
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@ -354,10 +353,9 @@ void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning)
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* restore historical levels for this channel
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*/
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ath_dbg(common, ANI,
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"Restore history: opmode %u chan %d Mhz/0x%x is_scanning=%d ofdm:%d cck:%d\n",
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"Restore history: opmode %u chan %d Mhz is_scanning=%d ofdm:%d cck:%d\n",
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ah->opmode,
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chan->channel,
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chan->channelFlags,
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is_scanning,
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aniState->ofdmNoiseImmunityLevel,
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aniState->cckNoiseImmunityLevel);
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@ -666,8 +666,7 @@ static void ar5008_hw_set_channel_regs(struct ath_hw *ah,
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if (IS_CHAN_HT40(chan)) {
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phymode |= AR_PHY_FC_DYN2040_EN;
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if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
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(chan->chanmode == CHANNEL_G_HT40PLUS))
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if (IS_CHAN_HT40PLUS(chan))
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phymode |= AR_PHY_FC_DYN2040_PRI_CH;
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}
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@ -691,31 +690,12 @@ static int ar5008_hw_process_ini(struct ath_hw *ah,
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int i, regWrites = 0;
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u32 modesIndex, freqIndex;
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switch (chan->chanmode) {
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case CHANNEL_A:
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case CHANNEL_A_HT20:
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modesIndex = 1;
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if (IS_CHAN_5GHZ(chan)) {
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freqIndex = 1;
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break;
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case CHANNEL_A_HT40PLUS:
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case CHANNEL_A_HT40MINUS:
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modesIndex = 2;
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freqIndex = 1;
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break;
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case CHANNEL_G:
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case CHANNEL_G_HT20:
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case CHANNEL_B:
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modesIndex = 4;
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modesIndex = IS_CHAN_HT40(chan) ? 2 : 1;
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} else {
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freqIndex = 2;
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break;
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case CHANNEL_G_HT40PLUS:
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case CHANNEL_G_HT40MINUS:
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modesIndex = 3;
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freqIndex = 2;
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break;
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default:
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return -EINVAL;
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modesIndex = IS_CHAN_HT40(chan) ? 3 : 4;
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}
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/*
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@ -1218,12 +1198,11 @@ static void ar5008_hw_ani_cache_ini_regs(struct ath_hw *ah)
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iniDef = &aniState->iniDef;
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ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
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ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz\n",
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ah->hw_version.macVersion,
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ah->hw_version.macRev,
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ah->opmode,
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chan->channel,
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chan->channelFlags);
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chan->channel);
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val = REG_READ(ah, AR_PHY_SFCORR);
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iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
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@ -419,28 +419,10 @@ void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan)
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u32 modesIndex;
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int i;
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switch (chan->chanmode) {
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case CHANNEL_A:
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case CHANNEL_A_HT20:
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modesIndex = 1;
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break;
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case CHANNEL_A_HT40PLUS:
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case CHANNEL_A_HT40MINUS:
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modesIndex = 2;
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break;
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case CHANNEL_G:
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case CHANNEL_G_HT20:
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case CHANNEL_B:
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modesIndex = 4;
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break;
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case CHANNEL_G_HT40PLUS:
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case CHANNEL_G_HT40MINUS:
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modesIndex = 3;
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break;
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default:
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return;
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}
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if (IS_CHAN_5GHZ(chan))
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modesIndex = IS_CHAN_HT40(chan) ? 2 : 1;
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else
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modesIndex = IS_CHAN_HT40(chan) ? 3 : 4;
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ENABLE_REGWRITE_BUFFER(ah);
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@ -551,8 +551,7 @@ static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
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if (IS_CHAN_HT40(chan)) {
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phymode |= AR_PHY_GC_DYN2040_EN;
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/* Configure control (primary) channel at +-10MHz */
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if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
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(chan->chanmode == CHANNEL_G_HT40PLUS))
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if (IS_CHAN_HT40PLUS(chan))
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phymode |= AR_PHY_GC_DYN2040_PRI_CH;
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}
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@ -682,42 +681,23 @@ static int ar9550_hw_get_modes_txgain_index(struct ath_hw *ah,
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{
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int ret;
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switch (chan->chanmode) {
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case CHANNEL_A:
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case CHANNEL_A_HT20:
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if (chan->channel <= 5350)
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ret = 1;
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else if ((chan->channel > 5350) && (chan->channel <= 5600))
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ret = 3;
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if (IS_CHAN_2GHZ(chan)) {
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if (IS_CHAN_HT40(chan))
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return 7;
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else
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ret = 5;
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break;
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case CHANNEL_A_HT40PLUS:
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case CHANNEL_A_HT40MINUS:
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if (chan->channel <= 5350)
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ret = 2;
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else if ((chan->channel > 5350) && (chan->channel <= 5600))
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ret = 4;
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else
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ret = 6;
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break;
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case CHANNEL_G:
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case CHANNEL_G_HT20:
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case CHANNEL_B:
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ret = 8;
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break;
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case CHANNEL_G_HT40PLUS:
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case CHANNEL_G_HT40MINUS:
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ret = 7;
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break;
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default:
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ret = -EINVAL;
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return 8;
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}
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if (chan->channel <= 5350)
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ret = 1;
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else if ((chan->channel > 5350) && (chan->channel <= 5600))
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ret = 3;
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else
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ret = 5;
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if (IS_CHAN_HT40(chan))
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ret++;
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return ret;
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}
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@ -727,28 +707,10 @@ static int ar9003_hw_process_ini(struct ath_hw *ah,
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unsigned int regWrites = 0, i;
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u32 modesIndex;
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switch (chan->chanmode) {
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case CHANNEL_A:
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case CHANNEL_A_HT20:
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modesIndex = 1;
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break;
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case CHANNEL_A_HT40PLUS:
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case CHANNEL_A_HT40MINUS:
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modesIndex = 2;
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break;
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case CHANNEL_G:
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case CHANNEL_G_HT20:
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case CHANNEL_B:
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modesIndex = 4;
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break;
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case CHANNEL_G_HT40PLUS:
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case CHANNEL_G_HT40MINUS:
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modesIndex = 3;
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break;
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default:
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return -EINVAL;
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}
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if (IS_CHAN_5GHZ(chan))
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modesIndex = IS_CHAN_HT40(chan) ? 2 : 1;
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else
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modesIndex = IS_CHAN_HT40(chan) ? 3 : 4;
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/*
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* SOC, MAC, BB, RADIO initvals.
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@ -1273,12 +1235,11 @@ static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
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aniState = &ah->ani;
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iniDef = &aniState->iniDef;
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ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
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ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz\n",
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ah->hw_version.macVersion,
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ah->hw_version.macRev,
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ah->opmode,
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chan->channel,
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chan->channelFlags);
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chan->channel);
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val = REG_READ(ah, AR_PHY_SFCORR);
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iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
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@ -1536,28 +1497,10 @@ static int ar9003_hw_fast_chan_change(struct ath_hw *ah,
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unsigned int regWrites = 0;
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u32 modesIndex;
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switch (chan->chanmode) {
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case CHANNEL_A:
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case CHANNEL_A_HT20:
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modesIndex = 1;
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break;
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case CHANNEL_A_HT40PLUS:
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case CHANNEL_A_HT40MINUS:
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modesIndex = 2;
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break;
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case CHANNEL_G:
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case CHANNEL_G_HT20:
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case CHANNEL_B:
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modesIndex = 4;
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break;
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case CHANNEL_G_HT40PLUS:
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case CHANNEL_G_HT40MINUS:
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modesIndex = 3;
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break;
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default:
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return -EINVAL;
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}
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if (IS_CHAN_5GHZ(chan))
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modesIndex = IS_CHAN_HT40(chan) ? 2 : 1;
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else
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modesIndex = IS_CHAN_HT40(chan) ? 3 : 4;
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if (modesIndex == ah->modes_index) {
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*ini_reloaded = false;
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@ -24,30 +24,10 @@
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static enum htc_phymode ath9k_htc_get_curmode(struct ath9k_htc_priv *priv,
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struct ath9k_channel *ichan)
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{
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enum htc_phymode mode;
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if (IS_CHAN_5GHZ(ichan))
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return HTC_MODE_11NA;
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mode = -EINVAL;
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switch (ichan->chanmode) {
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case CHANNEL_G:
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case CHANNEL_G_HT20:
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case CHANNEL_G_HT40PLUS:
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case CHANNEL_G_HT40MINUS:
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mode = HTC_MODE_11NG;
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break;
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case CHANNEL_A:
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case CHANNEL_A_HT20:
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case CHANNEL_A_HT40PLUS:
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case CHANNEL_A_HT40MINUS:
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mode = HTC_MODE_11NA;
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break;
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default:
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break;
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}
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WARN_ON(mode < 0);
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return mode;
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return HTC_MODE_11NG;
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}
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bool ath9k_htc_setpower(struct ath9k_htc_priv *priv,
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@ -294,8 +294,7 @@ void ath9k_hw_get_channel_centers(struct ath_hw *ah,
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return;
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}
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if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
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(chan->chanmode == CHANNEL_G_HT40PLUS)) {
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if (IS_CHAN_HT40PLUS(chan)) {
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centers->synth_center =
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chan->channel + HT40_CHANNEL_CENTER_SHIFT;
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extoff = 1;
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@ -1510,9 +1509,7 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
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int r;
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if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) {
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u32 cur = ah->curchan->channelFlags & (CHANNEL_2GHZ | CHANNEL_5GHZ);
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u32 new = chan->channelFlags & (CHANNEL_2GHZ | CHANNEL_5GHZ);
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band_switch = (cur != new);
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band_switch = IS_CHAN_5GHZ(ah->curchan) != IS_CHAN_5GHZ(chan);
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mode_diff = (chan->chanmode != ah->curchan->chanmode);
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}
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@ -463,6 +463,8 @@ struct ath9k_channel {
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((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
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((_c)->chanmode == CHANNEL_G_HT40MINUS))
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#define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
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#define IS_CHAN_HT40PLUS(_c) ((_c)->chanmode & CHANNEL_HT40PLUS)
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#define IS_CHAN_HT40MINUS(_c) ((_c)->chanmode & CHANNEL_HT40MINUS)
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enum ath9k_power_mode {
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ATH9K_PM_AWAKE = 0,
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@ -661,9 +661,9 @@ void ath9k_mci_update_wlan_channels(struct ath_softc *sc, bool allow_all)
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chan_start = wlan_chan - 10;
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chan_end = wlan_chan + 10;
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if (chan->chanmode == CHANNEL_G_HT40PLUS)
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if (IS_CHAN_HT40PLUS(chan))
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chan_end += 20;
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else if (chan->chanmode == CHANNEL_G_HT40MINUS)
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else if (IS_CHAN_HT40MINUS(chan))
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chan_start -= 20;
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/* adjust side band */
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@ -707,11 +707,11 @@ void ath9k_mci_set_txpower(struct ath_softc *sc, bool setchannel,
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if (setchannel) {
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struct ath9k_hw_cal_data *caldata = &sc->caldata;
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if ((caldata->chanmode == CHANNEL_G_HT40PLUS) &&
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if (IS_CHAN_HT40PLUS(ah->curchan) &&
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(ah->curchan->channel > caldata->channel) &&
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(ah->curchan->channel <= caldata->channel + 20))
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return;
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if ((caldata->chanmode == CHANNEL_G_HT40MINUS) &&
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if (IS_CHAN_HT40MINUS(ah->curchan) &&
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(ah->curchan->channel < caldata->channel) &&
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(ah->curchan->channel >= caldata->channel - 20))
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return;
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@ -2023,8 +2023,7 @@ u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
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struct ath_hw *ah = sc->sc_ah;
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struct ath9k_channel *curchan = ah->curchan;
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if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) &&
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(curchan->channelFlags & CHANNEL_5GHZ) &&
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if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && IS_CHAN_5GHZ(curchan) &&
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(chainmask == 0x7) && (rate < 0x90))
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return 0x3;
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else if (AR_SREV_9462(ah) && ath9k_hw_btcoex_is_enabled(ah) &&
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