[PATCH] sata_sil24: convert to new EH
Convert sata_sil24 to new EH. * When port is frozen, IRQ for the port is masked. * sil24_softreset() doesn't need to mangle with IRQ mask anymore. libata ensures that the port is frozen during reset. * Only turn on interrupts which are handled by interrupt handler and EH. As we don't handle SDB notify yet, turn it off. DEV_XCHG and UNK_FIS are handled by EH and thus turned on. * sil24_softreset() usually fails to recover the port after DEV_XCHG. ATA_PORT_HARDRESET is used as recovery action for DEV_XCHG. * sil24 may be invoked without any active command. e.g. DEV_XCHG irq occuring while no qc in progress still triggers EH and will reset the port and revalidate attached device. Signed-off-by: Tejun Heo <htejun@gmail.com>
This commit is contained in:
Tejun Heo
parent
2a3917a8bb
commit
88ce7550c3
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@ -156,6 +156,9 @@ enum {
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PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */
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PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */
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DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR |
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PORT_IRQ_DEV_XCHG | PORT_IRQ_UNK_FIS,
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/* bits[27:16] are unmasked (raw) */
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PORT_IRQ_RAW_SHIFT = 16,
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PORT_IRQ_MASKED_MASK = 0x7ff,
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@ -242,6 +245,58 @@ union sil24_cmd_block {
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struct sil24_atapi_block atapi;
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};
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static struct sil24_cerr_info {
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unsigned int err_mask, action;
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const char *desc;
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} sil24_cerr_db[] = {
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[0] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
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"device error" },
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[PORT_CERR_DEV] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
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"device error via D2H FIS" },
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[PORT_CERR_SDB] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
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"device error via SDB FIS" },
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[PORT_CERR_DATA] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET,
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"error in data FIS" },
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[PORT_CERR_SEND] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET,
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"failed to transmit command FIS" },
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[PORT_CERR_INCONSISTENT] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
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"protocol mismatch" },
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[PORT_CERR_DIRECTION] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
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"data directon mismatch" },
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[PORT_CERR_UNDERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
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"ran out of SGEs while writing" },
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[PORT_CERR_OVERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
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"ran out of SGEs while reading" },
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[PORT_CERR_PKT_PROT] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
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"invalid data directon for ATAPI CDB" },
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[PORT_CERR_SGT_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET,
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"SGT no on qword boundary" },
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[PORT_CERR_SGT_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
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"PCI target abort while fetching SGT" },
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[PORT_CERR_SGT_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
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"PCI master abort while fetching SGT" },
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[PORT_CERR_SGT_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
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"PCI parity error while fetching SGT" },
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[PORT_CERR_CMD_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET,
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"PRB not on qword boundary" },
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[PORT_CERR_CMD_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
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"PCI target abort while fetching PRB" },
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[PORT_CERR_CMD_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
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"PCI master abort while fetching PRB" },
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[PORT_CERR_CMD_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
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"PCI parity error while fetching PRB" },
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[PORT_CERR_XFR_UNDEF] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
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"undefined error while transferring data" },
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[PORT_CERR_XFR_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
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"PCI target abort while transferring data" },
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[PORT_CERR_XFR_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
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"PCI master abort while transferring data" },
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[PORT_CERR_XFR_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
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"PCI parity error while transferring data" },
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[PORT_CERR_SENDSERVICE] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
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"FIS received while sending service FIS" },
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};
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/*
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* ap->private_data
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*
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@ -269,8 +324,11 @@ static int sil24_probe_reset(struct ata_port *ap, unsigned int *classes);
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static void sil24_qc_prep(struct ata_queued_cmd *qc);
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static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc);
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static void sil24_irq_clear(struct ata_port *ap);
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static void sil24_eng_timeout(struct ata_port *ap);
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static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs);
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static void sil24_freeze(struct ata_port *ap);
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static void sil24_thaw(struct ata_port *ap);
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static void sil24_error_handler(struct ata_port *ap);
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static void sil24_post_internal_cmd(struct ata_queued_cmd *qc);
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static int sil24_port_start(struct ata_port *ap);
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static void sil24_port_stop(struct ata_port *ap);
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static void sil24_host_stop(struct ata_host_set *host_set);
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@ -325,14 +383,17 @@ static const struct ata_port_operations sil24_ops = {
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.qc_prep = sil24_qc_prep,
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.qc_issue = sil24_qc_issue,
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.eng_timeout = sil24_eng_timeout,
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.irq_handler = sil24_interrupt,
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.irq_clear = sil24_irq_clear,
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.scr_read = sil24_scr_read,
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.scr_write = sil24_scr_write,
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.freeze = sil24_freeze,
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.thaw = sil24_thaw,
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.error_handler = sil24_error_handler,
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.post_internal_cmd = sil24_post_internal_cmd,
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.port_start = sil24_port_start,
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.port_stop = sil24_port_stop,
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.host_stop = sil24_host_stop,
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@ -459,7 +520,7 @@ static int sil24_softreset(struct ata_port *ap, unsigned int *class)
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struct sil24_port_priv *pp = ap->private_data;
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struct sil24_prb *prb = &pp->cmd_block[0].ata.prb;
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dma_addr_t paddr = pp->cmd_block_dma;
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u32 mask, irq_enable, irq_stat;
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u32 mask, irq_stat;
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const char *reason;
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DPRINTK("ENTER\n");
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@ -470,10 +531,6 @@ static int sil24_softreset(struct ata_port *ap, unsigned int *class)
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goto out;
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}
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/* temporarily turn off IRQs during SRST */
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irq_enable = readl(port + PORT_IRQ_ENABLE_SET);
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writel(irq_enable, port + PORT_IRQ_ENABLE_CLR);
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/* put the port into known state */
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if (sil24_init_port(ap)) {
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reason ="port not ready";
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@ -494,9 +551,6 @@ static int sil24_softreset(struct ata_port *ap, unsigned int *class)
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writel(irq_stat, port + PORT_IRQ_STAT); /* clear IRQs */
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irq_stat >>= PORT_IRQ_RAW_SHIFT;
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/* restore IRQs */
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writel(irq_enable, port + PORT_IRQ_ENABLE_SET);
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if (!(irq_stat & PORT_IRQ_COMPLETE)) {
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if (irq_stat & PORT_IRQ_ERROR)
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reason = "SRST command error";
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@ -655,158 +709,134 @@ static void sil24_irq_clear(struct ata_port *ap)
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/* unused */
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}
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static int __sil24_restart_controller(void __iomem *port)
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static void sil24_freeze(struct ata_port *ap)
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{
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u32 tmp;
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int cnt;
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writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
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/* Max ~10ms */
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for (cnt = 0; cnt < 10000; cnt++) {
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tmp = readl(port + PORT_CTRL_STAT);
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if (tmp & PORT_CS_RDY)
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return 0;
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udelay(1);
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}
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return -1;
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}
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static void sil24_restart_controller(struct ata_port *ap)
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{
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if (__sil24_restart_controller((void __iomem *)ap->ioaddr.cmd_addr))
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printk(KERN_ERR DRV_NAME
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" ata%u: failed to restart controller\n", ap->id);
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}
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static int __sil24_reset_controller(void __iomem *port)
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{
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int cnt;
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u32 tmp;
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/* Reset controller state. Is this correct? */
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writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
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readl(port + PORT_CTRL_STAT); /* sync */
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/* Max ~100ms */
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for (cnt = 0; cnt < 1000; cnt++) {
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udelay(100);
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tmp = readl(port + PORT_CTRL_STAT);
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if (!(tmp & PORT_CS_DEV_RST))
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break;
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}
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if (tmp & PORT_CS_DEV_RST)
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return -1;
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if (tmp & PORT_CS_RDY)
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return 0;
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return __sil24_restart_controller(port);
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}
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static void sil24_reset_controller(struct ata_port *ap)
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{
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printk(KERN_NOTICE DRV_NAME
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" ata%u: resetting controller...\n", ap->id);
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if (__sil24_reset_controller((void __iomem *)ap->ioaddr.cmd_addr))
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printk(KERN_ERR DRV_NAME
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" ata%u: failed to reset controller\n", ap->id);
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}
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static void sil24_eng_timeout(struct ata_port *ap)
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{
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struct ata_queued_cmd *qc;
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qc = ata_qc_from_tag(ap, ap->active_tag);
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ata_port_printk(ap, KERN_ERR, "command timeout\n");
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qc->err_mask |= AC_ERR_TIMEOUT;
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ata_eh_qc_complete(qc);
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sil24_reset_controller(ap);
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}
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static void sil24_error_intr(struct ata_port *ap, u32 slot_stat)
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{
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struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
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struct sil24_port_priv *pp = ap->private_data;
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void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
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u32 irq_stat, cmd_err, sstatus, serror;
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unsigned int err_mask;
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irq_stat = readl(port + PORT_IRQ_STAT);
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writel(irq_stat, port + PORT_IRQ_STAT); /* clear irq */
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if (!(irq_stat & PORT_IRQ_ERROR)) {
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/* ignore non-completion, non-error irqs for now */
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printk(KERN_WARNING DRV_NAME
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"ata%u: non-error exception irq (irq_stat %x)\n",
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ap->id, irq_stat);
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return;
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}
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cmd_err = readl(port + PORT_CMD_ERR);
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sstatus = readl(port + PORT_SSTATUS);
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serror = readl(port + PORT_SERROR);
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if (serror)
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writel(serror, port + PORT_SERROR);
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/*
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* Don't log ATAPI device errors. They're supposed to happen
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* and any serious errors will be logged using sense data by
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* the SCSI layer.
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/* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear
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* PORT_IRQ_ENABLE instead.
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*/
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if (ap->device[0].class != ATA_DEV_ATAPI || cmd_err > PORT_CERR_SDB)
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printk("ata%u: error interrupt on port%d\n"
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" stat=0x%x irq=0x%x cmd_err=%d sstatus=0x%x serror=0x%x\n",
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ap->id, ap->port_no, slot_stat, irq_stat, cmd_err, sstatus, serror);
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writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
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}
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if (cmd_err == PORT_CERR_DEV || cmd_err == PORT_CERR_SDB) {
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/*
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* Device is reporting error, tf registers are valid.
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static void sil24_thaw(struct ata_port *ap)
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{
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void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
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u32 tmp;
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/* clear IRQ */
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tmp = readl(port + PORT_IRQ_STAT);
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writel(tmp, port + PORT_IRQ_STAT);
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/* turn IRQ back on */
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writel(DEF_PORT_IRQ, port + PORT_IRQ_ENABLE_SET);
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}
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static void sil24_error_intr(struct ata_port *ap)
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{
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void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
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struct ata_eh_info *ehi = &ap->eh_info;
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int freeze = 0;
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u32 irq_stat;
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/* on error, we need to clear IRQ explicitly */
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irq_stat = readl(port + PORT_IRQ_STAT);
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writel(irq_stat, port + PORT_IRQ_STAT);
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/* first, analyze and record host port events */
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ata_ehi_clear_desc(ehi);
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ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
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if (irq_stat & PORT_IRQ_DEV_XCHG) {
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ehi->err_mask |= AC_ERR_ATA_BUS;
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/* sil24 doesn't recover very well from phy
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* disconnection with a softreset. Force hardreset.
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*/
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sil24_update_tf(ap);
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err_mask = ac_err_mask(pp->tf.command);
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sil24_restart_controller(ap);
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} else {
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/*
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* Other errors. libata currently doesn't have any
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* mechanism to report these errors. Just turn on
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* ATA_ERR.
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*/
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err_mask = AC_ERR_OTHER;
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sil24_reset_controller(ap);
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ehi->action |= ATA_EH_HARDRESET;
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ata_ehi_push_desc(ehi, ", device_exchanged");
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freeze = 1;
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}
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if (qc) {
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qc->err_mask |= err_mask;
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ata_qc_complete(qc);
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if (irq_stat & PORT_IRQ_UNK_FIS) {
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ehi->err_mask |= AC_ERR_HSM;
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ehi->action |= ATA_EH_SOFTRESET;
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ata_ehi_push_desc(ehi , ", unknown FIS");
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freeze = 1;
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}
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/* deal with command error */
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if (irq_stat & PORT_IRQ_ERROR) {
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struct sil24_cerr_info *ci = NULL;
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unsigned int err_mask = 0, action = 0;
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struct ata_queued_cmd *qc;
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u32 cerr;
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/* analyze CMD_ERR */
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cerr = readl(port + PORT_CMD_ERR);
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if (cerr < ARRAY_SIZE(sil24_cerr_db))
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ci = &sil24_cerr_db[cerr];
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if (ci && ci->desc) {
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err_mask |= ci->err_mask;
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action |= ci->action;
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ata_ehi_push_desc(ehi, ", %s", ci->desc);
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} else {
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err_mask |= AC_ERR_OTHER;
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action |= ATA_EH_SOFTRESET;
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ata_ehi_push_desc(ehi, ", unknown command error %d",
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cerr);
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}
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/* record error info */
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qc = ata_qc_from_tag(ap, ap->active_tag);
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if (qc) {
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int tag = qc->tag;
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if (unlikely(ata_tag_internal(tag)))
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tag = 0;
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sil24_update_tf(ap);
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qc->err_mask |= err_mask;
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} else
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ehi->err_mask |= err_mask;
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ehi->action |= action;
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}
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/* freeze or abort */
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if (freeze)
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ata_port_freeze(ap);
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else
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ata_port_abort(ap);
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}
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static inline void sil24_host_intr(struct ata_port *ap)
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{
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struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
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void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
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struct ata_queued_cmd *qc;
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u32 slot_stat;
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slot_stat = readl(port + PORT_SLOT_STAT);
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if (!(slot_stat & HOST_SSTAT_ATTN)) {
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struct sil24_port_priv *pp = ap->private_data;
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if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
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writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT);
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if (unlikely(slot_stat & HOST_SSTAT_ATTN)) {
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sil24_error_intr(ap);
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return;
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}
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if (qc) {
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if (qc->flags & ATA_QCFLAG_RESULT_TF)
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sil24_update_tf(ap);
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qc->err_mask |= ac_err_mask(pp->tf.command);
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ata_qc_complete(qc);
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}
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} else
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sil24_error_intr(ap, slot_stat);
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if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
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writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT);
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qc = ata_qc_from_tag(ap, ap->active_tag);
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if (qc) {
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if (qc->flags & ATA_QCFLAG_RESULT_TF)
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sil24_update_tf(ap);
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ata_qc_complete(qc);
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return;
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}
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if (ata_ratelimit())
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ata_port_printk(ap, KERN_INFO, "spurious interrupt "
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"(slot_stat 0x%x active_tag %d)\n",
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slot_stat, ap->active_tag);
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}
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static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
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@ -846,6 +876,31 @@ static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *
|
|||
return IRQ_RETVAL(handled);
|
||||
}
|
||||
|
||||
static void sil24_error_handler(struct ata_port *ap)
|
||||
{
|
||||
struct ata_eh_context *ehc = &ap->eh_context;
|
||||
|
||||
if (sil24_init_port(ap)) {
|
||||
ata_eh_freeze_port(ap);
|
||||
ehc->i.action |= ATA_EH_HARDRESET;
|
||||
}
|
||||
|
||||
/* perform recovery */
|
||||
ata_do_eh(ap, sil24_softreset, sil24_hardreset, ata_std_postreset);
|
||||
}
|
||||
|
||||
static void sil24_post_internal_cmd(struct ata_queued_cmd *qc)
|
||||
{
|
||||
struct ata_port *ap = qc->ap;
|
||||
|
||||
if (qc->flags & ATA_QCFLAG_FAILED)
|
||||
qc->err_mask |= AC_ERR_OTHER;
|
||||
|
||||
/* make DMA engine forget about the failed command */
|
||||
if (qc->err_mask)
|
||||
sil24_init_port(ap);
|
||||
}
|
||||
|
||||
static inline void sil24_cblk_free(struct sil24_port_priv *pp, struct device *dev)
|
||||
{
|
||||
const size_t cb_size = sizeof(*pp->cmd_block);
|
||||
|
|
@ -1058,15 +1113,6 @@ static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|||
/* Always use 64bit activation */
|
||||
writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
|
||||
|
||||
/* Configure interrupts */
|
||||
writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
|
||||
writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR |
|
||||
PORT_IRQ_SDB_NOTIFY, port + PORT_IRQ_ENABLE_SET);
|
||||
|
||||
/* Clear interrupts */
|
||||
writel(0x0fff0fff, port + PORT_IRQ_STAT);
|
||||
writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
|
||||
|
||||
/* Clear port multiplier enable and resume bits */
|
||||
writel(PORT_CS_PM_EN | PORT_CS_RESUME, port + PORT_CTRL_CLR);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue