gpio: omap: use raw locks for locking
This patch converts gpio_bank.lock from a spin_lock into a raw_spin_lock. The call path is to access this lock is always under a raw_spin_lock, for instance - __setup_irq() holds &desc->lock with irq off + __irq_set_trigger() + omap_gpio_irq_type() - handle_level_irq() (runs with irqs off therefore raw locks) + mask_ack_irq() + omap_gpio_mask_irq() This fixes the obvious backtrace on -RT. However the locking vs context is not and this is not limited to -RT: - omap_gpio_irq_type() is called with IRQ off and has an conditional call to pm_runtime_get_sync() which may sleep. Either it may happen or it may not happen but pm_runtime_get_sync() should not be called with irqs off. - omap_gpio_debounce() is holding the lock with IRQs off. + omap2_set_gpio_debounce() + clk_prepare_enable() + clk_prepare() this one might sleep. The number of users of gpiod_set_debounce() / gpio_set_debounce() looks low but still this is not good. Cc: stable-rt@vger.kernel.org Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Steven Rostedt <rostedt@goodmis.org>
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9673232a79
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@ -59,7 +59,7 @@ struct gpio_bank {
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u32 saved_datain;
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u32 level_mask;
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u32 toggle_mask;
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spinlock_t lock;
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raw_spinlock_t lock;
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struct gpio_chip chip;
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struct clk *dbck;
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u32 mod_usage;
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@ -503,14 +503,14 @@ static int gpio_irq_type(struct irq_data *d, unsigned type)
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(type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
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return -EINVAL;
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spin_lock_irqsave(&bank->lock, flags);
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raw_spin_lock_irqsave(&bank->lock, flags);
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offset = GPIO_INDEX(bank, gpio);
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retval = _set_gpio_triggering(bank, offset, type);
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if (!LINE_USED(bank->mod_usage, offset)) {
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_enable_gpio_module(bank, offset);
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_set_gpio_direction(bank, offset, 1);
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} else if (!gpio_is_input(bank, 1 << offset)) {
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spin_unlock_irqrestore(&bank->lock, flags);
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raw_spin_unlock_irqrestore(&bank->lock, flags);
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return -EINVAL;
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}
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@ -518,12 +518,12 @@ static int gpio_irq_type(struct irq_data *d, unsigned type)
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if (retval) {
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dev_err(bank->dev, "unable to lock offset %d for IRQ\n",
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offset);
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spin_unlock_irqrestore(&bank->lock, flags);
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raw_spin_unlock_irqrestore(&bank->lock, flags);
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return retval;
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}
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bank->irq_usage |= 1 << GPIO_INDEX(bank, gpio);
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spin_unlock_irqrestore(&bank->lock, flags);
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raw_spin_unlock_irqrestore(&bank->lock, flags);
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if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
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__irq_set_handler_locked(d->irq, handle_level_irq);
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@ -640,14 +640,14 @@ static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
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return -EINVAL;
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}
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spin_lock_irqsave(&bank->lock, flags);
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raw_spin_lock_irqsave(&bank->lock, flags);
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if (enable)
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bank->context.wake_en |= gpio_bit;
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else
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bank->context.wake_en &= ~gpio_bit;
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writel_relaxed(bank->context.wake_en, bank->base + bank->regs->wkup_en);
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spin_unlock_irqrestore(&bank->lock, flags);
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raw_spin_unlock_irqrestore(&bank->lock, flags);
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return 0;
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}
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@ -682,7 +682,7 @@ static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
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if (!BANK_USED(bank))
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pm_runtime_get_sync(bank->dev);
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spin_lock_irqsave(&bank->lock, flags);
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raw_spin_lock_irqsave(&bank->lock, flags);
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/* Set trigger to none. You need to enable the desired trigger with
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* request_irq() or set_irq_type(). Only do this if the IRQ line has
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* not already been requested.
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@ -692,7 +692,7 @@ static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
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_enable_gpio_module(bank, offset);
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}
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bank->mod_usage |= 1 << offset;
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spin_unlock_irqrestore(&bank->lock, flags);
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raw_spin_unlock_irqrestore(&bank->lock, flags);
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return 0;
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}
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@ -702,11 +702,11 @@ static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
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struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
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unsigned long flags;
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spin_lock_irqsave(&bank->lock, flags);
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raw_spin_lock_irqsave(&bank->lock, flags);
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bank->mod_usage &= ~(1 << offset);
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_disable_gpio_module(bank, offset);
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_reset_gpio(bank, bank->chip.base + offset);
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spin_unlock_irqrestore(&bank->lock, flags);
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raw_spin_unlock_irqrestore(&bank->lock, flags);
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/*
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* If this is the last gpio to be freed in the bank,
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@ -804,12 +804,12 @@ static void gpio_irq_shutdown(struct irq_data *d)
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unsigned long flags;
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unsigned offset = GPIO_INDEX(bank, gpio);
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spin_lock_irqsave(&bank->lock, flags);
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raw_spin_lock_irqsave(&bank->lock, flags);
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gpio_unlock_as_irq(&bank->chip, offset);
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bank->irq_usage &= ~(1 << offset);
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_disable_gpio_module(bank, offset);
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_reset_gpio(bank, gpio);
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spin_unlock_irqrestore(&bank->lock, flags);
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raw_spin_unlock_irqrestore(&bank->lock, flags);
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/*
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* If this is the last IRQ to be freed in the bank,
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@ -833,10 +833,10 @@ static void gpio_mask_irq(struct irq_data *d)
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unsigned int gpio = irq_to_gpio(bank, d->hwirq);
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unsigned long flags;
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spin_lock_irqsave(&bank->lock, flags);
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raw_spin_lock_irqsave(&bank->lock, flags);
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_set_gpio_irqenable(bank, gpio, 0);
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_set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
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spin_unlock_irqrestore(&bank->lock, flags);
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raw_spin_unlock_irqrestore(&bank->lock, flags);
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}
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static void gpio_unmask_irq(struct irq_data *d)
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@ -847,7 +847,7 @@ static void gpio_unmask_irq(struct irq_data *d)
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u32 trigger = irqd_get_trigger_type(d);
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unsigned long flags;
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spin_lock_irqsave(&bank->lock, flags);
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raw_spin_lock_irqsave(&bank->lock, flags);
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if (trigger)
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_set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger);
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@ -859,7 +859,7 @@ static void gpio_unmask_irq(struct irq_data *d)
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}
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_set_gpio_irqenable(bank, gpio, 1);
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spin_unlock_irqrestore(&bank->lock, flags);
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raw_spin_unlock_irqrestore(&bank->lock, flags);
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}
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static struct irq_chip gpio_irq_chip = {
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@ -882,9 +882,9 @@ static int omap_mpuio_suspend_noirq(struct device *dev)
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OMAP_MPUIO_GPIO_MASKIT / bank->stride;
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unsigned long flags;
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spin_lock_irqsave(&bank->lock, flags);
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raw_spin_lock_irqsave(&bank->lock, flags);
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writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg);
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spin_unlock_irqrestore(&bank->lock, flags);
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raw_spin_unlock_irqrestore(&bank->lock, flags);
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return 0;
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}
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@ -897,9 +897,9 @@ static int omap_mpuio_resume_noirq(struct device *dev)
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OMAP_MPUIO_GPIO_MASKIT / bank->stride;
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unsigned long flags;
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spin_lock_irqsave(&bank->lock, flags);
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raw_spin_lock_irqsave(&bank->lock, flags);
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writel_relaxed(bank->context.wake_en, mask_reg);
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spin_unlock_irqrestore(&bank->lock, flags);
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raw_spin_unlock_irqrestore(&bank->lock, flags);
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return 0;
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}
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@ -942,9 +942,9 @@ static int gpio_input(struct gpio_chip *chip, unsigned offset)
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unsigned long flags;
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bank = container_of(chip, struct gpio_bank, chip);
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spin_lock_irqsave(&bank->lock, flags);
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raw_spin_lock_irqsave(&bank->lock, flags);
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_set_gpio_direction(bank, offset, 1);
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spin_unlock_irqrestore(&bank->lock, flags);
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raw_spin_unlock_irqrestore(&bank->lock, flags);
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return 0;
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}
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@ -968,10 +968,10 @@ static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
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unsigned long flags;
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bank = container_of(chip, struct gpio_bank, chip);
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spin_lock_irqsave(&bank->lock, flags);
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raw_spin_lock_irqsave(&bank->lock, flags);
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bank->set_dataout(bank, offset, value);
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_set_gpio_direction(bank, offset, 0);
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spin_unlock_irqrestore(&bank->lock, flags);
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raw_spin_unlock_irqrestore(&bank->lock, flags);
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return 0;
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}
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@ -983,9 +983,9 @@ static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
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bank = container_of(chip, struct gpio_bank, chip);
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spin_lock_irqsave(&bank->lock, flags);
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raw_spin_lock_irqsave(&bank->lock, flags);
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_set_gpio_debounce(bank, offset, debounce);
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spin_unlock_irqrestore(&bank->lock, flags);
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raw_spin_unlock_irqrestore(&bank->lock, flags);
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return 0;
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}
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@ -996,9 +996,9 @@ static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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unsigned long flags;
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bank = container_of(chip, struct gpio_bank, chip);
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spin_lock_irqsave(&bank->lock, flags);
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raw_spin_lock_irqsave(&bank->lock, flags);
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bank->set_dataout(bank, offset, value);
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spin_unlock_irqrestore(&bank->lock, flags);
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raw_spin_unlock_irqrestore(&bank->lock, flags);
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}
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/*---------------------------------------------------------------------*/
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@ -1210,7 +1210,7 @@ static int omap_gpio_probe(struct platform_device *pdev)
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else
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bank->set_dataout = _set_gpio_dataout_mask;
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spin_lock_init(&bank->lock);
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raw_spin_lock_init(&bank->lock);
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/* Static mapping, never released */
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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@ -1267,7 +1267,7 @@ static int omap_gpio_runtime_suspend(struct device *dev)
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unsigned long flags;
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u32 wake_low, wake_hi;
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spin_lock_irqsave(&bank->lock, flags);
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raw_spin_lock_irqsave(&bank->lock, flags);
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/*
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* Only edges can generate a wakeup event to the PRCM.
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@ -1320,7 +1320,7 @@ update_gpio_context_count:
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bank->get_context_loss_count(bank->dev);
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_gpio_dbck_disable(bank);
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spin_unlock_irqrestore(&bank->lock, flags);
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raw_spin_unlock_irqrestore(&bank->lock, flags);
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return 0;
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}
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@ -1335,7 +1335,7 @@ static int omap_gpio_runtime_resume(struct device *dev)
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unsigned long flags;
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int c;
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spin_lock_irqsave(&bank->lock, flags);
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raw_spin_lock_irqsave(&bank->lock, flags);
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/*
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* On the first resume during the probe, the context has not
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@ -1371,14 +1371,14 @@ static int omap_gpio_runtime_resume(struct device *dev)
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if (c != bank->context_loss_count) {
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omap_gpio_restore_context(bank);
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} else {
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spin_unlock_irqrestore(&bank->lock, flags);
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raw_spin_unlock_irqrestore(&bank->lock, flags);
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return 0;
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}
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}
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}
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if (!bank->workaround_enabled) {
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spin_unlock_irqrestore(&bank->lock, flags);
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raw_spin_unlock_irqrestore(&bank->lock, flags);
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return 0;
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}
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@ -1433,7 +1433,7 @@ static int omap_gpio_runtime_resume(struct device *dev)
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}
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bank->workaround_enabled = false;
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spin_unlock_irqrestore(&bank->lock, flags);
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raw_spin_unlock_irqrestore(&bank->lock, flags);
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return 0;
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}
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