ASoC: cygnus: Add support for 384kHz frame rates
Allow the audio ports to operate at 384kHz. Signed-off-by: Lori Hikichi <lori.hikichi@broadcom.com> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Lori Hikichi
Mark Brown
parent
5771a8c088
commit
8937ea0f3c
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@ -27,12 +27,6 @@
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#define DEFAULT_VCO 1354750204
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#define CYGNUS_TDM_RATE \
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(SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | \
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SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_22050 | \
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SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
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SNDRV_PCM_RATE_48000)
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#define CAPTURE_FCI_ID_BASE 0x180
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#define CYGNUS_SSP_TRISTATE_MASK 0x001fff
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#define CYGNUS_PLLCLKSEL_MASK 0xf
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@ -234,152 +228,20 @@ static const struct pll_macro_entry pll_predef_mclk[] = {
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{98304000, 2},
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};
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#define CYGNUS_RATE_MIN 8000
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#define CYGNUS_RATE_MAX 384000
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/* List of valid frame sizes for tdm mode */
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static const int ssp_valid_tdm_framesize[] = {32, 64, 128, 256, 512};
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/*
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* Use this relationship to derive the sampling rate (lrclk)
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* lrclk = (mclk) / ((2*mclk_to_sclk_ratio) * (32 * SCLK))).
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*
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* Use mclk and pll_ch from the table above
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*
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* Valid SCLK = 0/1/2/4/8/12
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*
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* mclk_to_sclk_ratio = number of MCLK per SCLK. Division is twice the
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* value programmed in this field.
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* Valid mclk_to_sclk_ratio = 1 through to 15
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*
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* eg: To set lrclk = 48khz, set mclk = 12288000, mclk_to_sclk_ratio = 2,
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* SCLK = 64
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*/
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struct _ssp_clk_coeff {
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u32 mclk;
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u32 sclk_rate;
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u32 rate;
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u32 mclk_rate;
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static const unsigned int cygnus_rates[] = {
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8000, 11025, 16000, 22050, 32000, 44100, 48000,
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88200, 96000, 176400, 192000, 352800, 384000
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};
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static const struct _ssp_clk_coeff ssp_clk_coeff[] = {
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{ 4096000, 32, 16000, 4},
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{ 4096000, 32, 32000, 2},
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{ 4096000, 64, 8000, 4},
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{ 4096000, 64, 16000, 2},
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{ 4096000, 64, 32000, 1},
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{ 4096000, 128, 8000, 2},
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{ 4096000, 128, 16000, 1},
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{ 4096000, 256, 8000, 1},
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{ 6144000, 32, 16000, 6},
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{ 6144000, 32, 32000, 3},
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{ 6144000, 32, 48000, 2},
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{ 6144000, 32, 96000, 1},
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{ 6144000, 64, 8000, 6},
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{ 6144000, 64, 16000, 3},
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{ 6144000, 64, 48000, 1},
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{ 6144000, 128, 8000, 3},
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{ 8192000, 32, 32000, 4},
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{ 8192000, 64, 16000, 4},
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{ 8192000, 64, 32000, 2},
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{ 8192000, 128, 8000, 4},
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{ 8192000, 128, 16000, 2},
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{ 8192000, 128, 32000, 1},
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{ 8192000, 256, 8000, 2},
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{ 8192000, 256, 16000, 1},
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{ 8192000, 512, 8000, 1},
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{12288000, 32, 32000, 6},
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{12288000, 32, 48000, 4},
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{12288000, 32, 96000, 2},
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{12288000, 32, 192000, 1},
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{12288000, 64, 16000, 6},
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{12288000, 64, 32000, 3},
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{12288000, 64, 48000, 2},
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{12288000, 64, 96000, 1},
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{12288000, 128, 8000, 6},
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{12288000, 128, 16000, 3},
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{12288000, 128, 48000, 1},
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{12288000, 256, 8000, 3},
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{16384000, 64, 32000, 4},
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{16384000, 128, 16000, 4},
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{16384000, 128, 32000, 2},
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{16384000, 256, 8000, 4},
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{16384000, 256, 16000, 2},
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{16384000, 256, 32000, 1},
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{16384000, 512, 8000, 2},
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{16384000, 512, 16000, 1},
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{24576000, 32, 96000, 4},
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{24576000, 32, 192000, 2},
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{24576000, 64, 32000, 6},
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{24576000, 64, 48000, 4},
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{24576000, 64, 96000, 2},
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{24576000, 64, 192000, 1},
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{24576000, 128, 16000, 6},
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{24576000, 128, 32000, 3},
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{24576000, 128, 48000, 2},
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{24576000, 256, 8000, 6},
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{24576000, 256, 16000, 3},
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{24576000, 256, 48000, 1},
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{24576000, 512, 8000, 3},
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{49152000, 32, 192000, 4},
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{49152000, 64, 96000, 4},
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{49152000, 64, 192000, 2},
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{49152000, 128, 32000, 6},
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{49152000, 128, 48000, 4},
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{49152000, 128, 96000, 2},
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{49152000, 128, 192000, 1},
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{49152000, 256, 16000, 6},
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{49152000, 256, 32000, 3},
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{49152000, 256, 48000, 2},
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{49152000, 256, 96000, 1},
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{49152000, 512, 8000, 6},
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{49152000, 512, 16000, 3},
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{49152000, 512, 48000, 1},
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{ 5644800, 32, 22050, 4},
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{ 5644800, 32, 44100, 2},
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{ 5644800, 32, 88200, 1},
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{ 5644800, 64, 11025, 4},
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{ 5644800, 64, 22050, 2},
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{ 5644800, 64, 44100, 1},
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{11289600, 32, 44100, 4},
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{11289600, 32, 88200, 2},
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{11289600, 32, 176400, 1},
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{11289600, 64, 22050, 4},
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{11289600, 64, 44100, 2},
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{11289600, 64, 88200, 1},
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{11289600, 128, 11025, 4},
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{11289600, 128, 22050, 2},
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{11289600, 128, 44100, 1},
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{22579200, 32, 88200, 4},
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{22579200, 32, 176400, 2},
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{22579200, 64, 44100, 4},
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{22579200, 64, 88200, 2},
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{22579200, 64, 176400, 1},
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{22579200, 128, 22050, 4},
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{22579200, 128, 44100, 2},
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{22579200, 128, 88200, 1},
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{22579200, 256, 11025, 4},
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{22579200, 256, 22050, 2},
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{22579200, 256, 44100, 1},
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{45158400, 32, 176400, 4},
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{45158400, 64, 88200, 4},
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{45158400, 64, 176400, 2},
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{45158400, 128, 44100, 4},
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{45158400, 128, 88200, 2},
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{45158400, 128, 176400, 1},
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{45158400, 256, 22050, 4},
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{45158400, 256, 44100, 2},
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{45158400, 256, 88200, 1},
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{45158400, 512, 11025, 4},
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{45158400, 512, 22050, 2},
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{45158400, 512, 44100, 1},
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static const struct snd_pcm_hw_constraint_list cygnus_rate_constraint = {
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.count = ARRAY_SIZE(cygnus_rates),
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.list = cygnus_rates,
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};
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static struct cygnus_aio_port *cygnus_dai_get_portinfo(struct snd_soc_dai *dai)
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@ -679,40 +541,55 @@ static int pll_configure_mclk(struct cygnus_audio *cygaud, u32 mclk,
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return p_entry->pll_ch_num;
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}
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static int cygnus_ssp_set_clocks(struct cygnus_aio_port *aio,
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struct cygnus_audio *cygaud)
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static int cygnus_ssp_set_clocks(struct cygnus_aio_port *aio)
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{
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u32 value, i = 0;
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u32 value;
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u32 mask = 0xf;
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u32 sclk;
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bool found = false;
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const struct _ssp_clk_coeff *p_entry = NULL;
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u32 mclk_rate;
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unsigned int bit_rate;
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unsigned int ratio;
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for (i = 0; i < ARRAY_SIZE(ssp_clk_coeff); i++) {
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p_entry = &ssp_clk_coeff[i];
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if ((p_entry->rate == aio->lrclk) &&
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(p_entry->sclk_rate == aio->bit_per_frame) &&
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(p_entry->mclk == aio->mclk)) {
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found = true;
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break;
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}
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}
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if (!found) {
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bit_rate = aio->bit_per_frame * aio->lrclk;
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/*
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* Check if the bit clock can be generated from the given MCLK.
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* MCLK must be a perfect multiple of bit clock and must be one of the
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* following values... (2,4,6,8,10,12,14)
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*/
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if ((aio->mclk % bit_rate) != 0)
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return -EINVAL;
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ratio = aio->mclk / bit_rate;
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switch (ratio) {
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case 2:
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case 4:
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case 6:
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case 8:
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case 10:
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case 12:
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case 14:
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mclk_rate = ratio / 2;
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break;
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default:
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dev_err(aio->cygaud->dev,
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"No valid match found in ssp_clk_coeff array\n");
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"Invalid combination of MCLK and BCLK\n");
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dev_err(aio->cygaud->dev, "lrclk = %u, bits/frame = %u, mclk = %u\n",
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aio->lrclk, aio->bit_per_frame, aio->mclk);
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return -EINVAL;
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}
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sclk = aio->bit_per_frame;
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if (sclk == 512)
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sclk = 0;
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/* sclks_per_1fs_div = sclk cycles/32 */
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sclk /= 32;
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/* Set sclk rate */
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switch (aio->port_type) {
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case PORT_TDM:
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sclk = aio->bit_per_frame;
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if (sclk == 512)
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sclk = 0;
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/* sclks_per_1fs_div = sclk cycles/32 */
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sclk /= 32;
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/* Set number of bitclks per frame */
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value = readl(aio->cygaud->audio + aio->regs.i2s_cfg);
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value &= ~(mask << I2S_OUT_CFGX_SCLKS_PER_1FS_DIV32);
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@ -731,7 +608,7 @@ static int cygnus_ssp_set_clocks(struct cygnus_aio_port *aio,
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/* Set MCLK_RATE ssp port (spdif and ssp are the same) */
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value = readl(aio->cygaud->audio + aio->regs.i2s_mclk_cfg);
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value &= ~(0xf << I2S_OUT_MCLKRATE_SHIFT);
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value |= (p_entry->mclk_rate << I2S_OUT_MCLKRATE_SHIFT);
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value |= (mclk_rate << I2S_OUT_MCLKRATE_SHIFT);
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writel(value, aio->cygaud->audio + aio->regs.i2s_mclk_cfg);
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dev_dbg(aio->cygaud->dev, "mclk cfg reg = 0x%x\n", value);
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@ -745,7 +622,6 @@ static int cygnus_ssp_hw_params(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct cygnus_aio_port *aio = cygnus_dai_get_portinfo(dai);
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struct cygnus_audio *cygaud = snd_soc_dai_get_drvdata(dai);
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int rate, bitres;
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u32 value;
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u32 mask = 0x1f;
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@ -841,7 +717,7 @@ static int cygnus_ssp_hw_params(struct snd_pcm_substream *substream,
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aio->lrclk = rate;
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if (!aio->is_slave)
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ret = cygnus_ssp_set_clocks(aio, cygaud);
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ret = cygnus_ssp_set_clocks(aio);
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return ret;
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}
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@ -888,6 +764,11 @@ static int cygnus_ssp_startup(struct snd_pcm_substream *substream,
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else
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aio->clk_trace.cap_en = true;
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substream->runtime->hw.rate_min = CYGNUS_RATE_MIN;
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substream->runtime->hw.rate_max = CYGNUS_RATE_MAX;
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snd_pcm_hw_constraint_list(substream->runtime, 0,
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SNDRV_PCM_HW_PARAM_RATE, &cygnus_rate_constraint);
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return 0;
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}
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@ -1261,9 +1142,7 @@ static const struct snd_soc_dai_ops cygnus_ssp_dai_ops = {
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.playback = { \
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.channels_min = 1, \
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.channels_max = 16, \
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.rates = CYGNUS_TDM_RATE | SNDRV_PCM_RATE_88200 | \
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SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | \
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SNDRV_PCM_RATE_192000, \
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.rates = SNDRV_PCM_RATE_KNOT, \
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.formats = SNDRV_PCM_FMTBIT_S8 | \
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SNDRV_PCM_FMTBIT_S16_LE | \
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SNDRV_PCM_FMTBIT_S32_LE, \
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@ -1271,9 +1150,7 @@ static const struct snd_soc_dai_ops cygnus_ssp_dai_ops = {
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.capture = { \
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.channels_min = 2, \
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.channels_max = 16, \
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.rates = CYGNUS_TDM_RATE | SNDRV_PCM_RATE_88200 | \
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SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | \
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SNDRV_PCM_RATE_192000, \
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.rates = SNDRV_PCM_RATE_KNOT, \
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.formats = SNDRV_PCM_FMTBIT_S16_LE | \
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SNDRV_PCM_FMTBIT_S32_LE, \
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}, \
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@ -1293,9 +1170,7 @@ static struct snd_soc_dai_driver cygnus_spdif_dai_info = {
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.playback = {
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.channels_min = 2,
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.channels_max = 2,
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.rates = CYGNUS_TDM_RATE | SNDRV_PCM_RATE_88200 |
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SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
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SNDRV_PCM_RATE_192000,
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.rates = SNDRV_PCM_RATE_KNOT,
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.formats = SNDRV_PCM_FMTBIT_S16_LE |
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SNDRV_PCM_FMTBIT_S32_LE,
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},
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