[PATCH] skge: remove XM phy (untested code)
Remove support for the non-Broadcom genesis based boards. The code is untested, and probably won't work as is. The newer boards are all Yukon based, and only old Genesis board I can find uses Broadcom. Signed-off-by: Stephen Hemminger <shemminger@osdl.org>
This commit is contained in:
Stephen Hemminger
Jeff Garzik
parent
c506a50902
commit
89bf5f231f
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@ -621,16 +621,8 @@ static void skge_led_on(struct skge_hw *hw, int port)
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skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
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skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
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switch (hw->phy_type) {
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case SK_PHY_BCOM:
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xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL,
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PHY_B_PEC_LED_ON);
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break;
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default:
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skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
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skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
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skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
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}
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/* For Broadcom Phy only */
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xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
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} else {
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gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
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gm_phy_write(hw, port, PHY_MARV_LED_OVER,
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@ -651,15 +643,8 @@ static void skge_led_off(struct skge_hw *hw, int port)
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skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
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skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
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switch (hw->phy_type) {
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case SK_PHY_BCOM:
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xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL,
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PHY_B_PEC_LED_OFF);
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break;
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default:
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skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
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skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
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}
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/* Broadcom only */
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xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
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} else {
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gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
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gm_phy_write(hw, port, PHY_MARV_LED_OVER,
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@ -887,21 +872,21 @@ static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
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xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
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v = xm_read16(hw, port, XM_PHY_DATA);
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if (hw->phy_type != SK_PHY_XMAC) {
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for (i = 0; i < PHY_RETRIES; i++) {
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udelay(1);
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if (xm_read16(hw, port, XM_MMU_CMD)
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& XM_MMU_PHY_RDY)
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goto ready;
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}
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printk(KERN_WARNING PFX "%s: phy read timed out\n",
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hw->dev[port]->name);
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return 0;
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ready:
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v = xm_read16(hw, port, XM_PHY_DATA);
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/* Need to wait for external PHY */
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for (i = 0; i < PHY_RETRIES; i++) {
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udelay(1);
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if (xm_read16(hw, port, XM_MMU_CMD)
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& XM_MMU_PHY_RDY)
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goto ready;
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}
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printk(KERN_WARNING PFX "%s: phy read timed out\n",
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hw->dev[port]->name);
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return 0;
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ready:
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v = xm_read16(hw, port, XM_PHY_DATA);
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return v;
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}
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@ -913,7 +898,7 @@ static void xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
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for (i = 0; i < PHY_RETRIES; i++) {
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if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
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goto ready;
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cpu_relax();
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udelay(1);
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}
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printk(KERN_WARNING PFX "%s: phy write failed to come ready\n",
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hw->dev[port]->name);
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@ -970,9 +955,8 @@ static void genesis_reset(struct skge_hw *hw, int port)
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xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
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xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
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/* disable all PHY IRQs */
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if (hw->phy_type == SK_PHY_BCOM)
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xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
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/* disable Broadcom PHY IRQ */
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xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
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xm_outhash(hw, port, XM_HSM, (u8 *) &zero);
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for (i = 0; i < 15; i++)
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@ -1020,54 +1004,55 @@ static void genesis_mac_init(struct skge_hw *hw, int port)
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* GMII mode.
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*/
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spin_lock_bh(&hw->phy_lock);
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if (hw->phy_type != SK_PHY_XMAC) {
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/* Take PHY out of reset. */
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r = skge_read32(hw, B2_GP_IO);
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if (port == 0)
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r |= GP_DIR_0|GP_IO_0;
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else
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r |= GP_DIR_2|GP_IO_2;
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skge_write32(hw, B2_GP_IO, r);
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skge_read32(hw, B2_GP_IO);
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/* External Phy Handling */
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/* Take PHY out of reset. */
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r = skge_read32(hw, B2_GP_IO);
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if (port == 0)
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r |= GP_DIR_0|GP_IO_0;
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else
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r |= GP_DIR_2|GP_IO_2;
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/* Enable GMII mode on the XMAC. */
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xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
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skge_write32(hw, B2_GP_IO, r);
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skge_read32(hw, B2_GP_IO);
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id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
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/* Enable GMII mode on the XMAC. */
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xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
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/* Optimize MDIO transfer by suppressing preamble. */
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xm_write16(hw, port, XM_MMU_CMD,
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xm_read16(hw, port, XM_MMU_CMD)
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| XM_MMU_NO_PRE);
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id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
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if (id1 == PHY_BCOM_ID1_C0) {
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/*
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* Workaround BCOM Errata for the C0 type.
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* Write magic patterns to reserved registers.
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*/
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for (i = 0; i < ARRAY_SIZE(C0hack); i++)
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xm_phy_write(hw, port,
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C0hack[i].reg, C0hack[i].val);
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} else if (id1 == PHY_BCOM_ID1_A1) {
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/*
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* Workaround BCOM Errata for the A1 type.
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* Write magic patterns to reserved registers.
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*/
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for (i = 0; i < ARRAY_SIZE(A1hack); i++)
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xm_phy_write(hw, port,
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A1hack[i].reg, A1hack[i].val);
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}
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/* Optimize MDIO transfer by suppressing preamble. */
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xm_write16(hw, port, XM_MMU_CMD,
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xm_read16(hw, port, XM_MMU_CMD)
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| XM_MMU_NO_PRE);
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if (id1 == PHY_BCOM_ID1_C0) {
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/*
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* Workaround BCOM Errata (#10523) for all BCom PHYs.
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* Disable Power Management after reset.
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* Workaround BCOM Errata for the C0 type.
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* Write magic patterns to reserved registers.
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*/
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r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
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xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r | PHY_B_AC_DIS_PM);
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for (i = 0; i < ARRAY_SIZE(C0hack); i++)
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xm_phy_write(hw, port,
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C0hack[i].reg, C0hack[i].val);
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} else if (id1 == PHY_BCOM_ID1_A1) {
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/*
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* Workaround BCOM Errata for the A1 type.
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* Write magic patterns to reserved registers.
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*/
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for (i = 0; i < ARRAY_SIZE(A1hack); i++)
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xm_phy_write(hw, port,
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A1hack[i].reg, A1hack[i].val);
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}
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/*
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* Workaround BCOM Errata (#10523) for all BCom PHYs.
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* Disable Power Management after reset.
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*/
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r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
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xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r | PHY_B_AC_DIS_PM);
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/* Dummy read */
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xm_read16(hw, port, XM_ISRC);
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@ -1098,8 +1083,8 @@ static void genesis_mac_init(struct skge_hw *hw, int port)
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*/
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r = xm_read32(hw, port, XM_MODE);
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xm_write32(hw, port, XM_MODE,
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XM_MD_RX_CRCE|XM_MD_RX_LONG|XM_MD_RX_RUNT|
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XM_MD_RX_ERR|XM_MD_RX_IRLE);
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XM_MD_RX_CRCE|XM_MD_RX_LONG|XM_MD_RX_RUNT|
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XM_MD_RX_ERR|XM_MD_RX_IRLE);
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xm_outaddr(hw, port, XM_SA, hw->dev[port]->dev_addr);
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xm_outaddr(hw, port, XM_EXM(0), hw->dev[port]->dev_addr);
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@ -1150,103 +1135,70 @@ static void genesis_mac_init(struct skge_hw *hw, int port)
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else
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xm_write16(hw, port, XM_RX_CMD, r & ~(XM_RX_BIG_PK_OK));
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switch (hw->phy_type) {
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case SK_PHY_XMAC:
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if (skge->autoneg == AUTONEG_ENABLE) {
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ctrl1 = PHY_X_AN_FD | PHY_X_AN_HD;
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/* Broadcom phy initialization */
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ctrl1 = PHY_CT_SP1000;
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ctrl2 = 0;
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ctrl3 = PHY_AN_CSMA;
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ctrl4 = PHY_B_PEC_EN_LTR;
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ctrl5 = PHY_B_AC_TX_TST;
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switch (skge->flow_control) {
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case FLOW_MODE_NONE:
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ctrl1 |= PHY_X_P_NO_PAUSE;
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break;
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case FLOW_MODE_LOC_SEND:
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ctrl1 |= PHY_X_P_ASYM_MD;
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break;
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case FLOW_MODE_SYMMETRIC:
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ctrl1 |= PHY_X_P_SYM_MD;
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break;
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case FLOW_MODE_REM_SEND:
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ctrl1 |= PHY_X_P_BOTH_MD;
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break;
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}
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if (skge->autoneg == AUTONEG_ENABLE) {
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/*
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* Workaround BCOM Errata #1 for the C5 type.
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* 1000Base-T Link Acquisition Failure in Slave Mode
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* Set Repeater/DTE bit 10 of the 1000Base-T Control Register
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*/
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ctrl2 |= PHY_B_1000C_RD;
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if (skge->advertising & ADVERTISED_1000baseT_Half)
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ctrl2 |= PHY_B_1000C_AHD;
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if (skge->advertising & ADVERTISED_1000baseT_Full)
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ctrl2 |= PHY_B_1000C_AFD;
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xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl1);
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ctrl2 = PHY_CT_ANE | PHY_CT_RE_CFG;
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} else {
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ctrl2 = 0;
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if (skge->duplex == DUPLEX_FULL)
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ctrl2 |= PHY_CT_DUP_MD;
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/* Set Flow-control capabilities */
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switch (skge->flow_control) {
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case FLOW_MODE_NONE:
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ctrl3 |= PHY_B_P_NO_PAUSE;
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break;
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case FLOW_MODE_LOC_SEND:
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ctrl3 |= PHY_B_P_ASYM_MD;
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break;
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case FLOW_MODE_SYMMETRIC:
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ctrl3 |= PHY_B_P_SYM_MD;
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break;
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case FLOW_MODE_REM_SEND:
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ctrl3 |= PHY_B_P_BOTH_MD;
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break;
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}
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xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl2);
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break;
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/* Restart Auto-negotiation */
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ctrl1 |= PHY_CT_ANE | PHY_CT_RE_CFG;
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} else {
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if (skge->duplex == DUPLEX_FULL)
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ctrl1 |= PHY_CT_DUP_MD;
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case SK_PHY_BCOM:
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ctrl1 = PHY_CT_SP1000;
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ctrl2 = 0;
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ctrl3 = PHY_AN_CSMA;
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ctrl4 = PHY_B_PEC_EN_LTR;
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ctrl5 = PHY_B_AC_TX_TST;
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if (skge->autoneg == AUTONEG_ENABLE) {
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/*
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* Workaround BCOM Errata #1 for the C5 type.
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* 1000Base-T Link Acquisition Failure in Slave Mode
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* Set Repeater/DTE bit 10 of the 1000Base-T Control Register
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*/
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ctrl2 |= PHY_B_1000C_RD;
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if (skge->advertising & ADVERTISED_1000baseT_Half)
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ctrl2 |= PHY_B_1000C_AHD;
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if (skge->advertising & ADVERTISED_1000baseT_Full)
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ctrl2 |= PHY_B_1000C_AFD;
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/* Set Flow-control capabilities */
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switch (skge->flow_control) {
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case FLOW_MODE_NONE:
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ctrl3 |= PHY_B_P_NO_PAUSE;
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break;
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case FLOW_MODE_LOC_SEND:
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ctrl3 |= PHY_B_P_ASYM_MD;
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break;
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case FLOW_MODE_SYMMETRIC:
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ctrl3 |= PHY_B_P_SYM_MD;
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break;
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case FLOW_MODE_REM_SEND:
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ctrl3 |= PHY_B_P_BOTH_MD;
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break;
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}
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/* Restart Auto-negotiation */
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ctrl1 |= PHY_CT_ANE | PHY_CT_RE_CFG;
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} else {
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if (skge->duplex == DUPLEX_FULL)
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ctrl1 |= PHY_CT_DUP_MD;
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ctrl2 |= PHY_B_1000C_MSE; /* set it to Slave */
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}
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xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, ctrl2);
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xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV, ctrl3);
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if (skge->netdev->mtu > ETH_DATA_LEN) {
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ctrl4 |= PHY_B_PEC_HIGH_LA;
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ctrl5 |= PHY_B_AC_LONG_PACK;
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xm_phy_write(hw, port,PHY_BCOM_AUX_CTRL, ctrl5);
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}
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xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ctrl4);
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xm_phy_write(hw, port, PHY_BCOM_CTRL, ctrl1);
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break;
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ctrl2 |= PHY_B_1000C_MSE; /* set it to Slave */
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}
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xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, ctrl2);
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xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV, ctrl3);
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if (skge->netdev->mtu > ETH_DATA_LEN) {
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ctrl4 |= PHY_B_PEC_HIGH_LA;
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ctrl5 |= PHY_B_AC_LONG_PACK;
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xm_phy_write(hw, port,PHY_BCOM_AUX_CTRL, ctrl5);
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}
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xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ctrl4);
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xm_phy_write(hw, port, PHY_BCOM_CTRL, ctrl1);
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spin_unlock_bh(&hw->phy_lock);
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/* Clear MIB counters */
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xm_write16(hw, port, XM_STAT_CMD,
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XM_SC_CLR_RXC | XM_SC_CLR_TXC);
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XM_SC_CLR_RXC | XM_SC_CLR_TXC);
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/* Clear two times according to Errata #3 */
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xm_write16(hw, port, XM_STAT_CMD,
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XM_SC_CLR_RXC | XM_SC_CLR_TXC);
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XM_SC_CLR_RXC | XM_SC_CLR_TXC);
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/* Start polling for link status */
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mod_timer(&skge->link_check, jiffies + LINK_POLL_HZ);
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@ -1256,6 +1208,7 @@ static void genesis_stop(struct skge_port *skge)
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{
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struct skge_hw *hw = skge->hw;
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int port = skge->port;
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u32 reg;
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/* Clear Tx packet arbiter timeout IRQ */
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skge_write16(hw, B3_PA_CTRL,
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@ -1273,19 +1226,16 @@ static void genesis_stop(struct skge_port *skge)
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skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
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/* For external PHYs there must be special handling */
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if (hw->phy_type != SK_PHY_XMAC) {
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u32 reg = skge_read32(hw, B2_GP_IO);
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if (port == 0) {
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reg |= GP_DIR_0;
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reg &= ~GP_IO_0;
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} else {
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reg |= GP_DIR_2;
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reg &= ~GP_IO_2;
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}
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skge_write32(hw, B2_GP_IO, reg);
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skge_read32(hw, B2_GP_IO);
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reg = skge_read32(hw, B2_GP_IO);
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if (port == 0) {
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reg |= GP_DIR_0;
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reg &= ~GP_IO_0;
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} else {
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reg |= GP_DIR_2;
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reg &= ~GP_IO_2;
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}
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skge_write32(hw, B2_GP_IO, reg);
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skge_read32(hw, B2_GP_IO);
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xm_write16(hw, port, XM_MMU_CMD,
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xm_read16(hw, port, XM_MMU_CMD)
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|
|
@ -1329,16 +1279,6 @@ static void genesis_mac_intr(struct skge_hw *hw, int port)
|
|||
u16 status = xm_read16(hw, port, XM_ISRC);
|
||||
|
||||
pr_debug("genesis_intr status %x\n", status);
|
||||
if (hw->phy_type == SK_PHY_XMAC) {
|
||||
/* LInk down, start polling for state change */
|
||||
if (status & XM_IS_INP_ASS) {
|
||||
xm_write16(hw, port, XM_IMSK,
|
||||
xm_read16(hw, port, XM_IMSK) | XM_IS_INP_ASS);
|
||||
mod_timer(&skge->link_check, jiffies + LINK_POLL_HZ);
|
||||
}
|
||||
else if (status & XM_IS_AND)
|
||||
mod_timer(&skge->link_check, jiffies + LINK_POLL_HZ);
|
||||
}
|
||||
|
||||
if (status & XM_IS_TXF_UR) {
|
||||
xm_write32(hw, port, XM_MODE, XM_MD_FTF);
|
||||
|
|
@ -1458,28 +1398,25 @@ static void genesis_link_up(struct skge_port *skge)
|
|||
xm_write32(hw, port, XM_MODE, mode);
|
||||
|
||||
msk = XM_DEF_MSK;
|
||||
if (hw->phy_type != SK_PHY_XMAC)
|
||||
msk |= XM_IS_INP_ASS; /* disable GP0 interrupt bit */
|
||||
/* disable GP0 interrupt bit for external Phy */
|
||||
msk |= XM_IS_INP_ASS;
|
||||
|
||||
xm_write16(hw, port, XM_IMSK, msk);
|
||||
xm_read16(hw, port, XM_ISRC);
|
||||
|
||||
/* get MMU Command Reg. */
|
||||
cmd = xm_read16(hw, port, XM_MMU_CMD);
|
||||
if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
|
||||
if (skge->duplex == DUPLEX_FULL)
|
||||
cmd |= XM_MMU_GMII_FD;
|
||||
|
||||
if (hw->phy_type == SK_PHY_BCOM) {
|
||||
/*
|
||||
* Workaround BCOM Errata (#10523) for all BCom Phys
|
||||
* Enable Power Management after link up
|
||||
*/
|
||||
xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
|
||||
xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
|
||||
& ~PHY_B_AC_DIS_PM);
|
||||
xm_phy_write(hw, port, PHY_BCOM_INT_MASK,
|
||||
PHY_B_DEF_MSK);
|
||||
}
|
||||
/*
|
||||
* Workaround BCOM Errata (#10523) for all BCom Phys
|
||||
* Enable Power Management after link up
|
||||
*/
|
||||
xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
|
||||
xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
|
||||
& ~PHY_B_AC_DIS_PM);
|
||||
xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
|
||||
|
||||
/* enable Rx/Tx */
|
||||
xm_write16(hw, port, XM_MMU_CMD,
|
||||
|
|
@ -1551,25 +1488,12 @@ static void skge_link_timer(unsigned long __arg)
|
|||
{
|
||||
struct skge_port *skge = (struct skge_port *) __arg;
|
||||
struct skge_hw *hw = skge->hw;
|
||||
int port = skge->port;
|
||||
|
||||
if (hw->chip_id != CHIP_ID_GENESIS || !netif_running(skge->netdev))
|
||||
return;
|
||||
|
||||
spin_lock_bh(&hw->phy_lock);
|
||||
if (hw->phy_type == SK_PHY_BCOM)
|
||||
genesis_bcom_intr(skge);
|
||||
else {
|
||||
int i;
|
||||
for (i = 0; i < 3; i++)
|
||||
if (xm_read16(hw, port, XM_ISRC) & XM_IS_INP_ASS)
|
||||
break;
|
||||
|
||||
if (i == 3)
|
||||
mod_timer(&skge->link_check, jiffies + LINK_POLL_HZ);
|
||||
else
|
||||
genesis_link_up(skge);
|
||||
}
|
||||
genesis_bcom_intr(skge);
|
||||
spin_unlock_bh(&hw->phy_lock);
|
||||
}
|
||||
|
||||
|
|
@ -2737,7 +2661,7 @@ static void skge_extirq(unsigned long data)
|
|||
|
||||
if (hw->chip_id != CHIP_ID_GENESIS)
|
||||
yukon_phy_intr(skge);
|
||||
else if (hw->phy_type == SK_PHY_BCOM)
|
||||
else
|
||||
genesis_bcom_intr(skge);
|
||||
}
|
||||
}
|
||||
|
|
@ -2886,9 +2810,6 @@ static int skge_reset(struct skge_hw *hw)
|
|||
switch (hw->chip_id) {
|
||||
case CHIP_ID_GENESIS:
|
||||
switch (hw->phy_type) {
|
||||
case SK_PHY_XMAC:
|
||||
hw->phy_addr = PHY_ADDR_XMAC;
|
||||
break;
|
||||
case SK_PHY_BCOM:
|
||||
hw->phy_addr = PHY_ADDR_BCOM;
|
||||
break;
|
||||
|
|
|
|||
Loading…
Reference in New Issue