net/mlx5_core: Add pci error handlers to mlx5_core driver
This patch implement the pci_error_handlers for mlx5_core which allow the driver to recover from PCI error. Once an error is detected in the PCI, the mlx5_pci_err_detected is called and it: 1) Marks the device to be in 'Internal Error' state. 2) Dispatches an event to the mlx5_ib to flush all the outstanding cqes with error. 3) Returns all the on going commands with error. 4) Unloads the driver. Afterwards, the FW is reset and mlx5_pci_slot_reset is called and it enables the device and restore it's pci state. If the later succeeds, mlx5_pci_resume is called, and it loads the SW stack. Signed-off-by: Majd Dibbiny <majd@mellanox.com> Signed-off-by: Eli Cohen <eli@mellanox.com> Signed-off-by: Or Gerlitz <ogerlitz@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
parent
fd76ee4da5
commit
89d44f0a6c
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@ -256,8 +256,154 @@ static void dump_buf(void *buf, int size, int data_only, int offset)
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enum {
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MLX5_DRIVER_STATUS_ABORTED = 0xfe,
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MLX5_DRIVER_SYND = 0xbadd00de,
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};
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static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op,
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u32 *synd, u8 *status)
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{
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*synd = 0;
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*status = 0;
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switch (op) {
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case MLX5_CMD_OP_TEARDOWN_HCA:
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case MLX5_CMD_OP_DISABLE_HCA:
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case MLX5_CMD_OP_MANAGE_PAGES:
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case MLX5_CMD_OP_DESTROY_MKEY:
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case MLX5_CMD_OP_DESTROY_EQ:
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case MLX5_CMD_OP_DESTROY_CQ:
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case MLX5_CMD_OP_DESTROY_QP:
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case MLX5_CMD_OP_DESTROY_PSV:
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case MLX5_CMD_OP_DESTROY_SRQ:
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case MLX5_CMD_OP_DESTROY_XRC_SRQ:
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case MLX5_CMD_OP_DESTROY_DCT:
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case MLX5_CMD_OP_DEALLOC_Q_COUNTER:
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case MLX5_CMD_OP_DEALLOC_PD:
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case MLX5_CMD_OP_DEALLOC_UAR:
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case MLX5_CMD_OP_DETTACH_FROM_MCG:
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case MLX5_CMD_OP_DEALLOC_XRCD:
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case MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN:
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case MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT:
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case MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY:
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case MLX5_CMD_OP_DESTROY_TIR:
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case MLX5_CMD_OP_DESTROY_SQ:
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case MLX5_CMD_OP_DESTROY_RQ:
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case MLX5_CMD_OP_DESTROY_RMP:
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case MLX5_CMD_OP_DESTROY_TIS:
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case MLX5_CMD_OP_DESTROY_RQT:
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case MLX5_CMD_OP_DESTROY_FLOW_TABLE:
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case MLX5_CMD_OP_DESTROY_FLOW_GROUP:
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case MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY:
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return MLX5_CMD_STAT_OK;
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case MLX5_CMD_OP_QUERY_HCA_CAP:
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case MLX5_CMD_OP_QUERY_ADAPTER:
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case MLX5_CMD_OP_INIT_HCA:
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case MLX5_CMD_OP_ENABLE_HCA:
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case MLX5_CMD_OP_QUERY_PAGES:
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case MLX5_CMD_OP_SET_HCA_CAP:
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case MLX5_CMD_OP_QUERY_ISSI:
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case MLX5_CMD_OP_SET_ISSI:
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case MLX5_CMD_OP_CREATE_MKEY:
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case MLX5_CMD_OP_QUERY_MKEY:
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case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS:
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case MLX5_CMD_OP_PAGE_FAULT_RESUME:
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case MLX5_CMD_OP_CREATE_EQ:
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case MLX5_CMD_OP_QUERY_EQ:
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case MLX5_CMD_OP_GEN_EQE:
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case MLX5_CMD_OP_CREATE_CQ:
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case MLX5_CMD_OP_QUERY_CQ:
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case MLX5_CMD_OP_MODIFY_CQ:
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case MLX5_CMD_OP_CREATE_QP:
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case MLX5_CMD_OP_RST2INIT_QP:
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case MLX5_CMD_OP_INIT2RTR_QP:
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case MLX5_CMD_OP_RTR2RTS_QP:
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case MLX5_CMD_OP_RTS2RTS_QP:
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case MLX5_CMD_OP_SQERR2RTS_QP:
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case MLX5_CMD_OP_2ERR_QP:
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case MLX5_CMD_OP_2RST_QP:
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case MLX5_CMD_OP_QUERY_QP:
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case MLX5_CMD_OP_SQD_RTS_QP:
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case MLX5_CMD_OP_INIT2INIT_QP:
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case MLX5_CMD_OP_CREATE_PSV:
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case MLX5_CMD_OP_CREATE_SRQ:
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case MLX5_CMD_OP_QUERY_SRQ:
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case MLX5_CMD_OP_ARM_RQ:
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case MLX5_CMD_OP_CREATE_XRC_SRQ:
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case MLX5_CMD_OP_QUERY_XRC_SRQ:
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case MLX5_CMD_OP_ARM_XRC_SRQ:
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case MLX5_CMD_OP_CREATE_DCT:
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case MLX5_CMD_OP_DRAIN_DCT:
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case MLX5_CMD_OP_QUERY_DCT:
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case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION:
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case MLX5_CMD_OP_QUERY_VPORT_STATE:
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case MLX5_CMD_OP_MODIFY_VPORT_STATE:
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case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT:
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case MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT:
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case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT:
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case MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT:
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case MLX5_CMD_OP_QUERY_ROCE_ADDRESS:
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case MLX5_CMD_OP_SET_ROCE_ADDRESS:
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case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT:
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case MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT:
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case MLX5_CMD_OP_QUERY_HCA_VPORT_GID:
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case MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY:
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case MLX5_CMD_OP_QUERY_VPORT_COUNTER:
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case MLX5_CMD_OP_ALLOC_Q_COUNTER:
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case MLX5_CMD_OP_QUERY_Q_COUNTER:
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case MLX5_CMD_OP_ALLOC_PD:
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case MLX5_CMD_OP_ALLOC_UAR:
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case MLX5_CMD_OP_CONFIG_INT_MODERATION:
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case MLX5_CMD_OP_ACCESS_REG:
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case MLX5_CMD_OP_ATTACH_TO_MCG:
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case MLX5_CMD_OP_GET_DROPPED_PACKET_LOG:
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case MLX5_CMD_OP_MAD_IFC:
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case MLX5_CMD_OP_QUERY_MAD_DEMUX:
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case MLX5_CMD_OP_SET_MAD_DEMUX:
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case MLX5_CMD_OP_NOP:
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case MLX5_CMD_OP_ALLOC_XRCD:
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case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN:
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case MLX5_CMD_OP_QUERY_CONG_STATUS:
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case MLX5_CMD_OP_MODIFY_CONG_STATUS:
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case MLX5_CMD_OP_QUERY_CONG_PARAMS:
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case MLX5_CMD_OP_MODIFY_CONG_PARAMS:
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case MLX5_CMD_OP_QUERY_CONG_STATISTICS:
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case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:
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case MLX5_CMD_OP_SET_L2_TABLE_ENTRY:
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case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY:
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case MLX5_CMD_OP_CREATE_TIR:
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case MLX5_CMD_OP_MODIFY_TIR:
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case MLX5_CMD_OP_QUERY_TIR:
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case MLX5_CMD_OP_CREATE_SQ:
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case MLX5_CMD_OP_MODIFY_SQ:
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case MLX5_CMD_OP_QUERY_SQ:
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case MLX5_CMD_OP_CREATE_RQ:
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case MLX5_CMD_OP_MODIFY_RQ:
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case MLX5_CMD_OP_QUERY_RQ:
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case MLX5_CMD_OP_CREATE_RMP:
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case MLX5_CMD_OP_MODIFY_RMP:
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case MLX5_CMD_OP_QUERY_RMP:
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case MLX5_CMD_OP_CREATE_TIS:
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case MLX5_CMD_OP_MODIFY_TIS:
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case MLX5_CMD_OP_QUERY_TIS:
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case MLX5_CMD_OP_CREATE_RQT:
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case MLX5_CMD_OP_MODIFY_RQT:
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case MLX5_CMD_OP_QUERY_RQT:
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case MLX5_CMD_OP_CREATE_FLOW_TABLE:
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case MLX5_CMD_OP_QUERY_FLOW_TABLE:
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case MLX5_CMD_OP_CREATE_FLOW_GROUP:
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case MLX5_CMD_OP_QUERY_FLOW_GROUP:
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case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:
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case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY:
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*status = MLX5_DRIVER_STATUS_ABORTED;
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*synd = MLX5_DRIVER_SYND;
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return -EIO;
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default:
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mlx5_core_err(dev, "Unknown FW command (%d)\n", op);
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return -EINVAL;
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}
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}
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const char *mlx5_command_str(int command)
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{
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switch (command) {
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@ -592,6 +738,16 @@ static int wait_func(struct mlx5_core_dev *dev, struct mlx5_cmd_work_ent *ent)
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return err;
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}
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static __be32 *get_synd_ptr(struct mlx5_outbox_hdr *out)
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{
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return &out->syndrome;
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}
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static u8 *get_status_ptr(struct mlx5_outbox_hdr *out)
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{
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return &out->status;
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}
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/* Notes:
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* 1. Callback functions may not sleep
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* 2. page queue commands do not support asynchrous completion
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@ -1200,6 +1356,11 @@ static struct mlx5_cmd_msg *alloc_msg(struct mlx5_core_dev *dev, int in_size,
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return msg;
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}
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static u16 opcode_from_in(struct mlx5_inbox_hdr *in)
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{
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return be16_to_cpu(in->opcode);
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}
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static int is_manage_pages(struct mlx5_inbox_hdr *in)
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{
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return be16_to_cpu(in->opcode) == MLX5_CMD_OP_MANAGE_PAGES;
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@ -1214,6 +1375,15 @@ static int cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
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gfp_t gfp;
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int err;
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u8 status = 0;
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u32 drv_synd;
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if (pci_channel_offline(dev->pdev) ||
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dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
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err = mlx5_internal_err_ret_value(dev, opcode_from_in(in), &drv_synd, &status);
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*get_synd_ptr(out) = cpu_to_be32(drv_synd);
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*get_status_ptr(out) = status;
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return err;
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}
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pages_queue = is_manage_pages(in);
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gfp = callback ? GFP_ATOMIC : GFP_KERNEL;
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@ -34,6 +34,7 @@
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#include <linux/module.h>
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#include <linux/random.h>
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#include <linux/vmalloc.h>
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#include <linux/hardirq.h>
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#include <linux/mlx5/driver.h>
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#include <linux/mlx5/cmd.h>
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#include "mlx5_core.h"
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@ -68,6 +69,29 @@ static u8 get_nic_interface(struct mlx5_core_dev *dev)
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return (ioread32be(&dev->iseg->cmdq_addr_l_sz) >> 8) & 3;
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}
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static void trigger_cmd_completions(struct mlx5_core_dev *dev)
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{
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unsigned long flags;
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u64 vector;
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/* wait for pending handlers to complete */
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synchronize_irq(dev->priv.msix_arr[MLX5_EQ_VEC_CMD].vector);
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spin_lock_irqsave(&dev->cmd.alloc_lock, flags);
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vector = ~dev->cmd.bitmask & ((1ul << (1 << dev->cmd.log_sz)) - 1);
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if (!vector)
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goto no_trig;
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vector |= MLX5_TRIGGERED_CMD_COMP;
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spin_unlock_irqrestore(&dev->cmd.alloc_lock, flags);
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mlx5_core_dbg(dev, "vector 0x%llx\n", vector);
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mlx5_cmd_comp_handler(dev, vector);
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return;
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no_trig:
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spin_unlock_irqrestore(&dev->cmd.alloc_lock, flags);
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}
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static int in_fatal(struct mlx5_core_dev *dev)
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{
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struct mlx5_core_health *health = &dev->priv.health;
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@ -82,6 +106,43 @@ static int in_fatal(struct mlx5_core_dev *dev)
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return 0;
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}
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void mlx5_enter_error_state(struct mlx5_core_dev *dev)
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{
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if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR)
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return;
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mlx5_core_err(dev, "start\n");
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if (pci_channel_offline(dev->pdev) || in_fatal(dev))
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dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
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mlx5_core_event(dev, MLX5_DEV_EVENT_SYS_ERROR, 0);
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mlx5_core_err(dev, "end\n");
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}
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static void mlx5_handle_bad_state(struct mlx5_core_dev *dev)
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{
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u8 nic_interface = get_nic_interface(dev);
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switch (nic_interface) {
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case MLX5_NIC_IFC_FULL:
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mlx5_core_warn(dev, "Expected to see disabled NIC but it is full driver\n");
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break;
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case MLX5_NIC_IFC_DISABLED:
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mlx5_core_warn(dev, "starting teardown\n");
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break;
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case MLX5_NIC_IFC_NO_DRAM_NIC:
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mlx5_core_warn(dev, "Expected to see disabled NIC but it is no dram nic\n");
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break;
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default:
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mlx5_core_warn(dev, "Expected to see disabled NIC but it is has invalid value %d\n",
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nic_interface);
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}
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mlx5_disable_device(dev);
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}
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static void health_care(struct work_struct *work)
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{
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struct mlx5_core_health *health;
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@ -92,6 +153,7 @@ static void health_care(struct work_struct *work)
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priv = container_of(health, struct mlx5_priv, health);
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dev = container_of(priv, struct mlx5_core_dev, priv);
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mlx5_core_warn(dev, "handling bad device here\n");
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mlx5_handle_bad_state(dev);
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}
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static const char *hsynd_str(u8 synd)
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@ -147,6 +209,10 @@ static void print_health_info(struct mlx5_core_dev *dev)
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u32 fw;
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int i;
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/* If the syndrom is 0, the device is OK and no need to print buffer */
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if (!ioread8(&h->synd))
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return;
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for (i = 0; i < ARRAY_SIZE(h->assert_var); i++)
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dev_err(&dev->pdev->dev, "assert_var[%d] 0x%08x\n", i, ioread32be(h->assert_var + i));
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@ -178,6 +244,12 @@ static void poll_health(unsigned long data)
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struct mlx5_core_health *health = &dev->priv.health;
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u32 count;
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if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
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trigger_cmd_completions(dev);
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mod_timer(&health->timer, get_next_poll_jiffies());
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return;
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}
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count = ioread32be(health->health_counter);
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if (count == health->prev)
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++health->miss_counter;
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@ -45,6 +45,7 @@
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#include <linux/mlx5/srq.h>
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#include <linux/debugfs.h>
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#include <linux/kmod.h>
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#include <linux/delay.h>
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#include <linux/mlx5/mlx5_ifc.h>
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#include "mlx5_core.h"
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@ -181,6 +182,34 @@ static int set_dma_caps(struct pci_dev *pdev)
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return err;
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}
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static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
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{
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struct pci_dev *pdev = dev->pdev;
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int err = 0;
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mutex_lock(&dev->pci_status_mutex);
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if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
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err = pci_enable_device(pdev);
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if (!err)
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dev->pci_status = MLX5_PCI_STATUS_ENABLED;
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}
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mutex_unlock(&dev->pci_status_mutex);
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return err;
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}
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static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
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{
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struct pci_dev *pdev = dev->pdev;
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mutex_lock(&dev->pci_status_mutex);
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if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
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pci_disable_device(pdev);
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dev->pci_status = MLX5_PCI_STATUS_DISABLED;
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}
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mutex_unlock(&dev->pci_status_mutex);
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}
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static int request_bar(struct pci_dev *pdev)
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{
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int err = 0;
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@ -807,7 +836,7 @@ static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
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if (!priv->dbg_root)
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return -ENOMEM;
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err = pci_enable_device(pdev);
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err = mlx5_pci_enable_device(dev);
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if (err) {
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dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
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goto err_dbg;
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@ -841,7 +870,7 @@ err_clr_master:
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pci_clear_master(dev->pdev);
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release_bar(dev->pdev);
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err_disable:
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pci_disable_device(dev->pdev);
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mlx5_pci_disable_device(dev);
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err_dbg:
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debugfs_remove(priv->dbg_root);
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@ -853,7 +882,7 @@ static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
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iounmap(dev->iseg);
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||||
pci_clear_master(dev->pdev);
|
||||
release_bar(dev->pdev);
|
||||
pci_disable_device(dev->pdev);
|
||||
mlx5_pci_disable_device(dev);
|
||||
debugfs_remove(priv->dbg_root);
|
||||
}
|
||||
|
||||
|
@ -863,13 +892,25 @@ static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
|
|||
struct pci_dev *pdev = dev->pdev;
|
||||
int err;
|
||||
|
||||
mutex_lock(&dev->intf_state_mutex);
|
||||
if (dev->interface_state == MLX5_INTERFACE_STATE_UP) {
|
||||
dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n",
|
||||
__func__);
|
||||
goto out;
|
||||
}
|
||||
|
||||
dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
|
||||
fw_rev_min(dev), fw_rev_sub(dev));
|
||||
|
||||
/* on load removing any previous indication of internal error, device is
|
||||
* up
|
||||
*/
|
||||
dev->state = MLX5_DEVICE_STATE_UP;
|
||||
|
||||
err = mlx5_cmd_init(dev);
|
||||
if (err) {
|
||||
dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
|
||||
return err;
|
||||
goto out_err;
|
||||
}
|
||||
|
||||
mlx5_pagealloc_init(dev);
|
||||
|
@ -994,6 +1035,10 @@ static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
|
|||
if (err)
|
||||
pr_info("failed request module on %s\n", MLX5_IB_MOD);
|
||||
|
||||
dev->interface_state = MLX5_INTERFACE_STATE_UP;
|
||||
out:
|
||||
mutex_unlock(&dev->intf_state_mutex);
|
||||
|
||||
return 0;
|
||||
|
||||
err_reg_dev:
|
||||
|
@ -1024,7 +1069,7 @@ err_stop_poll:
|
|||
mlx5_stop_health_poll(dev);
|
||||
if (mlx5_cmd_teardown_hca(dev)) {
|
||||
dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
|
||||
return err;
|
||||
goto out_err;
|
||||
}
|
||||
|
||||
err_pagealloc_stop:
|
||||
|
@ -1040,13 +1085,23 @@ err_pagealloc_cleanup:
|
|||
mlx5_pagealloc_cleanup(dev);
|
||||
mlx5_cmd_cleanup(dev);
|
||||
|
||||
out_err:
|
||||
dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
|
||||
mutex_unlock(&dev->intf_state_mutex);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
|
||||
{
|
||||
int err;
|
||||
int err = 0;
|
||||
|
||||
mutex_lock(&dev->intf_state_mutex);
|
||||
if (dev->interface_state == MLX5_INTERFACE_STATE_DOWN) {
|
||||
dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n",
|
||||
__func__);
|
||||
goto out;
|
||||
}
|
||||
mlx5_unregister_device(dev);
|
||||
mlx5_cleanup_mr_table(dev);
|
||||
mlx5_cleanup_srq_table(dev);
|
||||
|
@ -1072,10 +1127,12 @@ static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
|
|||
mlx5_cmd_cleanup(dev);
|
||||
|
||||
out:
|
||||
dev->interface_state = MLX5_INTERFACE_STATE_DOWN;
|
||||
mutex_unlock(&dev->intf_state_mutex);
|
||||
return err;
|
||||
}
|
||||
|
||||
static void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
|
||||
void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
|
||||
unsigned long param)
|
||||
{
|
||||
struct mlx5_priv *priv = &dev->priv;
|
||||
|
@ -1125,6 +1182,8 @@ static int init_one(struct pci_dev *pdev,
|
|||
|
||||
INIT_LIST_HEAD(&priv->ctx_list);
|
||||
spin_lock_init(&priv->ctx_lock);
|
||||
mutex_init(&dev->pci_status_mutex);
|
||||
mutex_init(&dev->intf_state_mutex);
|
||||
err = mlx5_pci_init(dev, priv);
|
||||
if (err) {
|
||||
dev_err(&pdev->dev, "mlx5_pci_init failed with error code %d\n", err);
|
||||
|
@ -1172,6 +1231,112 @@ static void remove_one(struct pci_dev *pdev)
|
|||
kfree(dev);
|
||||
}
|
||||
|
||||
static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
|
||||
pci_channel_state_t state)
|
||||
{
|
||||
struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
|
||||
struct mlx5_priv *priv = &dev->priv;
|
||||
|
||||
dev_info(&pdev->dev, "%s was called\n", __func__);
|
||||
mlx5_enter_error_state(dev);
|
||||
mlx5_unload_one(dev, priv);
|
||||
mlx5_pci_disable_device(dev);
|
||||
return state == pci_channel_io_perm_failure ?
|
||||
PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
|
||||
}
|
||||
|
||||
static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
|
||||
{
|
||||
struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
|
||||
int err = 0;
|
||||
|
||||
dev_info(&pdev->dev, "%s was called\n", __func__);
|
||||
|
||||
err = mlx5_pci_enable_device(dev);
|
||||
if (err) {
|
||||
dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n"
|
||||
, __func__, err);
|
||||
return PCI_ERS_RESULT_DISCONNECT;
|
||||
}
|
||||
pci_set_master(pdev);
|
||||
pci_set_power_state(pdev, PCI_D0);
|
||||
pci_restore_state(pdev);
|
||||
|
||||
return err ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
|
||||
}
|
||||
|
||||
void mlx5_disable_device(struct mlx5_core_dev *dev)
|
||||
{
|
||||
mlx5_pci_err_detected(dev->pdev, 0);
|
||||
}
|
||||
|
||||
/* wait for the device to show vital signs. For now we check
|
||||
* that we can read the device ID and that the health buffer
|
||||
* shows a non zero value which is different than 0xffffffff
|
||||
*/
|
||||
static void wait_vital(struct pci_dev *pdev)
|
||||
{
|
||||
struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
|
||||
struct mlx5_core_health *health = &dev->priv.health;
|
||||
const int niter = 100;
|
||||
u32 count;
|
||||
u16 did;
|
||||
int i;
|
||||
|
||||
/* Wait for firmware to be ready after reset */
|
||||
msleep(1000);
|
||||
for (i = 0; i < niter; i++) {
|
||||
if (pci_read_config_word(pdev, 2, &did)) {
|
||||
dev_warn(&pdev->dev, "failed reading config word\n");
|
||||
break;
|
||||
}
|
||||
if (did == pdev->device) {
|
||||
dev_info(&pdev->dev, "device ID correctly read after %d iterations\n", i);
|
||||
break;
|
||||
}
|
||||
msleep(50);
|
||||
}
|
||||
if (i == niter)
|
||||
dev_warn(&pdev->dev, "%s-%d: could not read device ID\n", __func__, __LINE__);
|
||||
|
||||
for (i = 0; i < niter; i++) {
|
||||
count = ioread32be(health->health_counter);
|
||||
if (count && count != 0xffffffff) {
|
||||
dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i);
|
||||
break;
|
||||
}
|
||||
msleep(50);
|
||||
}
|
||||
|
||||
if (i == niter)
|
||||
dev_warn(&pdev->dev, "%s-%d: could not read device ID\n", __func__, __LINE__);
|
||||
}
|
||||
|
||||
static void mlx5_pci_resume(struct pci_dev *pdev)
|
||||
{
|
||||
struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
|
||||
struct mlx5_priv *priv = &dev->priv;
|
||||
int err;
|
||||
|
||||
dev_info(&pdev->dev, "%s was called\n", __func__);
|
||||
|
||||
pci_save_state(pdev);
|
||||
wait_vital(pdev);
|
||||
|
||||
err = mlx5_load_one(dev, priv);
|
||||
if (err)
|
||||
dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n"
|
||||
, __func__, err);
|
||||
else
|
||||
dev_info(&pdev->dev, "%s: device recovered\n", __func__);
|
||||
}
|
||||
|
||||
static const struct pci_error_handlers mlx5_err_handler = {
|
||||
.error_detected = mlx5_pci_err_detected,
|
||||
.slot_reset = mlx5_pci_slot_reset,
|
||||
.resume = mlx5_pci_resume
|
||||
};
|
||||
|
||||
static const struct pci_device_id mlx5_core_pci_table[] = {
|
||||
{ PCI_VDEVICE(MELLANOX, 0x1011) }, /* Connect-IB */
|
||||
{ PCI_VDEVICE(MELLANOX, 0x1012) }, /* Connect-IB VF */
|
||||
|
@ -1188,7 +1353,8 @@ static struct pci_driver mlx5_core_driver = {
|
|||
.name = DRIVER_NAME,
|
||||
.id_table = mlx5_core_pci_table,
|
||||
.probe = init_one,
|
||||
.remove = remove_one
|
||||
.remove = remove_one,
|
||||
.err_handler = &mlx5_err_handler
|
||||
};
|
||||
|
||||
static int __init init(void)
|
||||
|
|
|
@ -86,6 +86,10 @@ int mlx5_query_hca_caps(struct mlx5_core_dev *dev);
|
|||
int mlx5_query_board_id(struct mlx5_core_dev *dev);
|
||||
int mlx5_cmd_init_hca(struct mlx5_core_dev *dev);
|
||||
int mlx5_cmd_teardown_hca(struct mlx5_core_dev *dev);
|
||||
void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
|
||||
unsigned long param);
|
||||
void mlx5_enter_error_state(struct mlx5_core_dev *dev);
|
||||
void mlx5_disable_device(struct mlx5_core_dev *dev);
|
||||
|
||||
void mlx5e_init(void);
|
||||
void mlx5e_cleanup(void);
|
||||
|
|
|
@ -493,15 +493,20 @@ int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev)
|
|||
struct fw_page *fwp;
|
||||
struct rb_node *p;
|
||||
int nclaimed = 0;
|
||||
int err;
|
||||
int err = 0;
|
||||
|
||||
do {
|
||||
p = rb_first(&dev->priv.page_root);
|
||||
if (p) {
|
||||
fwp = rb_entry(p, struct fw_page, rb_node);
|
||||
if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
|
||||
free_4k(dev, fwp->addr);
|
||||
nclaimed = 1;
|
||||
} else {
|
||||
err = reclaim_pages(dev, fwp->func_id,
|
||||
optimal_reclaimed_pages(),
|
||||
&nclaimed);
|
||||
}
|
||||
if (err) {
|
||||
mlx5_core_warn(dev, "failed reclaiming pages (%d)\n",
|
||||
err);
|
||||
|
|
|
@ -487,8 +487,26 @@ struct mlx5_priv {
|
|||
spinlock_t ctx_lock;
|
||||
};
|
||||
|
||||
enum mlx5_device_state {
|
||||
MLX5_DEVICE_STATE_UP,
|
||||
MLX5_DEVICE_STATE_INTERNAL_ERROR,
|
||||
};
|
||||
|
||||
enum mlx5_interface_state {
|
||||
MLX5_INTERFACE_STATE_DOWN,
|
||||
MLX5_INTERFACE_STATE_UP,
|
||||
};
|
||||
|
||||
enum mlx5_pci_status {
|
||||
MLX5_PCI_STATUS_DISABLED,
|
||||
MLX5_PCI_STATUS_ENABLED,
|
||||
};
|
||||
|
||||
struct mlx5_core_dev {
|
||||
struct pci_dev *pdev;
|
||||
/* sync pci state */
|
||||
struct mutex pci_status_mutex;
|
||||
enum mlx5_pci_status pci_status;
|
||||
u8 rev_id;
|
||||
char board_id[MLX5_BOARD_ID_LEN];
|
||||
struct mlx5_cmd cmd;
|
||||
|
@ -497,6 +515,10 @@ struct mlx5_core_dev {
|
|||
u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
|
||||
phys_addr_t iseg_base;
|
||||
struct mlx5_init_seg __iomem *iseg;
|
||||
enum mlx5_device_state state;
|
||||
/* sync interface state */
|
||||
struct mutex intf_state_mutex;
|
||||
enum mlx5_interface_state interface_state;
|
||||
void (*event) (struct mlx5_core_dev *dev,
|
||||
enum mlx5_dev_event event,
|
||||
unsigned long param);
|
||||
|
|
Loading…
Reference in New Issue