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ARM: dts: exynos: Specify I2S assigned clocks in proper node 

The assigned parent clocks should be normally specified in the consumer
device's DT node, this ensures respective driver always sees correct clock
settings when required.

This patch fixes regression in audio subsystem on Odroid XU3/XU4 boards
that appeared after commits:

commit 647d04f8e0 ("ASoC: samsung: i2s: Ensure the RCLK rate is properly determined")
commit 995e73e55f ("ASoC: samsung: i2s: Fix rclk_srcrate handling")
commit 48279c53fd ("ASoC: samsung: i2s: Prevent external abort on exynos5433 I2S1 access")

Without this patch the driver gets wrong clock as the I2S function clock
(op_clk) in probe() and effectively the clock which is finally assigned
from DT is not being enabled/disabled in the runtime resume/suspend ops.

Without the above listed commits the EXYNOS_I2S_BUS clock was always set
as parent of CLK_I2S_RCLK_SRC regardless of DT settings so there was no issue
with not enabled EXYNOS_SCLK_I2S.

Cc: <stable@vger.kernel.org> # 4.17.x
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This commit is contained in:
Sylwester Nawrocki 2018-12-12 18:57:44 +01:00 committed by Krzysztof Kozlowski
parent 497f1bcb90
commit 8ac686d7df
2 changed files with 8 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi
View File

@ -26,8 +26,7 @@
"Speakers", "SPKL",
"Speakers", "SPKR";
assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>,
<&clock CLK_MOUT_EPLL>,
assigned-clocks = <&clock CLK_MOUT_EPLL>,
<&clock CLK_MOUT_MAU_EPLL>,
<&clock CLK_MOUT_USER_MAU_EPLL>,
<&clock_audss EXYNOS_MOUT_AUDSS>,
@ -36,8 +35,7 @@
<&clock_audss EXYNOS_DOUT_AUD_BUS>,
<&clock_audss EXYNOS_DOUT_I2S>;
assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>,
<&clock CLK_FOUT_EPLL>,
assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
<&clock CLK_MOUT_EPLL>,
<&clock CLK_MOUT_MAU_EPLL>,
<&clock CLK_MAU_EPLL>,
@ -48,7 +46,6 @@
<0>,
<0>,
<0>,
<0>,
<196608001>,
<(196608002 / 2)>,
<196608000>;
@ -84,4 +81,6 @@
&i2s0 {
status = "okay";
assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>;
assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>;
};

9
arch/arm/boot/dts/exynos5422-odroidxu4.dts
View File

@ -33,8 +33,7 @@
compatible = "samsung,odroid-xu3-audio";
model = "Odroid-XU4";
assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>,
<&clock CLK_MOUT_EPLL>,
assigned-clocks = <&clock CLK_MOUT_EPLL>,
<&clock CLK_MOUT_MAU_EPLL>,
<&clock CLK_MOUT_USER_MAU_EPLL>,
<&clock_audss EXYNOS_MOUT_AUDSS>,
@ -43,8 +42,7 @@
<&clock_audss EXYNOS_DOUT_AUD_BUS>,
<&clock_audss EXYNOS_DOUT_I2S>;
assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>,
<&clock CLK_FOUT_EPLL>,
assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
<&clock CLK_MOUT_EPLL>,
<&clock CLK_MOUT_MAU_EPLL>,
<&clock CLK_MAU_EPLL>,
@ -55,7 +53,6 @@
<0>,
<0>,
<0>,
<0>,
<196608001>,
<(196608002 / 2)>,
<196608000>;
@ -79,6 +76,8 @@
&i2s0 {
status = "okay";
assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>;
assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>;
};
&pwm {