mmc: msm_sdcc: Wrap readl/writel calls with appropriate clk delays
As it turns out, all sdcc register writes must be delayed by at
least 3 core clock cycles for the writes to take effect. *sigh*
Also removes the 30us constant delay on clock enable in favor
of a 3 core clock delay.
Signed-off-by: San Mehat <san@google.com>
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
This commit is contained in:
San Mehat
Daniel Walker
parent
865c8064a2
commit
8b1c2ba274
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@ -62,6 +62,7 @@ static inline int
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msmsdcc_enable_clocks(struct msmsdcc_host *host, int enable)
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{
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int rc;
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WARN_ON(enable == host->clks_on);
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if (enable) {
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rc = clk_enable(host->pclk);
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@ -72,7 +73,8 @@ msmsdcc_enable_clocks(struct msmsdcc_host *host, int enable)
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clk_disable(host->pclk);
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return rc;
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}
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udelay(30);
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udelay(1 + ((3 * USEC_PER_SEC) /
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(host->clk_rate ? host->clk_rate : msmsdcc_fmin)));
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host->clks_on = 1;
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} else {
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clk_disable(host->clk);
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@ -82,6 +84,20 @@ msmsdcc_enable_clocks(struct msmsdcc_host *host, int enable)
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return 0;
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}
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static inline unsigned int
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msmsdcc_readl(struct msmsdcc_host *host, unsigned int reg)
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{
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return readl(host->base + reg);
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}
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static inline void
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msmsdcc_writel(struct msmsdcc_host *host, u32 data, unsigned int reg)
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{
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writel(data, host->base + reg);
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/* 3 clk delay required! */
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udelay(1 + ((3 * USEC_PER_SEC) /
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(host->clk_rate ? host->clk_rate : msmsdcc_fmin)));
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}
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static void
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msmsdcc_start_command(struct msmsdcc_host *host, struct mmc_command *cmd,
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@ -90,7 +106,7 @@ msmsdcc_start_command(struct msmsdcc_host *host, struct mmc_command *cmd,
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static void
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msmsdcc_request_end(struct msmsdcc_host *host, struct mmc_request *mrq)
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{
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writel(0, host->base + MMCICOMMAND);
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msmsdcc_writel(host, 0, MMCICOMMAND);
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BUG_ON(host->curr.data);
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@ -116,7 +132,7 @@ msmsdcc_request_end(struct msmsdcc_host *host, struct mmc_request *mrq)
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static void
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msmsdcc_stop_data(struct msmsdcc_host *host)
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{
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writel(0, host->base + MMCIDATACTRL);
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msmsdcc_writel(host, 0, MMCIDATACTRL);
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host->curr.data = NULL;
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host->curr.got_dataend = host->curr.got_datablkend = 0;
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}
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@ -200,7 +216,7 @@ msmsdcc_dma_complete_func(struct msm_dmov_cmd *cmd,
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if (!mrq->data->error)
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host->curr.data_xfered = host->curr.xfer_size;
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if (!mrq->data->stop || mrq->cmd->error) {
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writel(0, host->base + MMCICOMMAND);
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msmsdcc_writel(host, 0, MMCICOMMAND);
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host->curr.mrq = NULL;
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host->curr.cmd = NULL;
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mrq->data->bytes_xfered = host->curr.data_xfered;
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@ -337,7 +353,6 @@ msmsdcc_start_data(struct msmsdcc_host *host, struct mmc_data *data)
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{
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unsigned int datactrl, timeout;
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unsigned long long clks;
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void __iomem *base = host->base;
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unsigned int pio_irqmask = 0;
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host->curr.data = data;
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@ -352,9 +367,9 @@ msmsdcc_start_data(struct msmsdcc_host *host, struct mmc_data *data)
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clks = (unsigned long long)data->timeout_ns * host->clk_rate;
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do_div(clks, NSEC_PER_SEC);
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timeout = data->timeout_clks + (unsigned int)clks;
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writel(timeout, base + MMCIDATATIMER);
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msmsdcc_writel(host, timeout, MMCIDATATIMER);
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writel(host->curr.xfer_size, base + MMCIDATALENGTH);
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msmsdcc_writel(host, host->curr.xfer_size, MMCIDATALENGTH);
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datactrl = MCI_DPSM_ENABLE | (data->blksz << 4);
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@ -376,8 +391,8 @@ msmsdcc_start_data(struct msmsdcc_host *host, struct mmc_data *data)
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if (data->flags & MMC_DATA_READ)
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datactrl |= MCI_DPSM_DIRECTION;
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writel(pio_irqmask, base + MMCIMASK1);
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writel(datactrl, base + MMCIDATACTRL);
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msmsdcc_writel(host, pio_irqmask, MMCIMASK1);
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msmsdcc_writel(host, datactrl, MMCIDATACTRL);
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if (datactrl & MCI_DPSM_DMAENABLE) {
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host->dma.busy = 1;
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@ -398,12 +413,8 @@ snoop_cccr_abort(struct mmc_command *cmd)
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static void
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msmsdcc_start_command(struct msmsdcc_host *host, struct mmc_command *cmd, u32 c)
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{
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void __iomem *base = host->base;
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if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
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writel(0, base + MMCICOMMAND);
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udelay(2 + ((5 * 1000000) / host->clk_rate));
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}
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if (msmsdcc_readl(host, MMCICOMMAND) & MCI_CPSM_ENABLE)
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msmsdcc_writel(host, 0, MMCICOMMAND);
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c |= cmd->opcode | MCI_CPSM_ENABLE;
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@ -428,8 +439,8 @@ msmsdcc_start_command(struct msmsdcc_host *host, struct mmc_command *cmd, u32 c)
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host->stats.cmds++;
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writel(cmd->arg, base + MMCIARGUMENT);
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writel(c, base + MMCICOMMAND);
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msmsdcc_writel(host, cmd->arg, MMCIARGUMENT);
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msmsdcc_writel(host, c, MMCICOMMAND);
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}
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static void
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@ -463,13 +474,11 @@ msmsdcc_data_err(struct msmsdcc_host *host, struct mmc_data *data,
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static int
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msmsdcc_pio_read(struct msmsdcc_host *host, char *buffer, unsigned int remain)
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{
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void __iomem *base = host->base;
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uint32_t *ptr = (uint32_t *) buffer;
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int count = 0;
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while (readl(base + MMCISTATUS) & MCI_RXDATAAVLBL) {
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*ptr = readl(base + MMCIFIFO + (count % MCI_FIFOSIZE));
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while (msmsdcc_readl(host, MMCISTATUS) & MCI_RXDATAAVLBL) {
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*ptr = msmsdcc_readl(host, MMCIFIFO + (count % MCI_FIFOSIZE));
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ptr++;
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count += sizeof(uint32_t);
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@ -501,7 +510,7 @@ msmsdcc_pio_write(struct msmsdcc_host *host, char *buffer,
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if (remain == 0)
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break;
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status = readl(base + MMCISTATUS);
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status = msmsdcc_readl(host, MMCISTATUS);
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} while (status & MCI_TXFIFOHALFEMPTY);
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return ptr - buffer;
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@ -511,7 +520,7 @@ static int
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msmsdcc_spin_on_status(struct msmsdcc_host *host, uint32_t mask, int maxspin)
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{
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while (maxspin) {
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if ((readl(host->base + MMCISTATUS) & mask))
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if ((msmsdcc_readl(host, MMCISTATUS) & mask))
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return 0;
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udelay(1);
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--maxspin;
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@ -523,10 +532,9 @@ static int
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msmsdcc_pio_irq(int irq, void *dev_id)
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{
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struct msmsdcc_host *host = dev_id;
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void __iomem *base = host->base;
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uint32_t status;
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status = readl(base + MMCISTATUS);
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status = msmsdcc_readl(host, MMCISTATUS);
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do {
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unsigned long flags;
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@ -581,14 +589,14 @@ msmsdcc_pio_irq(int irq, void *dev_id)
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host->pio.sg_off = 0;
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}
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status = readl(base + MMCISTATUS);
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status = msmsdcc_readl(host, MMCISTATUS);
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} while (1);
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if (status & MCI_RXACTIVE && host->curr.xfer_remain < MCI_FIFOSIZE)
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writel(MCI_RXDATAAVLBLMASK, base + MMCIMASK1);
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msmsdcc_writel(host, MCI_RXDATAAVLBLMASK, MMCIMASK1);
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if (!host->curr.xfer_remain)
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writel(0, base + MMCIMASK1);
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msmsdcc_writel(host, 0, MMCIMASK1);
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return IRQ_HANDLED;
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}
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@ -596,13 +604,12 @@ msmsdcc_pio_irq(int irq, void *dev_id)
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static void msmsdcc_do_cmdirq(struct msmsdcc_host *host, uint32_t status)
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{
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struct mmc_command *cmd = host->curr.cmd;
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void __iomem *base = host->base;
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host->curr.cmd = NULL;
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cmd->resp[0] = readl(base + MMCIRESPONSE0);
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cmd->resp[1] = readl(base + MMCIRESPONSE1);
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cmd->resp[2] = readl(base + MMCIRESPONSE2);
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cmd->resp[3] = readl(base + MMCIRESPONSE3);
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cmd->resp[0] = msmsdcc_readl(host, MMCIRESPONSE0);
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cmd->resp[1] = msmsdcc_readl(host, MMCIRESPONSE1);
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cmd->resp[2] = msmsdcc_readl(host, MMCIRESPONSE2);
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cmd->resp[3] = msmsdcc_readl(host, MMCIRESPONSE3);
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del_timer(&host->command_timer);
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if (status & MCI_CMDTIMEOUT) {
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@ -699,10 +706,11 @@ msmsdcc_irq(int irq, void *dev_id)
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spin_lock(&host->lock);
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do {
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status = readl(base + MMCISTATUS);
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status &= (readl(base + MMCIMASK0) | MCI_DATABLOCKENDMASK);
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writel(status, base + MMCICLEAR);
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struct mmc_data *data;
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status = msmsdcc_readl(host, MMCISTATUS);
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status &= (msmsdcc_readl(host, MMCIMASK0) |
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MCI_DATABLOCKENDMASK);
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msmsdcc_writel(host, status, MMCICLEAR);
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if (status & MCI_SDIOINTR)
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status &= ~MCI_SDIOINTR;
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@ -774,10 +782,11 @@ msmsdcc_request(struct mmc_host *mmc, struct mmc_request *mrq)
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if (host->cmdpoll && !msmsdcc_spin_on_status(host,
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MCI_CMDRESPEND|MCI_CMDCRCFAIL|MCI_CMDTIMEOUT,
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CMD_SPINMAX)) {
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uint32_t status = readl(host->base + MMCISTATUS);
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uint32_t status = msmsdcc_readl(host, MMCISTATUS);
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msmsdcc_do_cmdirq(host, status);
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writel(MCI_CMDRESPEND | MCI_CMDCRCFAIL | MCI_CMDTIMEOUT,
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host->base + MMCICLEAR);
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msmsdcc_writel(host,
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MCI_CMDRESPEND | MCI_CMDCRCFAIL | MCI_CMDTIMEOUT,
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MMCICLEAR);
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host->stats.cmdpoll_hits++;
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} else {
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host->stats.cmdpoll_misses++;
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@ -836,11 +845,11 @@ msmsdcc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
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if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
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pwr |= MCI_OD;
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writel(clk, host->base + MMCICLOCK);
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msmsdcc_writel(host, clk, MMCICLOCK);
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if (host->pwr != pwr) {
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host->pwr = pwr;
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writel(pwr, host->base + MMCIPOWER);
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msmsdcc_writel(host, pwr, MMCIPOWER);
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}
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if (host->clks_on)
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msmsdcc_enable_clocks(host, 0);
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@ -855,13 +864,13 @@ static void msmsdcc_enable_sdio_irq(struct mmc_host *mmc, int enable)
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spin_lock_irqsave(&host->lock, flags);
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if (msmsdcc_sdioirq == 1) {
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status = readl(host->base + MMCIMASK0);
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status = msmsdcc_readl(host, MMCIMASK0);
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if (enable)
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status |= MCI_SDIOINTOPERMASK;
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else
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status &= ~MCI_SDIOINTOPERMASK;
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host->saved_irq0mask = status;
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writel(status, host->base + MMCIMASK0);
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msmsdcc_writel(host, status, MMCIMASK0);
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}
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spin_unlock_irqrestore(&host->lock, flags);
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}
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@ -950,19 +959,16 @@ msmsdcc_command_expired(unsigned long _data)
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mrq = host->curr.mrq;
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if (!mrq) {
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pr_info("%s: Command expiry misfire\n",
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mmc_hostname(host->mmc));
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spin_unlock_irqrestore(&host->lock, flags);
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return;
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}
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pr_err("%s: Command timeout (%p %p %p %p)\n",
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mmc_hostname(host->mmc), mrq, mrq->cmd,
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mrq->data, host->dma.sg);
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pr_err("%s: Controller lockup detected\n",
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mmc_hostname(host->mmc));
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mrq->cmd->error = -ETIMEDOUT;
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msmsdcc_stop_data(host);
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writel(0, host->base + MMCICOMMAND);
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msmsdcc_writel(host, 0, MMCICOMMAND);
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host->curr.mrq = NULL;
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host->curr.cmd = NULL;
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@ -1143,10 +1149,10 @@ msmsdcc_probe(struct platform_device *pdev)
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mmc->max_req_size = 33554432; /* MCI_DATA_LENGTH is 25 bits */
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mmc->max_seg_size = mmc->max_req_size;
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writel(0, host->base + MMCIMASK0);
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writel(0x5e007ff, host->base + MMCICLEAR); /* Add: 1 << 25 */
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msmsdcc_writel(host, 0, MMCIMASK0);
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msmsdcc_writel(host, 0x5e007ff, MMCICLEAR);
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writel(MCI_IRQENABLE, host->base + MMCIMASK0);
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msmsdcc_writel(host, MCI_IRQENABLE, MMCIMASK0);
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host->saved_irq0mask = MCI_IRQENABLE;
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/*
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@ -1269,7 +1275,7 @@ msmsdcc_suspend(struct platform_device *dev, pm_message_t state)
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if (mmc->card && mmc->card->type != MMC_TYPE_SDIO)
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rc = mmc_suspend_host(mmc, state);
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if (!rc) {
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writel(0, host->base + MMCIMASK0);
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msmsdcc_writel(host, 0, MMCIMASK0);
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if (host->clks_on)
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msmsdcc_enable_clocks(host, 0);
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@ -1292,7 +1298,7 @@ msmsdcc_resume(struct platform_device *dev)
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if (!host->clks_on)
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msmsdcc_enable_clocks(host, 1);
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writel(host->saved_irq0mask, host->base + MMCIMASK0);
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msmsdcc_writel(host, host->saved_irq0mask, MMCIMASK0);
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spin_unlock_irqrestore(&host->lock, flags);
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