clk: h8300: Migrate to clk_hw based registration APIs
Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in these drivers, allowing us to move closer to a clear split of consumer and provider clk APIs. Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Cc: <uclinux-h8-devel@lists.sourceforge.jp> Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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@ -14,7 +14,7 @@ static DEFINE_SPINLOCK(clklock);
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static void __init h8300_div_clk_setup(struct device_node *node)
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static void __init h8300_div_clk_setup(struct device_node *node)
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{
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{
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unsigned int num_parents;
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unsigned int num_parents;
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struct clk *clk;
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struct clk_hw *hw;
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const char *clk_name = node->name;
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const char *clk_name = node->name;
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const char *parent_name;
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const char *parent_name;
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void __iomem *divcr = NULL;
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void __iomem *divcr = NULL;
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@ -38,15 +38,15 @@ static void __init h8300_div_clk_setup(struct device_node *node)
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parent_name = of_clk_get_parent_name(node, 0);
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parent_name = of_clk_get_parent_name(node, 0);
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of_property_read_u32(node, "renesas,width", &width);
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of_property_read_u32(node, "renesas,width", &width);
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clk = clk_register_divider(NULL, clk_name, parent_name,
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hw = clk_hw_register_divider(NULL, clk_name, parent_name,
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CLK_SET_RATE_GATE, divcr, offset, width,
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CLK_SET_RATE_GATE, divcr, offset, width,
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CLK_DIVIDER_POWER_OF_TWO, &clklock);
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CLK_DIVIDER_POWER_OF_TWO, &clklock);
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if (!IS_ERR(clk)) {
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if (!IS_ERR(hw)) {
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of_clk_add_provider(node, of_clk_src_simple_get, clk);
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of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw);
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return;
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return;
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}
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}
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pr_err("%s: failed to register %s div clock (%ld)\n",
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pr_err("%s: failed to register %s div clock (%ld)\n",
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__func__, clk_name, PTR_ERR(clk));
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__func__, clk_name, PTR_ERR(hw));
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error:
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error:
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if (divcr)
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if (divcr)
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iounmap(divcr);
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iounmap(divcr);
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@ -84,11 +84,11 @@ static const struct clk_ops pll_ops = {
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static void __init h8s2678_pll_clk_setup(struct device_node *node)
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static void __init h8s2678_pll_clk_setup(struct device_node *node)
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{
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{
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unsigned int num_parents;
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unsigned int num_parents;
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struct clk *clk;
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const char *clk_name = node->name;
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const char *clk_name = node->name;
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const char *parent_name;
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const char *parent_name;
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struct pll_clock *pll_clock;
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struct pll_clock *pll_clock;
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struct clk_init_data init;
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struct clk_init_data init;
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int ret;
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num_parents = of_clk_get_parent_count(node);
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num_parents = of_clk_get_parent_count(node);
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if (!num_parents) {
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if (!num_parents) {
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@ -121,14 +121,14 @@ static void __init h8s2678_pll_clk_setup(struct device_node *node)
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init.num_parents = 1;
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init.num_parents = 1;
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pll_clock->hw.init = &init;
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pll_clock->hw.init = &init;
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clk = clk_register(NULL, &pll_clock->hw);
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ret = clk_hw_register(NULL, &pll_clock->hw);
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if (IS_ERR(clk)) {
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if (ret) {
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pr_err("%s: failed to register %s div clock (%ld)\n",
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pr_err("%s: failed to register %s div clock (%d)\n",
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__func__, clk_name, PTR_ERR(clk));
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__func__, clk_name, ret);
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goto unmap_pllcr;
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goto unmap_pllcr;
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}
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}
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of_clk_add_provider(node, of_clk_src_simple_get, clk);
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of_clk_add_hw_provider(node, of_clk_hw_simple_get, &pll_clock->hw);
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return;
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return;
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unmap_pllcr:
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unmap_pllcr:
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