ARM: mxc: convert tzic to use generic irq chip
The patch converts mxc tzic interrupt controller to use generic irq chip. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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@ -376,6 +376,7 @@ config ARCH_MXC
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select ARCH_REQUIRE_GPIOLIB
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select ARCH_REQUIRE_GPIOLIB
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select CLKDEV_LOOKUP
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select CLKDEV_LOOKUP
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select CLKSRC_MMIO
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select CLKSRC_MMIO
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select GENERIC_IRQ_CHIP
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select HAVE_SCHED_CLOCK
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select HAVE_SCHED_CLOCK
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help
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help
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Support for Freescale MXC/iMX-based family of processors
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Support for Freescale MXC/iMX-based family of processors
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@ -42,17 +42,16 @@ EXPORT_SYMBOL(imx_irq_set_priority);
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int mxc_set_irq_fiq(unsigned int irq, unsigned int type)
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int mxc_set_irq_fiq(unsigned int irq, unsigned int type)
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{
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{
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struct mxc_irq_chip *chip;
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struct irq_chip_generic *gc;
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struct irq_chip *base;
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int (*set_irq_fiq)(unsigned int, unsigned int);
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int ret;
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int ret;
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ret = -ENOSYS;
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ret = -ENOSYS;
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base = irq_get_chip(irq);
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gc = irq_get_chip_data(irq);
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if (base) {
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if (gc && gc->private) {
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chip = container_of(base, struct mxc_irq_chip, base);
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set_irq_fiq = gc->private;
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if (chip->set_irq_fiq)
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ret = set_irq_fiq(irq, type);
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ret = chip->set_irq_fiq(irq, type);
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}
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}
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return ret;
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return ret;
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@ -68,78 +68,34 @@ static int tzic_set_irq_fiq(unsigned int irq, unsigned int type)
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return 0;
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return 0;
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}
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}
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#else
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#define tzic_set_irq_fiq NULL
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#endif
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#endif
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/**
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static unsigned int *wakeup_intr[4];
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* tzic_mask_irq() - Disable interrupt source "d" in the TZIC
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*
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static __init void tzic_init_gc(unsigned int irq_start)
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* @param d interrupt source
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*/
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static void tzic_mask_irq(struct irq_data *d)
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{
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{
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int index, off;
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struct irq_chip_generic *gc;
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struct irq_chip_type *ct;
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int idx = irq_start >> 5;
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index = d->irq >> 5;
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gc = irq_alloc_generic_chip("tzic", 1, irq_start, tzic_base,
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off = d->irq & 0x1F;
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handle_level_irq);
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__raw_writel(1 << off, tzic_base + TZIC_ENCLEAR0(index));
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gc->private = tzic_set_irq_fiq;
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gc->wake_enabled = IRQ_MSK(32);
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wakeup_intr[idx] = &gc->wake_active;
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ct = gc->chip_types;
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ct->chip.irq_mask = irq_gc_mask_disable_reg;
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ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
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ct->chip.irq_set_wake = irq_gc_set_wake;
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ct->regs.disable = TZIC_ENCLEAR0(idx);
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ct->regs.enable = TZIC_ENSET0(idx);
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irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
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}
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}
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/**
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* tzic_unmask_irq() - Enable interrupt source "d" in the TZIC
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*
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* @param d interrupt source
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*/
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static void tzic_unmask_irq(struct irq_data *d)
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{
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int index, off;
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index = d->irq >> 5;
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off = d->irq & 0x1F;
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__raw_writel(1 << off, tzic_base + TZIC_ENSET0(index));
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}
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static unsigned int wakeup_intr[4];
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/**
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* tzic_set_wake_irq() - Set interrupt source "d" in the TZIC as a wake-up source.
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*
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* @param d interrupt source
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* @param enable enable as wake-up if equal to non-zero
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* disble as wake-up if equal to zero
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*
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* @return This function returns 0 on success.
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*/
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static int tzic_set_wake_irq(struct irq_data *d, unsigned int enable)
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{
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unsigned int index, off;
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index = d->irq >> 5;
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off = d->irq & 0x1F;
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if (index > 3)
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return -EINVAL;
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if (enable)
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wakeup_intr[index] |= (1 << off);
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else
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wakeup_intr[index] &= ~(1 << off);
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return 0;
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}
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static struct mxc_irq_chip mxc_tzic_chip = {
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.base = {
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.name = "MXC_TZIC",
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.irq_ack = tzic_mask_irq,
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.irq_mask = tzic_mask_irq,
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.irq_unmask = tzic_unmask_irq,
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.irq_set_wake = tzic_set_wake_irq,
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},
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#ifdef CONFIG_FIQ
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.set_irq_fiq = tzic_set_irq_fiq,
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#endif
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};
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/*
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/*
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* This function initializes the TZIC hardware and disables all the
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* This function initializes the TZIC hardware and disables all the
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* interrupts. It registers the interrupt enable and disable functions
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* interrupts. It registers the interrupt enable and disable functions
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@ -168,11 +124,8 @@ void __init tzic_init_irq(void __iomem *irqbase)
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/* all IRQ no FIQ Warning :: No selection */
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/* all IRQ no FIQ Warning :: No selection */
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for (i = 0; i < TZIC_NUM_IRQS; i++) {
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for (i = 0; i < TZIC_NUM_IRQS; i += 32)
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irq_set_chip_and_handler(i, &mxc_tzic_chip.base,
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tzic_init_gc(i);
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handle_level_irq);
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set_irq_flags(i, IRQF_VALID);
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}
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#ifdef CONFIG_FIQ
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#ifdef CONFIG_FIQ
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/* Initialize FIQ */
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/* Initialize FIQ */
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@ -199,7 +152,7 @@ int tzic_enable_wake(int is_idle)
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for (i = 0; i < 4; i++) {
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for (i = 0; i < 4; i++) {
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v = is_idle ? __raw_readl(tzic_base + TZIC_ENSET0(i)) :
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v = is_idle ? __raw_readl(tzic_base + TZIC_ENSET0(i)) :
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wakeup_intr[i];
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*wakeup_intr[i];
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__raw_writel(v, tzic_base + TZIC_WAKEUP0(i));
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__raw_writel(v, tzic_base + TZIC_WAKEUP0(i));
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}
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}
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