bnx2x: MSI support
Enabling MSI on top of MSI-X and INTA. Also changing the module parameter to allow choosing INTA or MSI even when MSI-X is available. The default status block should not be reversed for endianity. Since MSI can issue re-configuration, the interrupt disable function now requires mmiowb Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
parent
555f6c7837
commit
8badd27aa0
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@ -740,6 +740,9 @@ struct bnx2x {
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atomic_t intr_sem;
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atomic_t intr_sem;
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struct msix_entry msix_table[MAX_CONTEXT+1];
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struct msix_entry msix_table[MAX_CONTEXT+1];
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#define INT_MODE_INTx 1
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#define INT_MODE_MSI 2
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#define INT_MODE_MSIX 3
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int tx_ring_size;
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int tx_ring_size;
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@ -794,7 +797,7 @@ struct bnx2x {
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#define NO_WOL_FLAG 8
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#define NO_WOL_FLAG 8
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#define USING_DAC_FLAG 0x10
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#define USING_DAC_FLAG 0x10
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#define USING_MSIX_FLAG 0x20
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#define USING_MSIX_FLAG 0x20
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#define ASF_ENABLE_FLAG 0x40
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#define USING_MSI_FLAG 0x40
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#define TPA_ENABLE_FLAG 0x80
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#define TPA_ENABLE_FLAG 0x80
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#define NO_MCP_FLAG 0x100
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#define NO_MCP_FLAG 0x100
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#define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG)
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#define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG)
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@ -1224,15 +1224,9 @@ struct host_func_stats {
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struct atten_def_status_block {
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struct atten_def_status_block {
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u32 attn_bits;
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u32 attn_bits;
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u32 attn_bits_ack;
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u32 attn_bits_ack;
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#if defined(__BIG_ENDIAN)
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u16 attn_bits_index;
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u8 reserved0;
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u8 status_block_id;
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#elif defined(__LITTLE_ENDIAN)
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u8 status_block_id;
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u8 status_block_id;
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u8 reserved0;
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u8 reserved0;
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u16 attn_bits_index;
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u16 attn_bits_index;
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#endif
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u32 reserved1;
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u32 reserved1;
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};
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};
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@ -77,17 +77,19 @@ static int multi_mode = 1;
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module_param(multi_mode, int, 0);
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module_param(multi_mode, int, 0);
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static int disable_tpa;
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static int disable_tpa;
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static int use_inta;
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static int poll;
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static int poll;
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static int debug;
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static int debug;
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static int load_count[3]; /* 0-common, 1-port0, 2-port1 */
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static int load_count[3]; /* 0-common, 1-port0, 2-port1 */
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module_param(disable_tpa, int, 0);
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module_param(disable_tpa, int, 0);
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module_param(use_inta, int, 0);
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static int int_mode;
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module_param(int_mode, int, 0);
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MODULE_PARM_DESC(int_mode, " Force interrupt mode (1 INT#x; 2 MSI)");
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module_param(poll, int, 0);
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module_param(poll, int, 0);
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module_param(debug, int, 0);
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module_param(debug, int, 0);
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MODULE_PARM_DESC(disable_tpa, "disable the TPA (LRO) feature");
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MODULE_PARM_DESC(disable_tpa, "disable the TPA (LRO) feature");
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MODULE_PARM_DESC(use_inta, "use INT#A instead of MSI-X");
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MODULE_PARM_DESC(poll, "use polling (for debug)");
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MODULE_PARM_DESC(poll, "use polling (for debug)");
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MODULE_PARM_DESC(debug, "default debug msglevel");
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MODULE_PARM_DESC(debug, "default debug msglevel");
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@ -588,34 +590,41 @@ static void bnx2x_int_enable(struct bnx2x *bp)
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u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
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u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
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u32 val = REG_RD(bp, addr);
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u32 val = REG_RD(bp, addr);
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int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
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int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
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int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
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if (msix) {
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if (msix) {
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val &= ~HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
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val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
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HC_CONFIG_0_REG_INT_LINE_EN_0);
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val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
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val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
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HC_CONFIG_0_REG_ATTN_BIT_EN_0);
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HC_CONFIG_0_REG_ATTN_BIT_EN_0);
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} else if (msi) {
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val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
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val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
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HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
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HC_CONFIG_0_REG_ATTN_BIT_EN_0);
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} else {
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} else {
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val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
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val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
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HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
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HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
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HC_CONFIG_0_REG_INT_LINE_EN_0 |
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HC_CONFIG_0_REG_INT_LINE_EN_0 |
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HC_CONFIG_0_REG_ATTN_BIT_EN_0);
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HC_CONFIG_0_REG_ATTN_BIT_EN_0);
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DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) MSI-X %d\n",
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DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
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val, port, addr, msix);
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val, port, addr);
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REG_WR(bp, addr, val);
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REG_WR(bp, addr, val);
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val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
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val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
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}
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}
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DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) MSI-X %d\n",
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DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n",
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val, port, addr, msix);
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val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
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REG_WR(bp, addr, val);
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REG_WR(bp, addr, val);
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if (CHIP_IS_E1H(bp)) {
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if (CHIP_IS_E1H(bp)) {
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/* init leading/trailing edge */
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/* init leading/trailing edge */
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if (IS_E1HMF(bp)) {
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if (IS_E1HMF(bp)) {
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val = (0xfe0f | (1 << (BP_E1HVN(bp) + 4)));
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val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
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if (bp->port.pmf)
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if (bp->port.pmf)
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/* enable nig attention */
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/* enable nig attention */
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val |= 0x0100;
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val |= 0x0100;
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@ -641,6 +650,9 @@ static void bnx2x_int_disable(struct bnx2x *bp)
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DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
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DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
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val, port, addr);
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val, port, addr);
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/* flush all outstanding writes */
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mmiowb();
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REG_WR(bp, addr, val);
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REG_WR(bp, addr, val);
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if (REG_RD(bp, addr) != val)
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if (REG_RD(bp, addr) != val)
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BNX2X_ERR("BUG! proper val not read from IGU!\n");
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BNX2X_ERR("BUG! proper val not read from IGU!\n");
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@ -649,7 +661,7 @@ static void bnx2x_int_disable(struct bnx2x *bp)
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static void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
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static void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
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{
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{
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int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
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int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
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int i;
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int i, offset;
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/* disable interrupt handling */
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/* disable interrupt handling */
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atomic_inc(&bp->intr_sem);
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atomic_inc(&bp->intr_sem);
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@ -659,11 +671,10 @@ static void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
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/* make sure all ISRs are done */
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/* make sure all ISRs are done */
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if (msix) {
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if (msix) {
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synchronize_irq(bp->msix_table[0].vector);
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offset = 1;
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for_each_queue(bp, i)
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for_each_queue(bp, i)
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synchronize_irq(bp->msix_table[i].vector);
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synchronize_irq(bp->msix_table[i + offset].vector);
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/* one more for the Slow Path IRQ */
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synchronize_irq(bp->msix_table[i].vector);
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} else
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} else
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synchronize_irq(bp->pdev->irq);
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synchronize_irq(bp->pdev->irq);
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@ -5198,6 +5209,8 @@ static int bnx2x_init_common(struct bnx2x *bp)
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REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
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REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
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REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
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REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
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REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
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REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
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/* make sure this value is 0 */
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REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
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/* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
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/* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
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REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
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REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
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@ -5648,10 +5661,17 @@ static int bnx2x_init_func(struct bnx2x *bp)
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{
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{
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int port = BP_PORT(bp);
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int port = BP_PORT(bp);
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int func = BP_FUNC(bp);
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int func = BP_FUNC(bp);
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u32 addr, val;
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int i;
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int i;
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DP(BNX2X_MSG_MCP, "starting func init func %x\n", func);
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DP(BNX2X_MSG_MCP, "starting func init func %x\n", func);
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/* set MSI reconfigure capability */
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addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
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val = REG_RD(bp, addr);
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val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
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REG_WR(bp, addr, val);
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i = FUNC_ILT_BASE(func);
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i = FUNC_ILT_BASE(func);
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bnx2x_ilt_wr(bp, i, bnx2x_sp_mapping(bp, context));
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bnx2x_ilt_wr(bp, i, bnx2x_sp_mapping(bp, context));
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@ -6053,10 +6073,6 @@ static void bnx2x_free_msix_irqs(struct bnx2x *bp)
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"state %x\n", i, bp->msix_table[i + offset].vector,
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"state %x\n", i, bp->msix_table[i + offset].vector,
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bnx2x_fp(bp, i, state));
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bnx2x_fp(bp, i, state));
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if (bnx2x_fp(bp, i, state) != BNX2X_FP_STATE_CLOSED)
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BNX2X_ERR("IRQ of fp #%d being freed while "
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"state != closed\n", i);
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free_irq(bp->msix_table[i + offset].vector, &bp->fp[i]);
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free_irq(bp->msix_table[i + offset].vector, &bp->fp[i]);
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}
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}
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}
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}
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@ -6068,21 +6084,25 @@ static void bnx2x_free_irq(struct bnx2x *bp)
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pci_disable_msix(bp->pdev);
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pci_disable_msix(bp->pdev);
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bp->flags &= ~USING_MSIX_FLAG;
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bp->flags &= ~USING_MSIX_FLAG;
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} else if (bp->flags & USING_MSI_FLAG) {
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free_irq(bp->pdev->irq, bp->dev);
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pci_disable_msi(bp->pdev);
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bp->flags &= ~USING_MSI_FLAG;
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} else
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} else
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free_irq(bp->pdev->irq, bp->dev);
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free_irq(bp->pdev->irq, bp->dev);
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}
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}
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static int bnx2x_enable_msix(struct bnx2x *bp)
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static int bnx2x_enable_msix(struct bnx2x *bp)
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{
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{
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int i, rc, offset;
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int i, rc, offset = 1;
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int igu_vec = 0;
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bp->msix_table[0].entry = 0;
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bp->msix_table[0].entry = igu_vec;
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offset = 1;
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DP(NETIF_MSG_IFUP, "msix_table[0].entry = %d (slowpath)\n", igu_vec);
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DP(NETIF_MSG_IFUP, "msix_table[0].entry = 0 (slowpath)\n");
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for_each_queue(bp, i) {
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for_each_queue(bp, i) {
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int igu_vec = offset + i + BP_L_ID(bp);
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igu_vec = BP_L_ID(bp) + offset + i;
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bp->msix_table[i + offset].entry = igu_vec;
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bp->msix_table[i + offset].entry = igu_vec;
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DP(NETIF_MSG_IFUP, "msix_table[%d].entry = %d "
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DP(NETIF_MSG_IFUP, "msix_table[%d].entry = %d "
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"(fastpath #%u)\n", i + offset, igu_vec, i);
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"(fastpath #%u)\n", i + offset, igu_vec, i);
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@ -6091,9 +6111,10 @@ static int bnx2x_enable_msix(struct bnx2x *bp)
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rc = pci_enable_msix(bp->pdev, &bp->msix_table[0],
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rc = pci_enable_msix(bp->pdev, &bp->msix_table[0],
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BNX2X_NUM_QUEUES(bp) + offset);
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BNX2X_NUM_QUEUES(bp) + offset);
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if (rc) {
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if (rc) {
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DP(NETIF_MSG_IFUP, "MSI-X is not attainable\n");
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DP(NETIF_MSG_IFUP, "MSI-X is not attainable rc %d\n", rc);
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return -1;
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return rc;
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}
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}
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bp->flags |= USING_MSIX_FLAG;
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bp->flags |= USING_MSIX_FLAG;
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return 0;
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return 0;
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@ -6140,11 +6161,31 @@ static int bnx2x_req_msix_irqs(struct bnx2x *bp)
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return 0;
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return 0;
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}
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}
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static int bnx2x_req_irq(struct bnx2x *bp)
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static int bnx2x_enable_msi(struct bnx2x *bp)
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{
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{
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int rc;
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int rc;
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rc = request_irq(bp->pdev->irq, bnx2x_interrupt, IRQF_SHARED,
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rc = pci_enable_msi(bp->pdev);
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if (rc) {
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DP(NETIF_MSG_IFUP, "MSI is not attainable\n");
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return -1;
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}
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bp->flags |= USING_MSI_FLAG;
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return 0;
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}
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static int bnx2x_req_irq(struct bnx2x *bp)
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{
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unsigned long flags;
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int rc;
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if (bp->flags & USING_MSI_FLAG)
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flags = 0;
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else
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flags = IRQF_SHARED;
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rc = request_irq(bp->pdev->irq, bnx2x_interrupt, flags,
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bp->dev->name, bp->dev);
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bp->dev->name, bp->dev);
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if (!rc)
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if (!rc)
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bnx2x_fp(bp, 0, state) = BNX2X_FP_STATE_IRQ;
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bnx2x_fp(bp, 0, state) = BNX2X_FP_STATE_IRQ;
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@ -6365,28 +6406,23 @@ static int bnx2x_setup_multi(struct bnx2x *bp, int index)
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}
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}
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static int bnx2x_poll(struct napi_struct *napi, int budget);
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static int bnx2x_poll(struct napi_struct *napi, int budget);
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static void bnx2x_set_rx_mode(struct net_device *dev);
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/* must be called with rtnl_lock */
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static void bnx2x_set_int_mode(struct bnx2x *bp)
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static int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
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{
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{
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u32 load_code;
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int i, rc = 0;
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int num_queues;
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int num_queues;
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#ifdef BNX2X_STOP_ON_ERROR
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if (unlikely(bp->panic))
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return -EPERM;
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#endif
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bp->state = BNX2X_STATE_OPENING_WAIT4_LOAD;
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switch (int_mode) {
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case INT_MODE_INTx:
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if (use_inta) {
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case INT_MODE_MSI:
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num_queues = 1;
|
num_queues = 1;
|
||||||
bp->num_rx_queues = num_queues;
|
bp->num_rx_queues = num_queues;
|
||||||
bp->num_tx_queues = num_queues;
|
bp->num_tx_queues = num_queues;
|
||||||
DP(NETIF_MSG_IFUP,
|
DP(NETIF_MSG_IFUP,
|
||||||
"set number of queues to %d\n", num_queues);
|
"set number of queues to %d\n", num_queues);
|
||||||
} else {
|
break;
|
||||||
|
|
||||||
|
case INT_MODE_MSIX:
|
||||||
|
default:
|
||||||
if (bp->multi_mode == ETH_RSS_MODE_REGULAR)
|
if (bp->multi_mode == ETH_RSS_MODE_REGULAR)
|
||||||
num_queues = min_t(u32, num_online_cpus(),
|
num_queues = min_t(u32, num_online_cpus(),
|
||||||
BNX2X_MAX_QUEUES(bp));
|
BNX2X_MAX_QUEUES(bp));
|
||||||
|
@ -6401,8 +6437,7 @@ static int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
|
||||||
* so try to enable MSI-X with the requested number of fp's
|
* so try to enable MSI-X with the requested number of fp's
|
||||||
* and fallback to MSI or legacy INTx with one fp
|
* and fallback to MSI or legacy INTx with one fp
|
||||||
*/
|
*/
|
||||||
rc = bnx2x_enable_msix(bp);
|
if (bnx2x_enable_msix(bp)) {
|
||||||
if (rc) {
|
|
||||||
/* failed to enable MSI-X */
|
/* failed to enable MSI-X */
|
||||||
num_queues = 1;
|
num_queues = 1;
|
||||||
bp->num_rx_queues = num_queues;
|
bp->num_rx_queues = num_queues;
|
||||||
|
@ -6412,8 +6447,27 @@ static int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
|
||||||
"enable MSI-X set number of "
|
"enable MSI-X set number of "
|
||||||
"queues to %d\n", num_queues);
|
"queues to %d\n", num_queues);
|
||||||
}
|
}
|
||||||
|
break;
|
||||||
}
|
}
|
||||||
bp->dev->real_num_tx_queues = bp->num_tx_queues;
|
bp->dev->real_num_tx_queues = bp->num_tx_queues;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void bnx2x_set_rx_mode(struct net_device *dev);
|
||||||
|
|
||||||
|
/* must be called with rtnl_lock */
|
||||||
|
static int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
|
||||||
|
{
|
||||||
|
u32 load_code;
|
||||||
|
int i, rc = 0;
|
||||||
|
#ifdef BNX2X_STOP_ON_ERROR
|
||||||
|
DP(NETIF_MSG_IFUP, "enter load_mode %d\n", load_mode);
|
||||||
|
if (unlikely(bp->panic))
|
||||||
|
return -EPERM;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
bp->state = BNX2X_STATE_OPENING_WAIT4_LOAD;
|
||||||
|
|
||||||
|
bnx2x_set_int_mode(bp);
|
||||||
|
|
||||||
if (bnx2x_alloc_mem(bp))
|
if (bnx2x_alloc_mem(bp))
|
||||||
return -ENOMEM;
|
return -ENOMEM;
|
||||||
|
@ -6445,14 +6499,22 @@ static int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
|
||||||
pci_disable_msix(bp->pdev);
|
pci_disable_msix(bp->pdev);
|
||||||
goto load_error1;
|
goto load_error1;
|
||||||
}
|
}
|
||||||
printk(KERN_INFO PFX "%s: using MSI-X\n", bp->dev->name);
|
|
||||||
} else {
|
} else {
|
||||||
|
if ((rc != -ENOMEM) && (int_mode != INT_MODE_INTx))
|
||||||
|
bnx2x_enable_msi(bp);
|
||||||
bnx2x_ack_int(bp);
|
bnx2x_ack_int(bp);
|
||||||
rc = bnx2x_req_irq(bp);
|
rc = bnx2x_req_irq(bp);
|
||||||
if (rc) {
|
if (rc) {
|
||||||
BNX2X_ERR("IRQ request failed rc %d, aborting\n", rc);
|
BNX2X_ERR("IRQ request failed rc %d, aborting\n", rc);
|
||||||
|
if (bp->flags & USING_MSI_FLAG)
|
||||||
|
pci_disable_msi(bp->pdev);
|
||||||
goto load_error1;
|
goto load_error1;
|
||||||
}
|
}
|
||||||
|
if (bp->flags & USING_MSI_FLAG) {
|
||||||
|
bp->dev->irq = bp->pdev->irq;
|
||||||
|
printk(KERN_INFO PFX "%s: using MSI IRQ %d\n",
|
||||||
|
bp->dev->name, bp->pdev->irq);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Send LOAD_REQUEST command to MCP
|
/* Send LOAD_REQUEST command to MCP
|
||||||
|
@ -6689,8 +6751,6 @@ static void bnx2x_reset_func(struct bnx2x *bp)
|
||||||
REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
|
REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
|
||||||
REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
|
REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
|
||||||
|
|
||||||
REG_WR(bp, HC_REG_CONFIG_0 + port*4, 0x1000);
|
|
||||||
|
|
||||||
/* Clear ILT */
|
/* Clear ILT */
|
||||||
base = FUNC_ILT_BASE(func);
|
base = FUNC_ILT_BASE(func);
|
||||||
for (i = base; i < base + ILT_PER_FUNC; i++)
|
for (i = base; i < base + ILT_PER_FUNC; i++)
|
||||||
|
@ -7636,9 +7696,10 @@ static int __devinit bnx2x_init_bp(struct bnx2x *bp)
|
||||||
"MCP disabled, must load devices in order!\n");
|
"MCP disabled, must load devices in order!\n");
|
||||||
|
|
||||||
/* Set multi queue mode */
|
/* Set multi queue mode */
|
||||||
if ((multi_mode != ETH_RSS_MODE_DISABLED) && (!use_inta)) {
|
if ((multi_mode != ETH_RSS_MODE_DISABLED) &&
|
||||||
|
((int_mode == INT_MODE_INTx) || (int_mode == INT_MODE_MSI))) {
|
||||||
printk(KERN_ERR PFX
|
printk(KERN_ERR PFX
|
||||||
"Multi disabled since INTA is requested\n");
|
"Multi disabled since int_mode requested is not MSI-X\n");
|
||||||
multi_mode = ETH_RSS_MODE_DISABLED;
|
multi_mode = ETH_RSS_MODE_DISABLED;
|
||||||
}
|
}
|
||||||
bp->multi_mode = multi_mode;
|
bp->multi_mode = multi_mode;
|
||||||
|
|
|
@ -745,6 +745,7 @@
|
||||||
#define DORQ_REG_SHRT_CMHEAD 0x170054
|
#define DORQ_REG_SHRT_CMHEAD 0x170054
|
||||||
#define HC_CONFIG_0_REG_ATTN_BIT_EN_0 (0x1<<4)
|
#define HC_CONFIG_0_REG_ATTN_BIT_EN_0 (0x1<<4)
|
||||||
#define HC_CONFIG_0_REG_INT_LINE_EN_0 (0x1<<3)
|
#define HC_CONFIG_0_REG_INT_LINE_EN_0 (0x1<<3)
|
||||||
|
#define HC_CONFIG_0_REG_MSI_ATTN_EN_0 (0x1<<7)
|
||||||
#define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 (0x1<<2)
|
#define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 (0x1<<2)
|
||||||
#define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 (0x1<<1)
|
#define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 (0x1<<1)
|
||||||
#define HC_REG_AGG_INT_0 0x108050
|
#define HC_REG_AGG_INT_0 0x108050
|
||||||
|
@ -5359,9 +5360,28 @@
|
||||||
#define PCICFG_PM_CSR_STATE (0x3<<0)
|
#define PCICFG_PM_CSR_STATE (0x3<<0)
|
||||||
#define PCICFG_PM_CSR_PME_ENABLE (1<<8)
|
#define PCICFG_PM_CSR_PME_ENABLE (1<<8)
|
||||||
#define PCICFG_PM_CSR_PME_STATUS (1<<15)
|
#define PCICFG_PM_CSR_PME_STATUS (1<<15)
|
||||||
|
#define PCICFG_MSI_CAP_ID 0x58
|
||||||
|
#define PCICFG_MSI_CONTROL_ENABLE (0x1<<16)
|
||||||
|
#define PCICFG_MSI_CONTROL_MCAP (0x7<<17)
|
||||||
|
#define PCICFG_MSI_CONTROL_MENA (0x7<<20)
|
||||||
|
#define PCICFG_MSI_CONTROL_64_BIT_ADDR_CAP (0x1<<23)
|
||||||
|
#define PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE (0x1<<24)
|
||||||
#define PCICFG_GRC_ADDRESS 0x78
|
#define PCICFG_GRC_ADDRESS 0x78
|
||||||
#define PCICFG_GRC_DATA 0x80
|
#define PCICFG_GRC_DATA 0x80
|
||||||
|
#define PCICFG_MSIX_CAP_ID 0xa0
|
||||||
|
#define PCICFG_MSIX_CONTROL_TABLE_SIZE (0x7ff<<16)
|
||||||
|
#define PCICFG_MSIX_CONTROL_RESERVED (0x7<<27)
|
||||||
|
#define PCICFG_MSIX_CONTROL_FUNC_MASK (0x1<<30)
|
||||||
|
#define PCICFG_MSIX_CONTROL_MSIX_ENABLE (0x1<<31)
|
||||||
|
|
||||||
#define PCICFG_DEVICE_CONTROL 0xb4
|
#define PCICFG_DEVICE_CONTROL 0xb4
|
||||||
|
#define PCICFG_DEVICE_STATUS 0xb6
|
||||||
|
#define PCICFG_DEVICE_STATUS_CORR_ERR_DET (1<<0)
|
||||||
|
#define PCICFG_DEVICE_STATUS_NON_FATAL_ERR_DET (1<<1)
|
||||||
|
#define PCICFG_DEVICE_STATUS_FATAL_ERR_DET (1<<2)
|
||||||
|
#define PCICFG_DEVICE_STATUS_UNSUP_REQ_DET (1<<3)
|
||||||
|
#define PCICFG_DEVICE_STATUS_AUX_PWR_DET (1<<4)
|
||||||
|
#define PCICFG_DEVICE_STATUS_NO_PEND (1<<5)
|
||||||
#define PCICFG_LINK_CONTROL 0xbc
|
#define PCICFG_LINK_CONTROL 0xbc
|
||||||
|
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue