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ARM: kirkwood: Move to ID based MBus window creation 

With the introduction of the ID based MBus API, it's better
to switch to use it instead of the current name based scheme.

This will allow to deprecate the name based API, once every
user is removed.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit is contained in:
Thomas Petazzoni 2013-07-26 10:17:40 -03:00 committed by Jason Cooper
parent 6a63b098f0
commit 8baeeeb2f1
2 changed files with 38 additions and 20 deletions
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18
arch/arm/mach-kirkwood/common.c
View File

@ -37,6 +37,12 @@
#include <linux/platform_data/dma-mv_xor.h>
#include "common.h"
/* These can go away once Kirkwood uses the mvebu-mbus DT binding */
#define KIRKWOOD_MBUS_NAND_TARGET 0x01
#define KIRKWOOD_MBUS_NAND_ATTR 0x2f
#define KIRKWOOD_MBUS_SRAM_TARGET 0x03
#define KIRKWOOD_MBUS_SRAM_ATTR 0x01
/*****************************************************************************
* I/O Address Mapping
****************************************************************************/
@ -672,10 +678,14 @@ char * __init kirkwood_id(void)
void __init kirkwood_setup_wins(void)
{
mvebu_mbus_add_window("nand", KIRKWOOD_NAND_MEM_PHYS_BASE,
KIRKWOOD_NAND_MEM_SIZE);
mvebu_mbus_add_window("sram", KIRKWOOD_SRAM_PHYS_BASE,
KIRKWOOD_SRAM_SIZE);
mvebu_mbus_add_window_by_id(KIRKWOOD_MBUS_NAND_TARGET,
KIRKWOOD_MBUS_NAND_ATTR,
KIRKWOOD_NAND_MEM_PHYS_BASE,
KIRKWOOD_NAND_MEM_SIZE);
mvebu_mbus_add_window_by_id(KIRKWOOD_MBUS_SRAM_TARGET,
KIRKWOOD_MBUS_SRAM_ATTR,
KIRKWOOD_SRAM_PHYS_BASE,
KIRKWOOD_SRAM_SIZE);
}
void __init kirkwood_l2_init(void)

40
arch/arm/mach-kirkwood/pcie.c
View File

@ -20,6 +20,16 @@
#include <mach/bridge-regs.h>
#include "common.h"
/* These can go away once Kirkwood uses the mvebu-mbus DT binding */
#define KIRKWOOD_MBUS_PCIE0_MEM_TARGET 0x4
#define KIRKWOOD_MBUS_PCIE0_MEM_ATTR 0xe8
#define KIRKWOOD_MBUS_PCIE0_IO_TARGET 0x4
#define KIRKWOOD_MBUS_PCIE0_IO_ATTR 0xe0
#define KIRKWOOD_MBUS_PCIE1_MEM_TARGET 0x4
#define KIRKWOOD_MBUS_PCIE1_MEM_ATTR 0xd8
#define KIRKWOOD_MBUS_PCIE1_IO_TARGET 0x4
#define KIRKWOOD_MBUS_PCIE1_IO_ATTR 0xd0
static void kirkwood_enable_pcie_clk(const char *port)
{
struct clk *clk;
@ -254,26 +264,24 @@ static void __init add_pcie_port(int index, void __iomem *base)
void __init kirkwood_pcie_init(unsigned int portmask)
{
mvebu_mbus_add_window_remap_flags("pcie0.0",
mvebu_mbus_add_window_remap_by_id(KIRKWOOD_MBUS_PCIE0_IO_TARGET,
KIRKWOOD_MBUS_PCIE0_IO_ATTR,
KIRKWOOD_PCIE_IO_PHYS_BASE,
KIRKWOOD_PCIE_IO_SIZE,
KIRKWOOD_PCIE_IO_BUS_BASE,
MVEBU_MBUS_PCI_IO);
mvebu_mbus_add_window_remap_flags("pcie0.0",
KIRKWOOD_PCIE_MEM_PHYS_BASE,
KIRKWOOD_PCIE_MEM_SIZE,
MVEBU_MBUS_NO_REMAP,
MVEBU_MBUS_PCI_MEM);
mvebu_mbus_add_window_remap_flags("pcie1.0",
KIRKWOOD_PCIE_IO_BUS_BASE);
mvebu_mbus_add_window_by_id(KIRKWOOD_MBUS_PCIE0_MEM_TARGET,
KIRKWOOD_MBUS_PCIE0_MEM_ATTR,
KIRKWOOD_PCIE_MEM_PHYS_BASE,
KIRKWOOD_PCIE_MEM_SIZE);
mvebu_mbus_add_window_remap_by_id(KIRKWOOD_MBUS_PCIE1_IO_TARGET,
KIRKWOOD_MBUS_PCIE1_IO_ATTR,
KIRKWOOD_PCIE1_IO_PHYS_BASE,
KIRKWOOD_PCIE1_IO_SIZE,
KIRKWOOD_PCIE1_IO_BUS_BASE,
MVEBU_MBUS_PCI_IO);
mvebu_mbus_add_window_remap_flags("pcie1.0",
KIRKWOOD_PCIE1_MEM_PHYS_BASE,
KIRKWOOD_PCIE1_MEM_SIZE,
MVEBU_MBUS_NO_REMAP,
MVEBU_MBUS_PCI_MEM);
KIRKWOOD_PCIE1_IO_BUS_BASE);
mvebu_mbus_add_window_by_id(KIRKWOOD_MBUS_PCIE1_MEM_TARGET,
KIRKWOOD_MBUS_PCIE1_MEM_ATTR,
KIRKWOOD_PCIE1_MEM_PHYS_BASE,
KIRKWOOD_PCIE1_MEM_SIZE);
vga_base = KIRKWOOD_PCIE_MEM_PHYS_BASE;