s390: rename psw_bits enums
The address space enums that must be used when modifying the address space part of a psw with the psw_bits() macro can easily be confused with the psw defines that are used to mask and compare directly the mask part of a psw. We have e.g. PSW_AS_PRIMARY vs PSW_ASC_PRIMARY. To avoid confusion rename the PSW_AS_* enums to PSW_BITS_AS_*. In addition also rename the PSW_AMODE_* enums, so they also follow the same naming scheme: PSW_BITS_AMODE_*. Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
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@ -46,16 +46,16 @@ struct psw_bits {
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};
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enum {
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PSW_AMODE_24BIT = 0,
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PSW_AMODE_31BIT = 1,
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PSW_AMODE_64BIT = 3
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PSW_BITS_AMODE_24BIT = 0,
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PSW_BITS_AMODE_31BIT = 1,
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PSW_BITS_AMODE_64BIT = 3
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};
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enum {
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PSW_AS_PRIMARY = 0,
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PSW_AS_ACCREG = 1,
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PSW_AS_SECONDARY = 2,
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PSW_AS_HOME = 3
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PSW_BITS_AS_PRIMARY = 0,
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PSW_BITS_AS_ACCREG = 1,
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PSW_BITS_AS_SECONDARY = 2,
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PSW_BITS_AS_HOME = 3
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};
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#define psw_bits(__psw) (*({ \
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@ -27,9 +27,9 @@ int arch_uprobe_analyze_insn(struct arch_uprobe *auprobe, struct mm_struct *mm,
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int arch_uprobe_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
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{
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if (psw_bits(regs->psw).eaba == PSW_AMODE_24BIT)
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if (psw_bits(regs->psw).eaba == PSW_BITS_AMODE_24BIT)
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return -EINVAL;
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if (!is_compat_task() && psw_bits(regs->psw).eaba == PSW_AMODE_31BIT)
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if (!is_compat_task() && psw_bits(regs->psw).eaba == PSW_BITS_AMODE_31BIT)
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return -EINVAL;
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clear_pt_regs_flag(regs, PIF_PER_TRAP);
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auprobe->saved_per = psw_bits(regs->psw).r;
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@ -372,8 +372,8 @@ static void handle_insn_ril(struct arch_uprobe *auprobe, struct pt_regs *regs)
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bool arch_uprobe_skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs)
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{
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if ((psw_bits(regs->psw).eaba == PSW_AMODE_24BIT) ||
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((psw_bits(regs->psw).eaba == PSW_AMODE_31BIT) &&
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if ((psw_bits(regs->psw).eaba == PSW_BITS_AMODE_24BIT) ||
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((psw_bits(regs->psw).eaba == PSW_BITS_AMODE_31BIT) &&
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!is_compat_task())) {
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regs->psw.addr = __rewind_psw(regs->psw, UPROBE_SWBP_INSN_SIZE);
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do_report_trap(regs, SIGILL, ILL_ILLADR, NULL);
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@ -557,20 +557,20 @@ static int get_vcpu_asce(struct kvm_vcpu *vcpu, union asce *asce,
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return 0;
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}
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if (mode == GACC_IFETCH)
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psw.as = psw.as == PSW_AS_HOME ? PSW_AS_HOME : PSW_AS_PRIMARY;
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if ((mode == GACC_IFETCH) && (psw.as != PSW_BITS_AS_HOME))
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psw.as = PSW_BITS_AS_PRIMARY;
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switch (psw.as) {
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case PSW_AS_PRIMARY:
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case PSW_BITS_AS_PRIMARY:
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asce->val = vcpu->arch.sie_block->gcr[1];
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return 0;
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case PSW_AS_SECONDARY:
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case PSW_BITS_AS_SECONDARY:
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asce->val = vcpu->arch.sie_block->gcr[7];
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return 0;
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case PSW_AS_HOME:
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case PSW_BITS_AS_HOME:
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asce->val = vcpu->arch.sie_block->gcr[13];
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return 0;
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case PSW_AS_ACCREG:
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case PSW_BITS_AS_ACCREG:
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rc = ar_translation(vcpu, asce, ar, mode);
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if (rc > 0)
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return trans_exc(vcpu, rc, ga, ar, mode, PROT_TYPE_ALC);
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@ -57,9 +57,9 @@ static inline unsigned long kvm_s390_logical_to_effective(struct kvm_vcpu *vcpu,
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{
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psw_t *psw = &vcpu->arch.sie_block->gpsw;
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if (psw_bits(*psw).eaba == PSW_AMODE_64BIT)
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if (psw_bits(*psw).eaba == PSW_BITS_AMODE_64BIT)
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return ga;
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if (psw_bits(*psw).eaba == PSW_AMODE_31BIT)
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if (psw_bits(*psw).eaba == PSW_BITS_AMODE_31BIT)
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return ga & ((1UL << 31) - 1);
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return ga & ((1UL << 24) - 1);
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}
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@ -613,7 +613,7 @@ int kvm_s390_handle_per_event(struct kvm_vcpu *vcpu)
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* instruction. Check primary and home space-switch-event
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* controls. (theoretically home -> home produced no event)
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*/
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if (((new_as == PSW_AS_HOME) ^ old_as_is_home(vcpu)) &&
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if (((new_as == PSW_BITS_AS_HOME) ^ old_as_is_home(vcpu)) &&
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(pssec(vcpu) || hssec(vcpu)))
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vcpu->arch.sie_block->iprcc = PGM_SPACE_SWITCH;
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@ -621,7 +621,7 @@ int kvm_s390_handle_per_event(struct kvm_vcpu *vcpu)
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* PT, PTI, PR, PC instruction operate on primary AS only. Check
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* if the primary-space-switch-event control was or got set.
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*/
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if (new_as == PSW_AS_PRIMARY && !old_as_is_home(vcpu) &&
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if (new_as == PSW_BITS_AS_PRIMARY && !old_as_is_home(vcpu) &&
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(pssec(vcpu) || old_ssec(vcpu)))
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vcpu->arch.sie_block->iprcc = PGM_SPACE_SWITCH;
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}
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@ -361,7 +361,7 @@ static int handle_sske(struct kvm_vcpu *vcpu)
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}
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}
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if (m3 & SSKE_MB) {
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if (psw_bits(vcpu->arch.sie_block->gpsw).eaba == PSW_AMODE_64BIT)
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if (psw_bits(vcpu->arch.sie_block->gpsw).eaba == PSW_BITS_AMODE_64BIT)
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vcpu->run->s.regs.gprs[reg2] &= ~PAGE_MASK;
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else
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vcpu->run->s.regs.gprs[reg2] &= ~0xfffff000UL;
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@ -901,7 +901,7 @@ static int handle_pfmf(struct kvm_vcpu *vcpu)
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/* only support 2G frame size if EDAT2 is available and we are
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not in 24-bit addressing mode */
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if (!test_kvm_facility(vcpu->kvm, 78) ||
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psw_bits(vcpu->arch.sie_block->gpsw).eaba == PSW_AMODE_24BIT)
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psw_bits(vcpu->arch.sie_block->gpsw).eaba == PSW_BITS_AMODE_24BIT)
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return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
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end = (start + (1UL << 31)) & ~((1UL << 31) - 1);
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break;
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@ -938,7 +938,7 @@ static int handle_pfmf(struct kvm_vcpu *vcpu)
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start += PAGE_SIZE;
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}
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if (vcpu->run->s.regs.gprs[reg1] & PFMF_FSC) {
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if (psw_bits(vcpu->arch.sie_block->gpsw).eaba == PSW_AMODE_64BIT) {
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if (psw_bits(vcpu->arch.sie_block->gpsw).eaba == PSW_BITS_AMODE_64BIT) {
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vcpu->run->s.regs.gprs[reg2] = end;
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} else {
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vcpu->run->s.regs.gprs[reg2] &= ~0xffffffffUL;
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@ -103,7 +103,7 @@ void __init paging_init(void)
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__ctl_load(S390_lowcore.kernel_asce, 13, 13);
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psw.mask = __extract_psw();
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psw_bits(psw).t = 1;
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psw_bits(psw).as = PSW_AS_HOME;
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psw_bits(psw).as = PSW_BITS_AS_HOME;
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__load_psw_mask(psw.mask);
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sparse_memory_present_with_active_regions(MAX_NUMNODES);
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