rt2x00: rt2800pci: move interrupt functions to the rt2800mmio module
Move the functions into a separate module, in order to make those usable from other modules. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Gabor Juhos
John W. Linville
parent
b5cfde3fd9
commit
8d03e77218
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@ -34,6 +34,7 @@
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#include "rt2x00.h"
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#include "rt2x00mmio.h"
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#include "rt2800.h"
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#include "rt2800lib.h"
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#include "rt2800mmio.h"
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@ -156,6 +157,401 @@ void rt2800mmio_fill_rxdone(struct queue_entry *entry,
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}
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EXPORT_SYMBOL_GPL(rt2800mmio_fill_rxdone);
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/*
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* Interrupt functions.
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*/
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static void rt2800mmio_wakeup(struct rt2x00_dev *rt2x00dev)
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{
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struct ieee80211_conf conf = { .flags = 0 };
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struct rt2x00lib_conf libconf = { .conf = &conf };
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rt2800_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
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}
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static bool rt2800mmio_txdone_entry_check(struct queue_entry *entry, u32 status)
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{
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__le32 *txwi;
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u32 word;
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int wcid, tx_wcid;
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wcid = rt2x00_get_field32(status, TX_STA_FIFO_WCID);
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txwi = rt2800_drv_get_txwi(entry);
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rt2x00_desc_read(txwi, 1, &word);
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tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
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return (tx_wcid == wcid);
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}
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static bool rt2800mmio_txdone_find_entry(struct queue_entry *entry, void *data)
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{
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u32 status = *(u32 *)data;
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/*
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* rt2800pci hardware might reorder frames when exchanging traffic
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* with multiple BA enabled STAs.
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*
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* For example, a tx queue
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* [ STA1 | STA2 | STA1 | STA2 ]
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* can result in tx status reports
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* [ STA1 | STA1 | STA2 | STA2 ]
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* when the hw decides to aggregate the frames for STA1 into one AMPDU.
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*
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* To mitigate this effect, associate the tx status to the first frame
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* in the tx queue with a matching wcid.
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*/
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if (rt2800mmio_txdone_entry_check(entry, status) &&
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!test_bit(ENTRY_DATA_STATUS_SET, &entry->flags)) {
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/*
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* Got a matching frame, associate the tx status with
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* the frame
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*/
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entry->status = status;
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set_bit(ENTRY_DATA_STATUS_SET, &entry->flags);
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return true;
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}
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/* Check the next frame */
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return false;
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}
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static bool rt2800mmio_txdone_match_first(struct queue_entry *entry, void *data)
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{
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u32 status = *(u32 *)data;
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/*
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* Find the first frame without tx status and assign this status to it
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* regardless if it matches or not.
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*/
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if (!test_bit(ENTRY_DATA_STATUS_SET, &entry->flags)) {
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/*
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* Got a matching frame, associate the tx status with
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* the frame
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*/
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entry->status = status;
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set_bit(ENTRY_DATA_STATUS_SET, &entry->flags);
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return true;
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}
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/* Check the next frame */
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return false;
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}
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static bool rt2800mmio_txdone_release_entries(struct queue_entry *entry,
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void *data)
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{
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if (test_bit(ENTRY_DATA_STATUS_SET, &entry->flags)) {
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rt2800_txdone_entry(entry, entry->status,
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rt2800mmio_get_txwi(entry));
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return false;
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}
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/* No more frames to release */
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return true;
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}
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static bool rt2800mmio_txdone(struct rt2x00_dev *rt2x00dev)
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{
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struct data_queue *queue;
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u32 status;
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u8 qid;
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int max_tx_done = 16;
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while (kfifo_get(&rt2x00dev->txstatus_fifo, &status)) {
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qid = rt2x00_get_field32(status, TX_STA_FIFO_PID_QUEUE);
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if (unlikely(qid >= QID_RX)) {
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/*
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* Unknown queue, this shouldn't happen. Just drop
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* this tx status.
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*/
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rt2x00_warn(rt2x00dev, "Got TX status report with unexpected pid %u, dropping\n",
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qid);
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break;
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}
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queue = rt2x00queue_get_tx_queue(rt2x00dev, qid);
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if (unlikely(queue == NULL)) {
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/*
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* The queue is NULL, this shouldn't happen. Stop
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* processing here and drop the tx status
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*/
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rt2x00_warn(rt2x00dev, "Got TX status for an unavailable queue %u, dropping\n",
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qid);
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break;
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}
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if (unlikely(rt2x00queue_empty(queue))) {
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/*
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* The queue is empty. Stop processing here
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* and drop the tx status.
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*/
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rt2x00_warn(rt2x00dev, "Got TX status for an empty queue %u, dropping\n",
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qid);
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break;
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}
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/*
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* Let's associate this tx status with the first
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* matching frame.
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*/
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if (!rt2x00queue_for_each_entry(queue, Q_INDEX_DONE,
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Q_INDEX, &status,
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rt2800mmio_txdone_find_entry)) {
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/*
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* We cannot match the tx status to any frame, so just
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* use the first one.
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*/
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if (!rt2x00queue_for_each_entry(queue, Q_INDEX_DONE,
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Q_INDEX, &status,
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rt2800mmio_txdone_match_first)) {
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rt2x00_warn(rt2x00dev, "No frame found for TX status on queue %u, dropping\n",
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qid);
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break;
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}
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}
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/*
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* Release all frames with a valid tx status.
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*/
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rt2x00queue_for_each_entry(queue, Q_INDEX_DONE,
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Q_INDEX, NULL,
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rt2800mmio_txdone_release_entries);
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if (--max_tx_done == 0)
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break;
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}
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return !max_tx_done;
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}
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static inline void rt2800mmio_enable_interrupt(struct rt2x00_dev *rt2x00dev,
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struct rt2x00_field32 irq_field)
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{
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u32 reg;
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/*
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* Enable a single interrupt. The interrupt mask register
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* access needs locking.
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*/
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spin_lock_irq(&rt2x00dev->irqmask_lock);
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rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, ®);
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rt2x00_set_field32(®, irq_field, 1);
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rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg);
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spin_unlock_irq(&rt2x00dev->irqmask_lock);
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}
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void rt2800mmio_txstatus_tasklet(unsigned long data)
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{
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struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
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if (rt2800mmio_txdone(rt2x00dev))
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tasklet_schedule(&rt2x00dev->txstatus_tasklet);
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/*
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* No need to enable the tx status interrupt here as we always
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* leave it enabled to minimize the possibility of a tx status
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* register overflow. See comment in interrupt handler.
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*/
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}
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EXPORT_SYMBOL_GPL(rt2800mmio_txstatus_tasklet);
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void rt2800mmio_pretbtt_tasklet(unsigned long data)
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{
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struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
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rt2x00lib_pretbtt(rt2x00dev);
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if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
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rt2800mmio_enable_interrupt(rt2x00dev, INT_MASK_CSR_PRE_TBTT);
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}
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EXPORT_SYMBOL_GPL(rt2800mmio_pretbtt_tasklet);
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void rt2800mmio_tbtt_tasklet(unsigned long data)
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{
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struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
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struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
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u32 reg;
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rt2x00lib_beacondone(rt2x00dev);
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if (rt2x00dev->intf_ap_count) {
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/*
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* The rt2800pci hardware tbtt timer is off by 1us per tbtt
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* causing beacon skew and as a result causing problems with
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* some powersaving clients over time. Shorten the beacon
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* interval every 64 beacons by 64us to mitigate this effect.
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*/
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if (drv_data->tbtt_tick == (BCN_TBTT_OFFSET - 2)) {
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rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG, ®);
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rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL,
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(rt2x00dev->beacon_int * 16) - 1);
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rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg);
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} else if (drv_data->tbtt_tick == (BCN_TBTT_OFFSET - 1)) {
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rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG, ®);
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rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL,
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(rt2x00dev->beacon_int * 16));
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rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg);
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}
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drv_data->tbtt_tick++;
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drv_data->tbtt_tick %= BCN_TBTT_OFFSET;
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}
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if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
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rt2800mmio_enable_interrupt(rt2x00dev, INT_MASK_CSR_TBTT);
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}
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EXPORT_SYMBOL_GPL(rt2800mmio_tbtt_tasklet);
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void rt2800mmio_rxdone_tasklet(unsigned long data)
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{
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struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
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if (rt2x00mmio_rxdone(rt2x00dev))
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tasklet_schedule(&rt2x00dev->rxdone_tasklet);
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else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
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rt2800mmio_enable_interrupt(rt2x00dev, INT_MASK_CSR_RX_DONE);
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}
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EXPORT_SYMBOL_GPL(rt2800mmio_rxdone_tasklet);
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void rt2800mmio_autowake_tasklet(unsigned long data)
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{
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struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
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rt2800mmio_wakeup(rt2x00dev);
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if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
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rt2800mmio_enable_interrupt(rt2x00dev,
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INT_MASK_CSR_AUTO_WAKEUP);
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}
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EXPORT_SYMBOL_GPL(rt2800mmio_autowake_tasklet);
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static void rt2800mmio_txstatus_interrupt(struct rt2x00_dev *rt2x00dev)
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{
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u32 status;
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int i;
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/*
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* The TX_FIFO_STATUS interrupt needs special care. We should
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* read TX_STA_FIFO but we should do it immediately as otherwise
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* the register can overflow and we would lose status reports.
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*
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* Hence, read the TX_STA_FIFO register and copy all tx status
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* reports into a kernel FIFO which is handled in the txstatus
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* tasklet. We use a tasklet to process the tx status reports
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* because we can schedule the tasklet multiple times (when the
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* interrupt fires again during tx status processing).
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*
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* Furthermore we don't disable the TX_FIFO_STATUS
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* interrupt here but leave it enabled so that the TX_STA_FIFO
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* can also be read while the tx status tasklet gets executed.
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*
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* Since we have only one producer and one consumer we don't
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* need to lock the kfifo.
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*/
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for (i = 0; i < rt2x00dev->tx->limit; i++) {
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rt2x00mmio_register_read(rt2x00dev, TX_STA_FIFO, &status);
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if (!rt2x00_get_field32(status, TX_STA_FIFO_VALID))
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break;
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if (!kfifo_put(&rt2x00dev->txstatus_fifo, &status)) {
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rt2x00_warn(rt2x00dev, "TX status FIFO overrun, drop tx status report\n");
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break;
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}
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}
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/* Schedule the tasklet for processing the tx status. */
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tasklet_schedule(&rt2x00dev->txstatus_tasklet);
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}
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irqreturn_t rt2800mmio_interrupt(int irq, void *dev_instance)
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{
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struct rt2x00_dev *rt2x00dev = dev_instance;
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u32 reg, mask;
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/* Read status and ACK all interrupts */
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rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR, ®);
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rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
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if (!reg)
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return IRQ_NONE;
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if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
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return IRQ_HANDLED;
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/*
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* Since INT_MASK_CSR and INT_SOURCE_CSR use the same bits
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* for interrupts and interrupt masks we can just use the value of
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* INT_SOURCE_CSR to create the interrupt mask.
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*/
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mask = ~reg;
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if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS)) {
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rt2800mmio_txstatus_interrupt(rt2x00dev);
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/*
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* Never disable the TX_FIFO_STATUS interrupt.
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*/
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rt2x00_set_field32(&mask, INT_MASK_CSR_TX_FIFO_STATUS, 1);
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}
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if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT))
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tasklet_hi_schedule(&rt2x00dev->pretbtt_tasklet);
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if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT))
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tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
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if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
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tasklet_schedule(&rt2x00dev->rxdone_tasklet);
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if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP))
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tasklet_schedule(&rt2x00dev->autowake_tasklet);
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/*
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* Disable all interrupts for which a tasklet was scheduled right now,
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* the tasklet will reenable the appropriate interrupts.
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*/
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spin_lock(&rt2x00dev->irqmask_lock);
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rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, ®);
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reg &= mask;
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rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg);
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spin_unlock(&rt2x00dev->irqmask_lock);
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return IRQ_HANDLED;
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}
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EXPORT_SYMBOL_GPL(rt2800mmio_interrupt);
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void rt2800mmio_toggle_irq(struct rt2x00_dev *rt2x00dev,
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enum dev_state state)
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{
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u32 reg;
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unsigned long flags;
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/*
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* When interrupts are being enabled, the interrupt registers
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* should clear the register to assure a clean state.
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*/
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if (state == STATE_RADIO_IRQ_ON) {
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rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR, ®);
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rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
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}
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spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
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reg = 0;
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if (state == STATE_RADIO_IRQ_ON) {
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rt2x00_set_field32(®, INT_MASK_CSR_RX_DONE, 1);
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rt2x00_set_field32(®, INT_MASK_CSR_TBTT, 1);
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rt2x00_set_field32(®, INT_MASK_CSR_PRE_TBTT, 1);
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rt2x00_set_field32(®, INT_MASK_CSR_TX_FIFO_STATUS, 1);
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rt2x00_set_field32(®, INT_MASK_CSR_AUTO_WAKEUP, 1);
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}
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rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg);
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spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
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if (state == STATE_RADIO_IRQ_OFF) {
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/*
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* Wait for possibly running tasklets to finish.
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*/
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tasklet_kill(&rt2x00dev->txstatus_tasklet);
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tasklet_kill(&rt2x00dev->rxdone_tasklet);
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tasklet_kill(&rt2x00dev->autowake_tasklet);
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tasklet_kill(&rt2x00dev->tbtt_tasklet);
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tasklet_kill(&rt2x00dev->pretbtt_tasklet);
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}
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}
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EXPORT_SYMBOL_GPL(rt2800mmio_toggle_irq);
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MODULE_AUTHOR(DRV_PROJECT);
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MODULE_VERSION(DRV_VERSION);
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MODULE_DESCRIPTION("rt2800 MMIO library");
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@ -128,5 +128,14 @@ void rt2800mmio_write_tx_desc(struct queue_entry *entry,
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void rt2800mmio_fill_rxdone(struct queue_entry *entry,
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struct rxdone_entry_desc *rxdesc);
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/* Interrupt functions */
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void rt2800mmio_txstatus_tasklet(unsigned long data);
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void rt2800mmio_pretbtt_tasklet(unsigned long data);
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void rt2800mmio_tbtt_tasklet(unsigned long data);
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void rt2800mmio_rxdone_tasklet(unsigned long data);
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void rt2800mmio_autowake_tasklet(unsigned long data);
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irqreturn_t rt2800mmio_interrupt(int irq, void *dev_instance);
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void rt2800mmio_toggle_irq(struct rt2x00_dev *rt2x00dev,
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enum dev_state state);
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#endif /* RT2800MMIO_H */
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|
|
@ -448,45 +448,6 @@ static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
|
|||
/*
|
||||
* Device state switch handlers.
|
||||
*/
|
||||
static void rt2800mmio_toggle_irq(struct rt2x00_dev *rt2x00dev,
|
||||
enum dev_state state)
|
||||
{
|
||||
u32 reg;
|
||||
unsigned long flags;
|
||||
|
||||
/*
|
||||
* When interrupts are being enabled, the interrupt registers
|
||||
* should clear the register to assure a clean state.
|
||||
*/
|
||||
if (state == STATE_RADIO_IRQ_ON) {
|
||||
rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR, ®);
|
||||
rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
|
||||
}
|
||||
|
||||
spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
|
||||
reg = 0;
|
||||
if (state == STATE_RADIO_IRQ_ON) {
|
||||
rt2x00_set_field32(®, INT_MASK_CSR_RX_DONE, 1);
|
||||
rt2x00_set_field32(®, INT_MASK_CSR_TBTT, 1);
|
||||
rt2x00_set_field32(®, INT_MASK_CSR_PRE_TBTT, 1);
|
||||
rt2x00_set_field32(®, INT_MASK_CSR_TX_FIFO_STATUS, 1);
|
||||
rt2x00_set_field32(®, INT_MASK_CSR_AUTO_WAKEUP, 1);
|
||||
}
|
||||
rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg);
|
||||
spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
|
||||
|
||||
if (state == STATE_RADIO_IRQ_OFF) {
|
||||
/*
|
||||
* Wait for possibly running tasklets to finish.
|
||||
*/
|
||||
tasklet_kill(&rt2x00dev->txstatus_tasklet);
|
||||
tasklet_kill(&rt2x00dev->rxdone_tasklet);
|
||||
tasklet_kill(&rt2x00dev->autowake_tasklet);
|
||||
tasklet_kill(&rt2x00dev->tbtt_tasklet);
|
||||
tasklet_kill(&rt2x00dev->pretbtt_tasklet);
|
||||
}
|
||||
}
|
||||
|
||||
static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
|
||||
{
|
||||
u32 reg;
|
||||
|
|
@ -627,355 +588,6 @@ static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
|
|||
return retval;
|
||||
}
|
||||
|
||||
/*
|
||||
* Interrupt functions.
|
||||
*/
|
||||
static void rt2800mmio_wakeup(struct rt2x00_dev *rt2x00dev)
|
||||
{
|
||||
struct ieee80211_conf conf = { .flags = 0 };
|
||||
struct rt2x00lib_conf libconf = { .conf = &conf };
|
||||
|
||||
rt2800_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
|
||||
}
|
||||
|
||||
static bool rt2800mmio_txdone_entry_check(struct queue_entry *entry, u32 status)
|
||||
{
|
||||
__le32 *txwi;
|
||||
u32 word;
|
||||
int wcid, tx_wcid;
|
||||
|
||||
wcid = rt2x00_get_field32(status, TX_STA_FIFO_WCID);
|
||||
|
||||
txwi = rt2800_drv_get_txwi(entry);
|
||||
rt2x00_desc_read(txwi, 1, &word);
|
||||
tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
|
||||
|
||||
return (tx_wcid == wcid);
|
||||
}
|
||||
|
||||
static bool rt2800mmio_txdone_find_entry(struct queue_entry *entry, void *data)
|
||||
{
|
||||
u32 status = *(u32 *)data;
|
||||
|
||||
/*
|
||||
* rt2800pci hardware might reorder frames when exchanging traffic
|
||||
* with multiple BA enabled STAs.
|
||||
*
|
||||
* For example, a tx queue
|
||||
* [ STA1 | STA2 | STA1 | STA2 ]
|
||||
* can result in tx status reports
|
||||
* [ STA1 | STA1 | STA2 | STA2 ]
|
||||
* when the hw decides to aggregate the frames for STA1 into one AMPDU.
|
||||
*
|
||||
* To mitigate this effect, associate the tx status to the first frame
|
||||
* in the tx queue with a matching wcid.
|
||||
*/
|
||||
if (rt2800mmio_txdone_entry_check(entry, status) &&
|
||||
!test_bit(ENTRY_DATA_STATUS_SET, &entry->flags)) {
|
||||
/*
|
||||
* Got a matching frame, associate the tx status with
|
||||
* the frame
|
||||
*/
|
||||
entry->status = status;
|
||||
set_bit(ENTRY_DATA_STATUS_SET, &entry->flags);
|
||||
return true;
|
||||
}
|
||||
|
||||
/* Check the next frame */
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool rt2800mmio_txdone_match_first(struct queue_entry *entry, void *data)
|
||||
{
|
||||
u32 status = *(u32 *)data;
|
||||
|
||||
/*
|
||||
* Find the first frame without tx status and assign this status to it
|
||||
* regardless if it matches or not.
|
||||
*/
|
||||
if (!test_bit(ENTRY_DATA_STATUS_SET, &entry->flags)) {
|
||||
/*
|
||||
* Got a matching frame, associate the tx status with
|
||||
* the frame
|
||||
*/
|
||||
entry->status = status;
|
||||
set_bit(ENTRY_DATA_STATUS_SET, &entry->flags);
|
||||
return true;
|
||||
}
|
||||
|
||||
/* Check the next frame */
|
||||
return false;
|
||||
}
|
||||
static bool rt2800mmio_txdone_release_entries(struct queue_entry *entry,
|
||||
void *data)
|
||||
{
|
||||
if (test_bit(ENTRY_DATA_STATUS_SET, &entry->flags)) {
|
||||
rt2800_txdone_entry(entry, entry->status,
|
||||
rt2800mmio_get_txwi(entry));
|
||||
return false;
|
||||
}
|
||||
|
||||
/* No more frames to release */
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool rt2800mmio_txdone(struct rt2x00_dev *rt2x00dev)
|
||||
{
|
||||
struct data_queue *queue;
|
||||
u32 status;
|
||||
u8 qid;
|
||||
int max_tx_done = 16;
|
||||
|
||||
while (kfifo_get(&rt2x00dev->txstatus_fifo, &status)) {
|
||||
qid = rt2x00_get_field32(status, TX_STA_FIFO_PID_QUEUE);
|
||||
if (unlikely(qid >= QID_RX)) {
|
||||
/*
|
||||
* Unknown queue, this shouldn't happen. Just drop
|
||||
* this tx status.
|
||||
*/
|
||||
rt2x00_warn(rt2x00dev, "Got TX status report with unexpected pid %u, dropping\n",
|
||||
qid);
|
||||
break;
|
||||
}
|
||||
|
||||
queue = rt2x00queue_get_tx_queue(rt2x00dev, qid);
|
||||
if (unlikely(queue == NULL)) {
|
||||
/*
|
||||
* The queue is NULL, this shouldn't happen. Stop
|
||||
* processing here and drop the tx status
|
||||
*/
|
||||
rt2x00_warn(rt2x00dev, "Got TX status for an unavailable queue %u, dropping\n",
|
||||
qid);
|
||||
break;
|
||||
}
|
||||
|
||||
if (unlikely(rt2x00queue_empty(queue))) {
|
||||
/*
|
||||
* The queue is empty. Stop processing here
|
||||
* and drop the tx status.
|
||||
*/
|
||||
rt2x00_warn(rt2x00dev, "Got TX status for an empty queue %u, dropping\n",
|
||||
qid);
|
||||
break;
|
||||
}
|
||||
|
||||
/*
|
||||
* Let's associate this tx status with the first
|
||||
* matching frame.
|
||||
*/
|
||||
if (!rt2x00queue_for_each_entry(queue, Q_INDEX_DONE,
|
||||
Q_INDEX, &status,
|
||||
rt2800mmio_txdone_find_entry)) {
|
||||
/*
|
||||
* We cannot match the tx status to any frame, so just
|
||||
* use the first one.
|
||||
*/
|
||||
if (!rt2x00queue_for_each_entry(queue, Q_INDEX_DONE,
|
||||
Q_INDEX, &status,
|
||||
rt2800mmio_txdone_match_first)) {
|
||||
rt2x00_warn(rt2x00dev, "No frame found for TX status on queue %u, dropping\n",
|
||||
qid);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Release all frames with a valid tx status.
|
||||
*/
|
||||
rt2x00queue_for_each_entry(queue, Q_INDEX_DONE,
|
||||
Q_INDEX, NULL,
|
||||
rt2800mmio_txdone_release_entries);
|
||||
|
||||
if (--max_tx_done == 0)
|
||||
break;
|
||||
}
|
||||
|
||||
return !max_tx_done;
|
||||
}
|
||||
|
||||
static inline void rt2800mmio_enable_interrupt(struct rt2x00_dev *rt2x00dev,
|
||||
struct rt2x00_field32 irq_field)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
/*
|
||||
* Enable a single interrupt. The interrupt mask register
|
||||
* access needs locking.
|
||||
*/
|
||||
spin_lock_irq(&rt2x00dev->irqmask_lock);
|
||||
rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, ®);
|
||||
rt2x00_set_field32(®, irq_field, 1);
|
||||
rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg);
|
||||
spin_unlock_irq(&rt2x00dev->irqmask_lock);
|
||||
}
|
||||
|
||||
static void rt2800mmio_txstatus_tasklet(unsigned long data)
|
||||
{
|
||||
struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
|
||||
if (rt2800mmio_txdone(rt2x00dev))
|
||||
tasklet_schedule(&rt2x00dev->txstatus_tasklet);
|
||||
|
||||
/*
|
||||
* No need to enable the tx status interrupt here as we always
|
||||
* leave it enabled to minimize the possibility of a tx status
|
||||
* register overflow. See comment in interrupt handler.
|
||||
*/
|
||||
}
|
||||
|
||||
static void rt2800mmio_pretbtt_tasklet(unsigned long data)
|
||||
{
|
||||
struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
|
||||
rt2x00lib_pretbtt(rt2x00dev);
|
||||
if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
|
||||
rt2800mmio_enable_interrupt(rt2x00dev, INT_MASK_CSR_PRE_TBTT);
|
||||
}
|
||||
|
||||
static void rt2800mmio_tbtt_tasklet(unsigned long data)
|
||||
{
|
||||
struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
|
||||
struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
|
||||
u32 reg;
|
||||
|
||||
rt2x00lib_beacondone(rt2x00dev);
|
||||
|
||||
if (rt2x00dev->intf_ap_count) {
|
||||
/*
|
||||
* The rt2800pci hardware tbtt timer is off by 1us per tbtt
|
||||
* causing beacon skew and as a result causing problems with
|
||||
* some powersaving clients over time. Shorten the beacon
|
||||
* interval every 64 beacons by 64us to mitigate this effect.
|
||||
*/
|
||||
if (drv_data->tbtt_tick == (BCN_TBTT_OFFSET - 2)) {
|
||||
rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG, ®);
|
||||
rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL,
|
||||
(rt2x00dev->beacon_int * 16) - 1);
|
||||
rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg);
|
||||
} else if (drv_data->tbtt_tick == (BCN_TBTT_OFFSET - 1)) {
|
||||
rt2x00mmio_register_read(rt2x00dev, BCN_TIME_CFG, ®);
|
||||
rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL,
|
||||
(rt2x00dev->beacon_int * 16));
|
||||
rt2x00mmio_register_write(rt2x00dev, BCN_TIME_CFG, reg);
|
||||
}
|
||||
drv_data->tbtt_tick++;
|
||||
drv_data->tbtt_tick %= BCN_TBTT_OFFSET;
|
||||
}
|
||||
|
||||
if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
|
||||
rt2800mmio_enable_interrupt(rt2x00dev, INT_MASK_CSR_TBTT);
|
||||
}
|
||||
|
||||
static void rt2800mmio_rxdone_tasklet(unsigned long data)
|
||||
{
|
||||
struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
|
||||
if (rt2x00mmio_rxdone(rt2x00dev))
|
||||
tasklet_schedule(&rt2x00dev->rxdone_tasklet);
|
||||
else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
|
||||
rt2800mmio_enable_interrupt(rt2x00dev, INT_MASK_CSR_RX_DONE);
|
||||
}
|
||||
|
||||
static void rt2800mmio_autowake_tasklet(unsigned long data)
|
||||
{
|
||||
struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
|
||||
rt2800mmio_wakeup(rt2x00dev);
|
||||
if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
|
||||
rt2800mmio_enable_interrupt(rt2x00dev,
|
||||
INT_MASK_CSR_AUTO_WAKEUP);
|
||||
}
|
||||
|
||||
static void rt2800mmio_txstatus_interrupt(struct rt2x00_dev *rt2x00dev)
|
||||
{
|
||||
u32 status;
|
||||
int i;
|
||||
|
||||
/*
|
||||
* The TX_FIFO_STATUS interrupt needs special care. We should
|
||||
* read TX_STA_FIFO but we should do it immediately as otherwise
|
||||
* the register can overflow and we would lose status reports.
|
||||
*
|
||||
* Hence, read the TX_STA_FIFO register and copy all tx status
|
||||
* reports into a kernel FIFO which is handled in the txstatus
|
||||
* tasklet. We use a tasklet to process the tx status reports
|
||||
* because we can schedule the tasklet multiple times (when the
|
||||
* interrupt fires again during tx status processing).
|
||||
*
|
||||
* Furthermore we don't disable the TX_FIFO_STATUS
|
||||
* interrupt here but leave it enabled so that the TX_STA_FIFO
|
||||
* can also be read while the tx status tasklet gets executed.
|
||||
*
|
||||
* Since we have only one producer and one consumer we don't
|
||||
* need to lock the kfifo.
|
||||
*/
|
||||
for (i = 0; i < rt2x00dev->tx->limit; i++) {
|
||||
rt2x00mmio_register_read(rt2x00dev, TX_STA_FIFO, &status);
|
||||
|
||||
if (!rt2x00_get_field32(status, TX_STA_FIFO_VALID))
|
||||
break;
|
||||
|
||||
if (!kfifo_put(&rt2x00dev->txstatus_fifo, &status)) {
|
||||
rt2x00_warn(rt2x00dev, "TX status FIFO overrun, drop tx status report\n");
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Schedule the tasklet for processing the tx status. */
|
||||
tasklet_schedule(&rt2x00dev->txstatus_tasklet);
|
||||
}
|
||||
|
||||
static irqreturn_t rt2800mmio_interrupt(int irq, void *dev_instance)
|
||||
{
|
||||
struct rt2x00_dev *rt2x00dev = dev_instance;
|
||||
u32 reg, mask;
|
||||
|
||||
/* Read status and ACK all interrupts */
|
||||
rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR, ®);
|
||||
rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
|
||||
|
||||
if (!reg)
|
||||
return IRQ_NONE;
|
||||
|
||||
if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
|
||||
return IRQ_HANDLED;
|
||||
|
||||
/*
|
||||
* Since INT_MASK_CSR and INT_SOURCE_CSR use the same bits
|
||||
* for interrupts and interrupt masks we can just use the value of
|
||||
* INT_SOURCE_CSR to create the interrupt mask.
|
||||
*/
|
||||
mask = ~reg;
|
||||
|
||||
if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS)) {
|
||||
rt2800mmio_txstatus_interrupt(rt2x00dev);
|
||||
/*
|
||||
* Never disable the TX_FIFO_STATUS interrupt.
|
||||
*/
|
||||
rt2x00_set_field32(&mask, INT_MASK_CSR_TX_FIFO_STATUS, 1);
|
||||
}
|
||||
|
||||
if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT))
|
||||
tasklet_hi_schedule(&rt2x00dev->pretbtt_tasklet);
|
||||
|
||||
if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT))
|
||||
tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
|
||||
|
||||
if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
|
||||
tasklet_schedule(&rt2x00dev->rxdone_tasklet);
|
||||
|
||||
if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP))
|
||||
tasklet_schedule(&rt2x00dev->autowake_tasklet);
|
||||
|
||||
/*
|
||||
* Disable all interrupts for which a tasklet was scheduled right now,
|
||||
* the tasklet will reenable the appropriate interrupts.
|
||||
*/
|
||||
spin_lock(&rt2x00dev->irqmask_lock);
|
||||
rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, ®);
|
||||
reg &= mask;
|
||||
rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg);
|
||||
spin_unlock(&rt2x00dev->irqmask_lock);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
/*
|
||||
* Device probe functions.
|
||||
*/
|
||||
|
|
|
|||
Loading…
Reference in New Issue