Merge remote branch 'nouveau/for-airlied' of ../drm-nouveau-next into drm-linus
* 'nouveau/for-airlied' of ../drm-nouveau-next: drm/nv50: prevent switching off SOR when in use for DVI-over-DP drm/nv50: fail auxch transaction if reply count not what we expect drm/nouveau: fix failure path if userspace specifies no valid memtypes drm/nouveau: report LVDS as disconnected if lid closed drm/nv50: prevent accidently turning off encoders we're actually using drm/nv50: fix alignment of per-channel fifo cache drm/nouveau: Evict buffers in VRAM before freeing sgdma drm/nouveau: Acknowledge DMA_VTX_PROTECTION PGRAPH interrupts drm/nouveau: fix thinko in nv04_instmem.c drm/nouveau: fix a race condition in nouveau_dma_wait()
This commit is contained in:
commit
8d586fe65a
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@ -24,9 +24,12 @@
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*
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*/
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#include <acpi/button.h>
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#include "drmP.h"
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#include "drm_edid.h"
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#include "drm_crtc_helper.h"
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#include "nouveau_reg.h"
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#include "nouveau_drv.h"
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#include "nouveau_encoder.h"
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@ -235,6 +238,10 @@ nouveau_connector_detect(struct drm_connector *connector)
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if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
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nv_encoder = find_encoder_by_type(connector, OUTPUT_LVDS);
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if (nv_encoder && nv_connector->native_mode) {
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#ifdef CONFIG_ACPI
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if (!nouveau_ignorelid && !acpi_lid_open())
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return connector_status_disconnected;
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#endif
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nouveau_connector_set_encoder(connector, nv_encoder);
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return connector_status_connected;
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}
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@ -126,47 +126,52 @@ OUT_RINGp(struct nouveau_channel *chan, const void *data, unsigned nr_dwords)
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chan->dma.cur += nr_dwords;
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}
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static inline bool
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READ_GET(struct nouveau_channel *chan, uint32_t *get)
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/* Fetch and adjust GPU GET pointer
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*
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* Returns:
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* value >= 0, the adjusted GET pointer
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* -EINVAL if GET pointer currently outside main push buffer
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* -EBUSY if timeout exceeded
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*/
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static inline int
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READ_GET(struct nouveau_channel *chan, uint32_t *prev_get, uint32_t *timeout)
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{
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uint32_t val;
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val = nvchan_rd32(chan, chan->user_get);
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if (val < chan->pushbuf_base ||
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val > chan->pushbuf_base + (chan->dma.max << 2)) {
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/* meaningless to dma_wait() except to know whether the
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* GPU has stalled or not
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*/
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*get = val;
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return false;
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/* reset counter as long as GET is still advancing, this is
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* to avoid misdetecting a GPU lockup if the GPU happens to
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* just be processing an operation that takes a long time
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*/
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if (val != *prev_get) {
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*prev_get = val;
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*timeout = 0;
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}
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*get = (val - chan->pushbuf_base) >> 2;
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return true;
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if ((++*timeout & 0xff) == 0) {
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DRM_UDELAY(1);
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if (*timeout > 100000)
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return -EBUSY;
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}
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if (val < chan->pushbuf_base ||
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val > chan->pushbuf_base + (chan->dma.max << 2))
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return -EINVAL;
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return (val - chan->pushbuf_base) >> 2;
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}
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int
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nouveau_dma_wait(struct nouveau_channel *chan, int size)
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{
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uint32_t get, prev_get = 0, cnt = 0;
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bool get_valid;
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uint32_t prev_get = 0, cnt = 0;
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int get;
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while (chan->dma.free < size) {
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/* reset counter as long as GET is still advancing, this is
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* to avoid misdetecting a GPU lockup if the GPU happens to
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* just be processing an operation that takes a long time
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*/
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get_valid = READ_GET(chan, &get);
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if (get != prev_get) {
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prev_get = get;
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cnt = 0;
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}
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if ((++cnt & 0xff) == 0) {
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DRM_UDELAY(1);
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if (cnt > 100000)
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return -EBUSY;
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}
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get = READ_GET(chan, &prev_get, &cnt);
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if (unlikely(get == -EBUSY))
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return -EBUSY;
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/* loop until we have a usable GET pointer. the value
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* we read from the GPU may be outside the main ring if
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@ -177,7 +182,7 @@ nouveau_dma_wait(struct nouveau_channel *chan, int size)
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* from the SKIPS area, so the code below doesn't have to deal
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* with some fun corner cases.
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*/
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if (!get_valid || get < NOUVEAU_DMA_SKIPS)
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if (unlikely(get == -EINVAL) || get < NOUVEAU_DMA_SKIPS)
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continue;
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if (get <= chan->dma.cur) {
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@ -203,6 +208,19 @@ nouveau_dma_wait(struct nouveau_channel *chan, int size)
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* after processing the currently pending commands.
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*/
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OUT_RING(chan, chan->pushbuf_base | 0x20000000);
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/* wait for GET to depart from the skips area.
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* prevents writing GET==PUT and causing a race
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* condition that causes us to think the GPU is
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* idle when it's not.
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*/
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do {
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get = READ_GET(chan, &prev_get, &cnt);
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if (unlikely(get == -EBUSY))
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return -EBUSY;
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if (unlikely(get == -EINVAL))
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continue;
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} while (get <= NOUVEAU_DMA_SKIPS);
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WRITE_PUT(NOUVEAU_DMA_SKIPS);
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/* we're now submitting commands at the start of
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@ -490,7 +490,8 @@ nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
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if (!nv_wait(NV50_AUXCH_CTRL(index), 0x00010000, 0x00000000)) {
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NV_ERROR(dev, "expected bit 16 == 0, got 0x%08x\n",
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nv_rd32(dev, NV50_AUXCH_CTRL(index)));
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return -EBUSY;
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ret = -EBUSY;
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goto out;
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}
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udelay(400);
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@ -501,6 +502,11 @@ nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
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break;
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}
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if ((stat & NV50_AUXCH_STAT_COUNT) != data_nr) {
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ret = -EREMOTEIO;
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goto out;
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}
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if (cmd & 1) {
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for (i = 0; i < 4; i++) {
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data32[i] = nv_rd32(dev, NV50_AUXCH_DATA_IN(index, i));
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@ -71,6 +71,10 @@ MODULE_PARM_DESC(uscript_tmds, "TMDS output script table ID (>=GeForce 8)");
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int nouveau_uscript_tmds = -1;
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module_param_named(uscript_tmds, nouveau_uscript_tmds, int, 0400);
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MODULE_PARM_DESC(ignorelid, "Ignore ACPI lid status");
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int nouveau_ignorelid = 0;
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module_param_named(ignorelid, nouveau_ignorelid, int, 0400);
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MODULE_PARM_DESC(tv_norm, "Default TV norm.\n"
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"\t\tSupported: PAL, PAL-M, PAL-N, PAL-Nc, NTSC-M, NTSC-J,\n"
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"\t\t\thd480i, hd480p, hd576i, hd576p, hd720p, hd1080i.\n"
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@ -677,6 +677,7 @@ extern char *nouveau_tv_norm;
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extern int nouveau_reg_debug;
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extern char *nouveau_vbios;
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extern int nouveau_ctxfw;
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extern int nouveau_ignorelid;
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/* nouveau_state.c */
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extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
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@ -321,6 +321,7 @@ retry:
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else {
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NV_ERROR(dev, "invalid valid domains: 0x%08x\n",
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b->valid_domains);
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list_add_tail(&nvbo->entry, &op->both_list);
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validate_fini(op, NULL);
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return -EINVAL;
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}
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@ -483,6 +483,13 @@ nouveau_pgraph_intr_error(struct drm_device *dev, uint32_t nsource)
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if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
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if (nouveau_pgraph_intr_swmthd(dev, &trap))
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unhandled = 1;
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} else if (nsource & NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION) {
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uint32_t v = nv_rd32(dev, 0x402000);
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nv_wr32(dev, 0x402000, v);
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/* dump the error anyway for now: it's useful for
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Gallium development */
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unhandled = 1;
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} else {
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unhandled = 1;
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}
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@ -386,7 +386,6 @@ void nouveau_mem_close(struct drm_device *dev)
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nouveau_bo_unpin(dev_priv->vga_ram);
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nouveau_bo_ref(NULL, &dev_priv->vga_ram);
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ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
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ttm_bo_device_release(&dev_priv->ttm.bdev);
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nouveau_ttm_global_release(dev_priv);
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@ -525,6 +525,7 @@ static void nouveau_card_takedown(struct drm_device *dev)
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engine->mc.takedown(dev);
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mutex_lock(&dev->struct_mutex);
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ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
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ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT);
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mutex_unlock(&dev->struct_mutex);
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nouveau_sgdma_takedown(dev);
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* of vram. For now, only reserve a small piece until we know
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* more about what each chipset requires.
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*/
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switch (dev_priv->chipset & 0xf0) {
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switch (dev_priv->chipset) {
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case 0x40:
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case 0x47:
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case 0x49:
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@ -432,6 +432,7 @@ nv50_crtc_prepare(struct drm_crtc *crtc)
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struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
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struct drm_device *dev = crtc->dev;
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struct drm_encoder *encoder;
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uint32_t dac = 0, sor = 0;
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NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
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list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
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struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
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if (drm_helper_encoder_in_use(encoder))
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if (!drm_helper_encoder_in_use(encoder))
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continue;
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if (nv_encoder->dcb->type == OUTPUT_ANALOG ||
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nv_encoder->dcb->type == OUTPUT_TV)
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dac |= (1 << nv_encoder->or);
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else
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sor |= (1 << nv_encoder->or);
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}
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list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
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struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
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if (nv_encoder->dcb->type == OUTPUT_ANALOG ||
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nv_encoder->dcb->type == OUTPUT_TV) {
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if (dac & (1 << nv_encoder->or))
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continue;
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} else {
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if (sor & (1 << nv_encoder->or))
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continue;
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}
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nv_encoder->disconnect(nv_encoder);
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}
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@ -272,7 +272,7 @@ nv50_fifo_create_context(struct nouveau_channel *chan)
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return ret;
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ramfc = chan->ramfc->gpuobj;
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ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, 4096, 256,
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ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, 4096, 1024,
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0, &chan->cache);
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if (ret)
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return ret;
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@ -90,11 +90,24 @@ nv50_sor_dpms(struct drm_encoder *encoder, int mode)
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{
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struct drm_device *dev = encoder->dev;
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struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
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struct drm_encoder *enc;
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uint32_t val;
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int or = nv_encoder->or;
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NV_DEBUG_KMS(dev, "or %d mode %d\n", or, mode);
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nv_encoder->last_dpms = mode;
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list_for_each_entry(enc, &dev->mode_config.encoder_list, head) {
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struct nouveau_encoder *nvenc = nouveau_encoder(enc);
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if (nvenc == nv_encoder ||
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nvenc->dcb->or != nv_encoder->dcb->or)
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continue;
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if (nvenc->last_dpms == DRM_MODE_DPMS_ON)
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return;
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}
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/* wait for it to be done */
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if (!nv_wait(NV50_PDISPLAY_SOR_DPMS_CTRL(or),
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NV50_PDISPLAY_SOR_DPMS_CTRL_PENDING, 0)) {
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