clk: tegra: Format tables consistently
Use spaces around { and } and pad values so that the cells are properly
aligned.
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Thierry Reding
parent
e52d7c04bb
commit
8d99704fde
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@ -183,32 +183,32 @@ static struct div_nmp pllxc_nmp = {
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};
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static struct pdiv_map pllxc_p[] = {
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{ .pdiv = 1, .hw_val = 0 },
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{ .pdiv = 2, .hw_val = 1 },
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{ .pdiv = 3, .hw_val = 2 },
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{ .pdiv = 4, .hw_val = 3 },
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{ .pdiv = 5, .hw_val = 4 },
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{ .pdiv = 6, .hw_val = 5 },
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{ .pdiv = 8, .hw_val = 6 },
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{ .pdiv = 10, .hw_val = 7 },
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{ .pdiv = 12, .hw_val = 8 },
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{ .pdiv = 16, .hw_val = 9 },
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{ .pdiv = 1, .hw_val = 0 },
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{ .pdiv = 2, .hw_val = 1 },
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{ .pdiv = 3, .hw_val = 2 },
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{ .pdiv = 4, .hw_val = 3 },
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{ .pdiv = 5, .hw_val = 4 },
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{ .pdiv = 6, .hw_val = 5 },
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{ .pdiv = 8, .hw_val = 6 },
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{ .pdiv = 10, .hw_val = 7 },
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{ .pdiv = 12, .hw_val = 8 },
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{ .pdiv = 16, .hw_val = 9 },
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{ .pdiv = 12, .hw_val = 10 },
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{ .pdiv = 16, .hw_val = 11 },
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{ .pdiv = 20, .hw_val = 12 },
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{ .pdiv = 24, .hw_val = 13 },
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{ .pdiv = 32, .hw_val = 14 },
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{ .pdiv = 0, .hw_val = 0 },
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{ .pdiv = 0, .hw_val = 0 },
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};
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static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
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{ 12000000, 624000000, 104, 0, 2},
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{ 12000000, 600000000, 100, 0, 2},
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{ 13000000, 600000000, 92, 0, 2}, /* actual: 598.0 MHz */
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{ 16800000, 600000000, 71, 0, 2}, /* actual: 596.4 MHz */
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{ 19200000, 600000000, 62, 0, 2}, /* actual: 595.2 MHz */
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{ 26000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */
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{ 0, 0, 0, 0, 0, 0 },
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{ 12000000, 624000000, 104, 0, 2, 0 },
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{ 12000000, 600000000, 100, 0, 2, 0 },
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{ 13000000, 600000000, 92, 0, 2, 0 }, /* actual: 598.0 MHz */
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{ 16800000, 600000000, 71, 0, 2, 0 }, /* actual: 596.4 MHz */
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{ 19200000, 600000000, 62, 0, 2, 0 }, /* actual: 595.2 MHz */
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{ 26000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */
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{ 0, 0, 0, 0, 0, 0 },
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};
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static struct tegra_clk_pll_params pll_c_params = {
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@ -245,21 +245,21 @@ static struct div_nmp pllcx_nmp = {
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};
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static struct pdiv_map pllc_p[] = {
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{ .pdiv = 1, .hw_val = 0 },
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{ .pdiv = 2, .hw_val = 1 },
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{ .pdiv = 4, .hw_val = 3 },
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{ .pdiv = 8, .hw_val = 5 },
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{ .pdiv = 1, .hw_val = 0 },
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{ .pdiv = 2, .hw_val = 1 },
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{ .pdiv = 4, .hw_val = 3 },
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{ .pdiv = 8, .hw_val = 5 },
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{ .pdiv = 16, .hw_val = 7 },
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{ .pdiv = 0, .hw_val = 0 },
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{ .pdiv = 0, .hw_val = 0 },
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};
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static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = {
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{12000000, 600000000, 100, 0, 2},
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{13000000, 600000000, 92, 0, 2}, /* actual: 598.0 MHz */
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{16800000, 600000000, 71, 0, 2}, /* actual: 596.4 MHz */
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{19200000, 600000000, 62, 0, 2}, /* actual: 595.2 MHz */
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{26000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */
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{0, 0, 0, 0, 0, 0},
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{ 12000000, 600000000, 100, 0, 2, 0 },
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{ 13000000, 600000000, 92, 0, 2, 0 }, /* actual: 598.0 MHz */
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{ 16800000, 600000000, 71, 0, 2, 0 }, /* actual: 596.4 MHz */
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{ 19200000, 600000000, 62, 0, 2, 0 }, /* actual: 595.2 MHz */
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{ 26000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */
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{ 0, 0, 0, 0, 0, 0 },
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};
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static struct tegra_clk_pll_params pll_c2_params = {
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@ -325,12 +325,12 @@ static struct pdiv_map pllm_p[] = {
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};
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static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
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{12000000, 800000000, 66, 0, 1}, /* actual: 792.0 MHz */
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{13000000, 800000000, 61, 0, 1}, /* actual: 793.0 MHz */
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{16800000, 800000000, 47, 0, 1}, /* actual: 789.6 MHz */
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{19200000, 800000000, 41, 0, 1}, /* actual: 787.2 MHz */
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{26000000, 800000000, 61, 1, 1}, /* actual: 793.0 MHz */
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{0, 0, 0, 0, 0, 0},
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{ 12000000, 800000000, 66, 0, 1, 0 }, /* actual: 792.0 MHz */
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{ 13000000, 800000000, 61, 0, 1, 0 }, /* actual: 793.0 MHz */
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{ 16800000, 800000000, 47, 0, 1, 0 }, /* actual: 789.6 MHz */
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{ 19200000, 800000000, 41, 0, 1, 0 }, /* actual: 787.2 MHz */
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{ 26000000, 800000000, 61, 1, 1, 0 }, /* actual: 793.0 MHz */
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{ 0, 0, 0, 0, 0, 0 },
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};
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static struct tegra_clk_pll_params pll_m_params = {
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@ -364,12 +364,12 @@ static struct div_nmp pllp_nmp = {
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};
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static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
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{12000000, 216000000, 432, 12, 1, 8},
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{13000000, 216000000, 432, 13, 1, 8},
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{16800000, 216000000, 360, 14, 1, 8},
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{19200000, 216000000, 360, 16, 1, 8},
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{26000000, 216000000, 432, 26, 1, 8},
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{0, 0, 0, 0, 0, 0},
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{ 12000000, 216000000, 432, 12, 1, 8 },
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{ 13000000, 216000000, 432, 13, 1, 8 },
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{ 16800000, 216000000, 360, 14, 1, 8 },
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{ 19200000, 216000000, 360, 16, 1, 8 },
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{ 26000000, 216000000, 432, 26, 1, 8 },
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{ 0, 0, 0, 0, 0, 0 },
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};
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static struct tegra_clk_pll_params pll_p_params = {
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@ -391,14 +391,13 @@ static struct tegra_clk_pll_params pll_p_params = {
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};
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static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
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{9600000, 282240000, 147, 5, 0, 4},
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{9600000, 368640000, 192, 5, 0, 4},
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{9600000, 240000000, 200, 8, 0, 8},
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{28800000, 282240000, 245, 25, 0, 8},
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{28800000, 368640000, 320, 25, 0, 8},
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{28800000, 240000000, 200, 24, 0, 8},
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{0, 0, 0, 0, 0, 0},
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{ 9600000, 282240000, 147, 5, 0, 4 },
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{ 9600000, 368640000, 192, 5, 0, 4 },
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{ 9600000, 240000000, 200, 8, 0, 8 },
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{ 28800000, 282240000, 245, 25, 0, 8 },
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{ 28800000, 368640000, 320, 25, 0, 8 },
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{ 28800000, 240000000, 200, 24, 0, 8 },
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{ 0, 0, 0, 0, 0, 0 },
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};
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@ -420,24 +419,21 @@ static struct tegra_clk_pll_params pll_a_params = {
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};
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static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
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{12000000, 216000000, 864, 12, 2, 12},
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{13000000, 216000000, 864, 13, 2, 12},
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{16800000, 216000000, 720, 14, 2, 12},
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{19200000, 216000000, 720, 16, 2, 12},
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{26000000, 216000000, 864, 26, 2, 12},
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{12000000, 594000000, 594, 12, 0, 12},
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{13000000, 594000000, 594, 13, 0, 12},
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{16800000, 594000000, 495, 14, 0, 12},
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{19200000, 594000000, 495, 16, 0, 12},
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{26000000, 594000000, 594, 26, 0, 12},
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{12000000, 1000000000, 1000, 12, 0, 12},
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{13000000, 1000000000, 1000, 13, 0, 12},
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{19200000, 1000000000, 625, 12, 0, 12},
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{26000000, 1000000000, 1000, 26, 0, 12},
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{0, 0, 0, 0, 0, 0},
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{ 12000000, 216000000, 864, 12, 2, 12 },
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{ 13000000, 216000000, 864, 13, 2, 12 },
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{ 16800000, 216000000, 720, 14, 2, 12 },
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{ 19200000, 216000000, 720, 16, 2, 12 },
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{ 26000000, 216000000, 864, 26, 2, 12 },
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{ 12000000, 594000000, 594, 12, 0, 12 },
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{ 13000000, 594000000, 594, 13, 0, 12 },
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{ 16800000, 594000000, 495, 14, 0, 12 },
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{ 19200000, 594000000, 495, 16, 0, 12 },
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{ 26000000, 594000000, 594, 26, 0, 12 },
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{ 12000000, 1000000000, 1000, 12, 0, 12 },
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{ 13000000, 1000000000, 1000, 13, 0, 12 },
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{ 19200000, 1000000000, 625, 12, 0, 12 },
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{ 26000000, 1000000000, 1000, 26, 0, 12 },
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{ 0, 0, 0, 0, 0, 0 },
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};
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static struct tegra_clk_pll_params pll_d_params = {
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@ -492,12 +488,12 @@ static struct div_nmp pllu_nmp = {
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};
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static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
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{12000000, 480000000, 960, 12, 0, 12},
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{13000000, 480000000, 960, 13, 0, 12},
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{16800000, 480000000, 400, 7, 0, 5},
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{19200000, 480000000, 200, 4, 0, 3},
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{26000000, 480000000, 960, 26, 0, 12},
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{0, 0, 0, 0, 0, 0},
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{ 12000000, 480000000, 960, 12, 0, 12 },
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{ 13000000, 480000000, 960, 13, 0, 12 },
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{ 16800000, 480000000, 400, 7, 0, 5 },
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{ 19200000, 480000000, 200, 4, 0, 3 },
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{ 26000000, 480000000, 960, 26, 0, 12 },
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{ 0, 0, 0, 0, 0, 0 },
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};
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static struct tegra_clk_pll_params pll_u_params = {
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@ -521,13 +517,12 @@ static struct tegra_clk_pll_params pll_u_params = {
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static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
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/* 1 GHz */
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{12000000, 1000000000, 83, 0, 1}, /* actual: 996.0 MHz */
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{13000000, 1000000000, 76, 0, 1}, /* actual: 988.0 MHz */
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{16800000, 1000000000, 59, 0, 1}, /* actual: 991.2 MHz */
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{19200000, 1000000000, 52, 0, 1}, /* actual: 998.4 MHz */
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{26000000, 1000000000, 76, 1, 1}, /* actual: 988.0 MHz */
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{0, 0, 0, 0, 0, 0},
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{ 12000000, 1000000000, 83, 0, 1, 0 }, /* actual: 996.0 MHz */
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{ 13000000, 1000000000, 76, 0, 1, 0 }, /* actual: 988.0 MHz */
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{ 16800000, 1000000000, 59, 0, 1, 0 }, /* actual: 991.2 MHz */
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{ 19200000, 1000000000, 52, 0, 1, 0 }, /* actual: 998.4 MHz */
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{ 26000000, 1000000000, 76, 1, 1, 0 }, /* actual: 988.0 MHz */
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{ 0, 0, 0, 0, 0, 0 },
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};
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static struct tegra_clk_pll_params pll_x_params = {
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@ -556,10 +551,10 @@ static struct tegra_clk_pll_params pll_x_params = {
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static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
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/* PLLE special case: use cpcon field to store cml divider value */
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{336000000, 100000000, 100, 21, 16, 11},
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{312000000, 100000000, 200, 26, 24, 13},
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{12000000, 100000000, 200, 1, 24, 13},
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{0, 0, 0, 0, 0, 0},
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{ 336000000, 100000000, 100, 21, 16, 11 },
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{ 312000000, 100000000, 200, 26, 24, 13 },
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{ 12000000, 100000000, 200, 1, 24, 13 },
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{ 0, 0, 0, 0, 0, 0 },
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};
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static struct div_nmp plle_nmp = {
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@ -619,12 +614,12 @@ static struct tegra_clk_pll_params pll_re_vco_params = {
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/* possible OSC frequencies in Hz */
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static unsigned long tegra114_input_freq[] = {
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[0] = 13000000,
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[1] = 16800000,
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[4] = 19200000,
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[5] = 38400000,
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[8] = 12000000,
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[9] = 48000000,
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[ 0] = 13000000,
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[ 1] = 16800000,
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[ 4] = 19200000,
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[ 5] = 38400000,
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[ 8] = 12000000,
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[ 9] = 48000000,
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[12] = 26000000,
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};
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@ -644,21 +639,27 @@ struct utmi_clk_param {
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};
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static const struct utmi_clk_param utmi_parameters[] = {
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{.osc_frequency = 13000000, .enable_delay_count = 0x02,
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.stable_count = 0x33, .active_delay_count = 0x05,
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.xtal_freq_count = 0x7F},
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{.osc_frequency = 19200000, .enable_delay_count = 0x03,
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.stable_count = 0x4B, .active_delay_count = 0x06,
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.xtal_freq_count = 0xBB},
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{.osc_frequency = 12000000, .enable_delay_count = 0x02,
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.stable_count = 0x2F, .active_delay_count = 0x04,
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.xtal_freq_count = 0x76},
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{.osc_frequency = 26000000, .enable_delay_count = 0x04,
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.stable_count = 0x66, .active_delay_count = 0x09,
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.xtal_freq_count = 0xFE},
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{.osc_frequency = 16800000, .enable_delay_count = 0x03,
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.stable_count = 0x41, .active_delay_count = 0x0A,
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.xtal_freq_count = 0xA4},
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{
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.osc_frequency = 13000000, .enable_delay_count = 0x02,
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.stable_count = 0x33, .active_delay_count = 0x05,
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.xtal_freq_count = 0x7f
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}, {
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.osc_frequency = 19200000, .enable_delay_count = 0x03,
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.stable_count = 0x4b, .active_delay_count = 0x06,
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.xtal_freq_count = 0xbb
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}, {
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.osc_frequency = 12000000, .enable_delay_count = 0x02,
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.stable_count = 0x2f, .active_delay_count = 0x04,
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.xtal_freq_count = 0x76
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}, {
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.osc_frequency = 26000000, .enable_delay_count = 0x04,
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.stable_count = 0x66, .active_delay_count = 0x09,
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.xtal_freq_count = 0xfe
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}, {
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.osc_frequency = 16800000, .enable_delay_count = 0x03,
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.stable_count = 0x41, .active_delay_count = 0x0a,
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.xtal_freq_count = 0xa4
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},
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};
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/* peripheral mux definitions */
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@ -1286,37 +1287,37 @@ static const struct of_device_id pmc_match[] __initconst = {
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* breaks
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*/
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static struct tegra_clk_init_table init_table[] __initdata = {
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{TEGRA114_CLK_UARTA, TEGRA114_CLK_PLL_P, 408000000, 0},
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{TEGRA114_CLK_UARTB, TEGRA114_CLK_PLL_P, 408000000, 0},
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{TEGRA114_CLK_UARTC, TEGRA114_CLK_PLL_P, 408000000, 0},
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{TEGRA114_CLK_UARTD, TEGRA114_CLK_PLL_P, 408000000, 0},
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{TEGRA114_CLK_PLL_A, TEGRA114_CLK_CLK_MAX, 564480000, 1},
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{TEGRA114_CLK_PLL_A_OUT0, TEGRA114_CLK_CLK_MAX, 11289600, 1},
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{TEGRA114_CLK_EXTERN1, TEGRA114_CLK_PLL_A_OUT0, 0, 1},
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{TEGRA114_CLK_CLK_OUT_1_MUX, TEGRA114_CLK_EXTERN1, 0, 1},
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{TEGRA114_CLK_CLK_OUT_1, TEGRA114_CLK_CLK_MAX, 0, 1},
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{TEGRA114_CLK_I2S0, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0},
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{TEGRA114_CLK_I2S1, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0},
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{TEGRA114_CLK_I2S2, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0},
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{TEGRA114_CLK_I2S3, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0},
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{TEGRA114_CLK_I2S4, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0},
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{TEGRA114_CLK_HOST1X, TEGRA114_CLK_PLL_P, 136000000, 0},
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{TEGRA114_CLK_DFLL_SOC, TEGRA114_CLK_PLL_P, 51000000, 1},
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{TEGRA114_CLK_DFLL_REF, TEGRA114_CLK_PLL_P, 51000000, 1},
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{TEGRA114_CLK_DISP1, TEGRA114_CLK_PLL_P, 0, 0},
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{TEGRA114_CLK_DISP2, TEGRA114_CLK_PLL_P, 0, 0},
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{TEGRA114_CLK_GR2D, TEGRA114_CLK_PLL_C2, 300000000, 0},
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{TEGRA114_CLK_GR3D, TEGRA114_CLK_PLL_C2, 300000000, 0},
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{TEGRA114_CLK_DSIALP, TEGRA114_CLK_PLL_P, 68000000, 0},
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{TEGRA114_CLK_DSIBLP, TEGRA114_CLK_PLL_P, 68000000, 0},
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{TEGRA114_CLK_PLL_RE_VCO, TEGRA114_CLK_CLK_MAX, 612000000, 0},
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{TEGRA114_CLK_XUSB_SS_SRC, TEGRA114_CLK_PLL_RE_OUT, 122400000, 0},
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{TEGRA114_CLK_XUSB_FS_SRC, TEGRA114_CLK_PLL_U_48M, 48000000, 0},
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{TEGRA114_CLK_XUSB_HS_SRC, TEGRA114_CLK_XUSB_SS_DIV2, 61200000, 0},
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{TEGRA114_CLK_XUSB_FALCON_SRC, TEGRA114_CLK_PLL_P, 204000000, 0},
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{TEGRA114_CLK_XUSB_HOST_SRC, TEGRA114_CLK_PLL_P, 102000000, 0},
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/* This MUST be the last entry. */
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{TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_CLK_MAX, 0, 0},
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{ TEGRA114_CLK_UARTA, TEGRA114_CLK_PLL_P, 408000000, 0 },
|
||||
{ TEGRA114_CLK_UARTB, TEGRA114_CLK_PLL_P, 408000000, 0 },
|
||||
{ TEGRA114_CLK_UARTC, TEGRA114_CLK_PLL_P, 408000000, 0 },
|
||||
{ TEGRA114_CLK_UARTD, TEGRA114_CLK_PLL_P, 408000000, 0 },
|
||||
{ TEGRA114_CLK_PLL_A, TEGRA114_CLK_CLK_MAX, 564480000, 1 },
|
||||
{ TEGRA114_CLK_PLL_A_OUT0, TEGRA114_CLK_CLK_MAX, 11289600, 1 },
|
||||
{ TEGRA114_CLK_EXTERN1, TEGRA114_CLK_PLL_A_OUT0, 0, 1 },
|
||||
{ TEGRA114_CLK_CLK_OUT_1_MUX, TEGRA114_CLK_EXTERN1, 0, 1 },
|
||||
{ TEGRA114_CLK_CLK_OUT_1, TEGRA114_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA114_CLK_I2S0, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA114_CLK_I2S1, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA114_CLK_I2S2, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA114_CLK_I2S3, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA114_CLK_I2S4, TEGRA114_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA114_CLK_HOST1X, TEGRA114_CLK_PLL_P, 136000000, 0 },
|
||||
{ TEGRA114_CLK_DFLL_SOC, TEGRA114_CLK_PLL_P, 51000000, 1 },
|
||||
{ TEGRA114_CLK_DFLL_REF, TEGRA114_CLK_PLL_P, 51000000, 1 },
|
||||
{ TEGRA114_CLK_DISP1, TEGRA114_CLK_PLL_P, 0, 0 },
|
||||
{ TEGRA114_CLK_DISP2, TEGRA114_CLK_PLL_P, 0, 0 },
|
||||
{ TEGRA114_CLK_GR2D, TEGRA114_CLK_PLL_C2, 300000000, 0 },
|
||||
{ TEGRA114_CLK_GR3D, TEGRA114_CLK_PLL_C2, 300000000, 0 },
|
||||
{ TEGRA114_CLK_DSIALP, TEGRA114_CLK_PLL_P, 68000000, 0 },
|
||||
{ TEGRA114_CLK_DSIBLP, TEGRA114_CLK_PLL_P, 68000000, 0 },
|
||||
{ TEGRA114_CLK_PLL_RE_VCO, TEGRA114_CLK_CLK_MAX, 612000000, 0 },
|
||||
{ TEGRA114_CLK_XUSB_SS_SRC, TEGRA114_CLK_PLL_RE_OUT, 122400000, 0 },
|
||||
{ TEGRA114_CLK_XUSB_FS_SRC, TEGRA114_CLK_PLL_U_48M, 48000000, 0 },
|
||||
{ TEGRA114_CLK_XUSB_HS_SRC, TEGRA114_CLK_XUSB_SS_DIV2, 61200000, 0 },
|
||||
{ TEGRA114_CLK_XUSB_FALCON_SRC, TEGRA114_CLK_PLL_P, 204000000, 0 },
|
||||
{ TEGRA114_CLK_XUSB_HOST_SRC, TEGRA114_CLK_PLL_P, 102000000, 0 },
|
||||
/* must be the last entry */
|
||||
{ TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_CLK_MAX, 0, 0 },
|
||||
};
|
||||
|
||||
static void __init tegra114_clock_apply_init_table(void)
|
||||
|
|
|
|||
|
|
@ -150,12 +150,12 @@ static DEFINE_SPINLOCK(emc_lock);
|
|||
|
||||
/* possible OSC frequencies in Hz */
|
||||
static unsigned long tegra124_input_freq[] = {
|
||||
[0] = 13000000,
|
||||
[1] = 16800000,
|
||||
[4] = 19200000,
|
||||
[5] = 38400000,
|
||||
[8] = 12000000,
|
||||
[9] = 48000000,
|
||||
[ 0] = 13000000,
|
||||
[ 1] = 16800000,
|
||||
[ 4] = 19200000,
|
||||
[ 5] = 38400000,
|
||||
[ 8] = 12000000,
|
||||
[ 9] = 48000000,
|
||||
[12] = 26000000,
|
||||
};
|
||||
|
||||
|
|
@ -169,32 +169,32 @@ static struct div_nmp pllxc_nmp = {
|
|||
};
|
||||
|
||||
static struct pdiv_map pllxc_p[] = {
|
||||
{ .pdiv = 1, .hw_val = 0 },
|
||||
{ .pdiv = 2, .hw_val = 1 },
|
||||
{ .pdiv = 3, .hw_val = 2 },
|
||||
{ .pdiv = 4, .hw_val = 3 },
|
||||
{ .pdiv = 5, .hw_val = 4 },
|
||||
{ .pdiv = 6, .hw_val = 5 },
|
||||
{ .pdiv = 8, .hw_val = 6 },
|
||||
{ .pdiv = 10, .hw_val = 7 },
|
||||
{ .pdiv = 12, .hw_val = 8 },
|
||||
{ .pdiv = 16, .hw_val = 9 },
|
||||
{ .pdiv = 1, .hw_val = 0 },
|
||||
{ .pdiv = 2, .hw_val = 1 },
|
||||
{ .pdiv = 3, .hw_val = 2 },
|
||||
{ .pdiv = 4, .hw_val = 3 },
|
||||
{ .pdiv = 5, .hw_val = 4 },
|
||||
{ .pdiv = 6, .hw_val = 5 },
|
||||
{ .pdiv = 8, .hw_val = 6 },
|
||||
{ .pdiv = 10, .hw_val = 7 },
|
||||
{ .pdiv = 12, .hw_val = 8 },
|
||||
{ .pdiv = 16, .hw_val = 9 },
|
||||
{ .pdiv = 12, .hw_val = 10 },
|
||||
{ .pdiv = 16, .hw_val = 11 },
|
||||
{ .pdiv = 20, .hw_val = 12 },
|
||||
{ .pdiv = 24, .hw_val = 13 },
|
||||
{ .pdiv = 32, .hw_val = 14 },
|
||||
{ .pdiv = 0, .hw_val = 0 },
|
||||
{ .pdiv = 0, .hw_val = 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
|
||||
/* 1 GHz */
|
||||
{12000000, 1000000000, 83, 0, 1}, /* actual: 996.0 MHz */
|
||||
{13000000, 1000000000, 76, 0, 1}, /* actual: 988.0 MHz */
|
||||
{16800000, 1000000000, 59, 0, 1}, /* actual: 991.2 MHz */
|
||||
{19200000, 1000000000, 52, 0, 1}, /* actual: 998.4 MHz */
|
||||
{26000000, 1000000000, 76, 1, 1}, /* actual: 988.0 MHz */
|
||||
{0, 0, 0, 0, 0, 0},
|
||||
{ 12000000, 1000000000, 83, 0, 1, 0 }, /* actual: 996.0 MHz */
|
||||
{ 13000000, 1000000000, 76, 0, 1, 0 }, /* actual: 988.0 MHz */
|
||||
{ 16800000, 1000000000, 59, 0, 1, 0 }, /* actual: 991.2 MHz */
|
||||
{ 19200000, 1000000000, 52, 0, 1, 0 }, /* actual: 998.4 MHz */
|
||||
{ 26000000, 1000000000, 76, 1, 1, 0 }, /* actual: 988.0 MHz */
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_params pll_x_params = {
|
||||
|
|
@ -222,13 +222,13 @@ static struct tegra_clk_pll_params pll_x_params = {
|
|||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
|
||||
{ 12000000, 624000000, 104, 1, 2},
|
||||
{ 12000000, 600000000, 100, 1, 2},
|
||||
{ 13000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */
|
||||
{ 16800000, 600000000, 71, 1, 2}, /* actual: 596.4 MHz */
|
||||
{ 19200000, 600000000, 62, 1, 2}, /* actual: 595.2 MHz */
|
||||
{ 26000000, 600000000, 92, 2, 2}, /* actual: 598.0 MHz */
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
{ 12000000, 624000000, 104, 1, 2, 0 },
|
||||
{ 12000000, 600000000, 100, 1, 2, 0 },
|
||||
{ 13000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */
|
||||
{ 16800000, 600000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */
|
||||
{ 19200000, 600000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */
|
||||
{ 26000000, 600000000, 92, 2, 2, 0 }, /* actual: 598.0 MHz */
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_params pll_c_params = {
|
||||
|
|
@ -265,24 +265,24 @@ static struct div_nmp pllcx_nmp = {
|
|||
};
|
||||
|
||||
static struct pdiv_map pllc_p[] = {
|
||||
{ .pdiv = 1, .hw_val = 0 },
|
||||
{ .pdiv = 2, .hw_val = 1 },
|
||||
{ .pdiv = 3, .hw_val = 2 },
|
||||
{ .pdiv = 4, .hw_val = 3 },
|
||||
{ .pdiv = 6, .hw_val = 4 },
|
||||
{ .pdiv = 8, .hw_val = 5 },
|
||||
{ .pdiv = 1, .hw_val = 0 },
|
||||
{ .pdiv = 2, .hw_val = 1 },
|
||||
{ .pdiv = 3, .hw_val = 2 },
|
||||
{ .pdiv = 4, .hw_val = 3 },
|
||||
{ .pdiv = 6, .hw_val = 4 },
|
||||
{ .pdiv = 8, .hw_val = 5 },
|
||||
{ .pdiv = 12, .hw_val = 6 },
|
||||
{ .pdiv = 16, .hw_val = 7 },
|
||||
{ .pdiv = 0, .hw_val = 0 },
|
||||
{ .pdiv = 0, .hw_val = 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = {
|
||||
{12000000, 600000000, 100, 1, 2},
|
||||
{13000000, 600000000, 92, 1, 2}, /* actual: 598.0 MHz */
|
||||
{16800000, 600000000, 71, 1, 2}, /* actual: 596.4 MHz */
|
||||
{19200000, 600000000, 62, 1, 2}, /* actual: 595.2 MHz */
|
||||
{26000000, 600000000, 92, 2, 2}, /* actual: 598.0 MHz */
|
||||
{0, 0, 0, 0, 0, 0},
|
||||
{ 12000000, 600000000, 100, 1, 2, 0 },
|
||||
{ 13000000, 600000000, 92, 1, 2, 0 }, /* actual: 598.0 MHz */
|
||||
{ 16800000, 600000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */
|
||||
{ 19200000, 600000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */
|
||||
{ 26000000, 600000000, 92, 2, 2, 0 }, /* actual: 598.0 MHz */
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_params pll_c2_params = {
|
||||
|
|
@ -339,31 +339,31 @@ static struct div_nmp pllss_nmp = {
|
|||
};
|
||||
|
||||
static struct pdiv_map pll12g_ssd_esd_p[] = {
|
||||
{ .pdiv = 1, .hw_val = 0 },
|
||||
{ .pdiv = 2, .hw_val = 1 },
|
||||
{ .pdiv = 3, .hw_val = 2 },
|
||||
{ .pdiv = 4, .hw_val = 3 },
|
||||
{ .pdiv = 5, .hw_val = 4 },
|
||||
{ .pdiv = 6, .hw_val = 5 },
|
||||
{ .pdiv = 8, .hw_val = 6 },
|
||||
{ .pdiv = 10, .hw_val = 7 },
|
||||
{ .pdiv = 12, .hw_val = 8 },
|
||||
{ .pdiv = 16, .hw_val = 9 },
|
||||
{ .pdiv = 1, .hw_val = 0 },
|
||||
{ .pdiv = 2, .hw_val = 1 },
|
||||
{ .pdiv = 3, .hw_val = 2 },
|
||||
{ .pdiv = 4, .hw_val = 3 },
|
||||
{ .pdiv = 5, .hw_val = 4 },
|
||||
{ .pdiv = 6, .hw_val = 5 },
|
||||
{ .pdiv = 8, .hw_val = 6 },
|
||||
{ .pdiv = 10, .hw_val = 7 },
|
||||
{ .pdiv = 12, .hw_val = 8 },
|
||||
{ .pdiv = 16, .hw_val = 9 },
|
||||
{ .pdiv = 12, .hw_val = 10 },
|
||||
{ .pdiv = 16, .hw_val = 11 },
|
||||
{ .pdiv = 20, .hw_val = 12 },
|
||||
{ .pdiv = 24, .hw_val = 13 },
|
||||
{ .pdiv = 32, .hw_val = 14 },
|
||||
{ .pdiv = 0, .hw_val = 0 },
|
||||
{ .pdiv = 0, .hw_val = 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_c4_freq_table[] = {
|
||||
{ 12000000, 600000000, 100, 1, 1},
|
||||
{ 13000000, 600000000, 92, 1, 1}, /* actual: 598.0 MHz */
|
||||
{ 16800000, 600000000, 71, 1, 1}, /* actual: 596.4 MHz */
|
||||
{ 19200000, 600000000, 62, 1, 1}, /* actual: 595.2 MHz */
|
||||
{ 26000000, 600000000, 92, 2, 1}, /* actual: 598.0 MHz */
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
{ 12000000, 600000000, 100, 1, 1, 0 },
|
||||
{ 13000000, 600000000, 92, 1, 1, 0 }, /* actual: 598.0 MHz */
|
||||
{ 16800000, 600000000, 71, 1, 1, 0 }, /* actual: 596.4 MHz */
|
||||
{ 19200000, 600000000, 62, 1, 1, 0 }, /* actual: 595.2 MHz */
|
||||
{ 26000000, 600000000, 92, 2, 1, 0 }, /* actual: 598.0 MHz */
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_params pll_c4_params = {
|
||||
|
|
@ -395,12 +395,12 @@ static struct pdiv_map pllm_p[] = {
|
|||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
|
||||
{12000000, 800000000, 66, 1, 1}, /* actual: 792.0 MHz */
|
||||
{13000000, 800000000, 61, 1, 1}, /* actual: 793.0 MHz */
|
||||
{16800000, 800000000, 47, 1, 1}, /* actual: 789.6 MHz */
|
||||
{19200000, 800000000, 41, 1, 1}, /* actual: 787.2 MHz */
|
||||
{26000000, 800000000, 61, 2, 1}, /* actual: 793.0 MHz */
|
||||
{0, 0, 0, 0, 0, 0},
|
||||
{ 12000000, 800000000, 66, 1, 1, 0 }, /* actual: 792.0 MHz */
|
||||
{ 13000000, 800000000, 61, 1, 1, 0 }, /* actual: 793.0 MHz */
|
||||
{ 16800000, 800000000, 47, 1, 1, 0 }, /* actual: 789.6 MHz */
|
||||
{ 19200000, 800000000, 41, 1, 1, 0 }, /* actual: 787.2 MHz */
|
||||
{ 26000000, 800000000, 61, 2, 1, 0 }, /* actual: 793.0 MHz */
|
||||
{ 0, 0, 0, 0, 0, 0},
|
||||
};
|
||||
|
||||
static struct div_nmp pllm_nmp = {
|
||||
|
|
@ -438,11 +438,11 @@ static struct tegra_clk_pll_params pll_m_params = {
|
|||
|
||||
static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
|
||||
/* PLLE special case: use cpcon field to store cml divider value */
|
||||
{336000000, 100000000, 100, 21, 16, 11},
|
||||
{312000000, 100000000, 200, 26, 24, 13},
|
||||
{13000000, 100000000, 200, 1, 26, 13},
|
||||
{12000000, 100000000, 200, 1, 24, 13},
|
||||
{0, 0, 0, 0, 0, 0},
|
||||
{ 336000000, 100000000, 100, 21, 16, 11 },
|
||||
{ 312000000, 100000000, 200, 26, 24, 13 },
|
||||
{ 13000000, 100000000, 200, 1, 26, 13 },
|
||||
{ 12000000, 100000000, 200, 1, 24, 13 },
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct div_nmp plle_nmp = {
|
||||
|
|
@ -520,12 +520,12 @@ static struct div_nmp pllp_nmp = {
|
|||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
|
||||
{12000000, 408000000, 408, 12, 0, 8},
|
||||
{13000000, 408000000, 408, 13, 0, 8},
|
||||
{16800000, 408000000, 340, 14, 0, 8},
|
||||
{19200000, 408000000, 340, 16, 0, 8},
|
||||
{26000000, 408000000, 408, 26, 0, 8},
|
||||
{0, 0, 0, 0, 0, 0},
|
||||
{ 12000000, 408000000, 408, 12, 0, 8 },
|
||||
{ 13000000, 408000000, 408, 13, 0, 8 },
|
||||
{ 16800000, 408000000, 340, 14, 0, 8 },
|
||||
{ 19200000, 408000000, 340, 16, 0, 8 },
|
||||
{ 26000000, 408000000, 408, 26, 0, 8 },
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_params pll_p_params = {
|
||||
|
|
@ -547,14 +547,13 @@ static struct tegra_clk_pll_params pll_p_params = {
|
|||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
|
||||
{9600000, 282240000, 147, 5, 0, 4},
|
||||
{9600000, 368640000, 192, 5, 0, 4},
|
||||
{9600000, 240000000, 200, 8, 0, 8},
|
||||
|
||||
{28800000, 282240000, 245, 25, 0, 8},
|
||||
{28800000, 368640000, 320, 25, 0, 8},
|
||||
{28800000, 240000000, 200, 24, 0, 8},
|
||||
{0, 0, 0, 0, 0, 0},
|
||||
{ 9600000, 282240000, 147, 5, 0, 4 },
|
||||
{ 9600000, 368640000, 192, 5, 0, 4 },
|
||||
{ 9600000, 240000000, 200, 8, 0, 8 },
|
||||
{ 28800000, 282240000, 245, 25, 0, 8 },
|
||||
{ 28800000, 368640000, 320, 25, 0, 8 },
|
||||
{ 28800000, 240000000, 200, 24, 0, 8 },
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_params pll_a_params = {
|
||||
|
|
@ -584,24 +583,21 @@ static struct div_nmp plld_nmp = {
|
|||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
|
||||
{12000000, 216000000, 864, 12, 4, 12},
|
||||
{13000000, 216000000, 864, 13, 4, 12},
|
||||
{16800000, 216000000, 720, 14, 4, 12},
|
||||
{19200000, 216000000, 720, 16, 4, 12},
|
||||
{26000000, 216000000, 864, 26, 4, 12},
|
||||
|
||||
{12000000, 594000000, 594, 12, 1, 12},
|
||||
{13000000, 594000000, 594, 13, 1, 12},
|
||||
{16800000, 594000000, 495, 14, 1, 12},
|
||||
{19200000, 594000000, 495, 16, 1, 12},
|
||||
{26000000, 594000000, 594, 26, 1, 12},
|
||||
|
||||
{12000000, 1000000000, 1000, 12, 1, 12},
|
||||
{13000000, 1000000000, 1000, 13, 1, 12},
|
||||
{19200000, 1000000000, 625, 12, 1, 12},
|
||||
{26000000, 1000000000, 1000, 26, 1, 12},
|
||||
|
||||
{0, 0, 0, 0, 0, 0},
|
||||
{ 12000000, 216000000, 864, 12, 4, 12 },
|
||||
{ 13000000, 216000000, 864, 13, 4, 12 },
|
||||
{ 16800000, 216000000, 720, 14, 4, 12 },
|
||||
{ 19200000, 216000000, 720, 16, 4, 12 },
|
||||
{ 26000000, 216000000, 864, 26, 4, 12 },
|
||||
{ 12000000, 594000000, 594, 12, 1, 12 },
|
||||
{ 13000000, 594000000, 594, 13, 1, 12 },
|
||||
{ 16800000, 594000000, 495, 14, 1, 12 },
|
||||
{ 19200000, 594000000, 495, 16, 1, 12 },
|
||||
{ 26000000, 594000000, 594, 26, 1, 12 },
|
||||
{ 12000000, 1000000000, 1000, 12, 1, 12 },
|
||||
{ 13000000, 1000000000, 1000, 13, 1, 12 },
|
||||
{ 19200000, 1000000000, 625, 12, 1, 12 },
|
||||
{ 26000000, 1000000000, 1000, 26, 1, 12 },
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_params pll_d_params = {
|
||||
|
|
@ -623,12 +619,12 @@ static struct tegra_clk_pll_params pll_d_params = {
|
|||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table tegra124_pll_d2_freq_table[] = {
|
||||
{ 12000000, 594000000, 99, 1, 2},
|
||||
{ 13000000, 594000000, 91, 1, 2}, /* actual: 591.5 MHz */
|
||||
{ 16800000, 594000000, 71, 1, 2}, /* actual: 596.4 MHz */
|
||||
{ 19200000, 594000000, 62, 1, 2}, /* actual: 595.2 MHz */
|
||||
{ 26000000, 594000000, 91, 2, 2}, /* actual: 591.5 MHz */
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
{ 12000000, 594000000, 99, 1, 2, 0 },
|
||||
{ 13000000, 594000000, 91, 1, 2, 0 }, /* actual: 591.5 MHz */
|
||||
{ 16800000, 594000000, 71, 1, 2, 0 }, /* actual: 596.4 MHz */
|
||||
{ 19200000, 594000000, 62, 1, 2, 0 }, /* actual: 595.2 MHz */
|
||||
{ 26000000, 594000000, 91, 2, 2, 0 }, /* actual: 591.5 MHz */
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_params tegra124_pll_d2_params = {
|
||||
|
|
@ -655,12 +651,12 @@ static struct tegra_clk_pll_params tegra124_pll_d2_params = {
|
|||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_dp_freq_table[] = {
|
||||
{ 12000000, 600000000, 100, 1, 1},
|
||||
{ 13000000, 600000000, 92, 1, 1}, /* actual: 598.0 MHz */
|
||||
{ 16800000, 600000000, 71, 1, 1}, /* actual: 596.4 MHz */
|
||||
{ 19200000, 600000000, 62, 1, 1}, /* actual: 595.2 MHz */
|
||||
{ 26000000, 600000000, 92, 2, 1}, /* actual: 598.0 MHz */
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
{ 12000000, 600000000, 100, 1, 1, 0 },
|
||||
{ 13000000, 600000000, 92, 1, 1, 0 }, /* actual: 598.0 MHz */
|
||||
{ 16800000, 600000000, 71, 1, 1, 0 }, /* actual: 596.4 MHz */
|
||||
{ 19200000, 600000000, 62, 1, 1, 0 }, /* actual: 595.2 MHz */
|
||||
{ 26000000, 600000000, 92, 2, 1, 0 }, /* actual: 598.0 MHz */
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_params pll_dp_params = {
|
||||
|
|
@ -702,12 +698,12 @@ static struct div_nmp pllu_nmp = {
|
|||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
|
||||
{12000000, 480000000, 960, 12, 2, 12},
|
||||
{13000000, 480000000, 960, 13, 2, 12},
|
||||
{16800000, 480000000, 400, 7, 2, 5},
|
||||
{19200000, 480000000, 200, 4, 2, 3},
|
||||
{26000000, 480000000, 960, 26, 2, 12},
|
||||
{0, 0, 0, 0, 0, 0},
|
||||
{ 12000000, 480000000, 960, 12, 2, 12 },
|
||||
{ 13000000, 480000000, 960, 13, 2, 12 },
|
||||
{ 16800000, 480000000, 400, 7, 2, 5 },
|
||||
{ 19200000, 480000000, 200, 4, 2, 3 },
|
||||
{ 26000000, 480000000, 960, 26, 2, 12 },
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_params pll_u_params = {
|
||||
|
|
@ -743,21 +739,27 @@ struct utmi_clk_param {
|
|||
};
|
||||
|
||||
static const struct utmi_clk_param utmi_parameters[] = {
|
||||
{.osc_frequency = 13000000, .enable_delay_count = 0x02,
|
||||
.stable_count = 0x33, .active_delay_count = 0x05,
|
||||
.xtal_freq_count = 0x7F},
|
||||
{.osc_frequency = 19200000, .enable_delay_count = 0x03,
|
||||
.stable_count = 0x4B, .active_delay_count = 0x06,
|
||||
.xtal_freq_count = 0xBB},
|
||||
{.osc_frequency = 12000000, .enable_delay_count = 0x02,
|
||||
.stable_count = 0x2F, .active_delay_count = 0x04,
|
||||
.xtal_freq_count = 0x76},
|
||||
{.osc_frequency = 26000000, .enable_delay_count = 0x04,
|
||||
.stable_count = 0x66, .active_delay_count = 0x09,
|
||||
.xtal_freq_count = 0xFE},
|
||||
{.osc_frequency = 16800000, .enable_delay_count = 0x03,
|
||||
.stable_count = 0x41, .active_delay_count = 0x0A,
|
||||
.xtal_freq_count = 0xA4},
|
||||
{
|
||||
.osc_frequency = 13000000, .enable_delay_count = 0x02,
|
||||
.stable_count = 0x33, .active_delay_count = 0x05,
|
||||
.xtal_freq_count = 0x7f
|
||||
}, {
|
||||
.osc_frequency = 19200000, .enable_delay_count = 0x03,
|
||||
.stable_count = 0x4b, .active_delay_count = 0x06,
|
||||
.xtal_freq_count = 0xbb
|
||||
}, {
|
||||
.osc_frequency = 12000000, .enable_delay_count = 0x02,
|
||||
.stable_count = 0x2f, .active_delay_count = 0x04,
|
||||
.xtal_freq_count = 0x76
|
||||
}, {
|
||||
.osc_frequency = 26000000, .enable_delay_count = 0x04,
|
||||
.stable_count = 0x66, .active_delay_count = 0x09,
|
||||
.xtal_freq_count = 0xfe
|
||||
}, {
|
||||
.osc_frequency = 16800000, .enable_delay_count = 0x03,
|
||||
.stable_count = 0x41, .active_delay_count = 0x0a,
|
||||
.xtal_freq_count = 0xa4
|
||||
},
|
||||
};
|
||||
|
||||
static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
|
||||
|
|
@ -1360,61 +1362,61 @@ static const struct of_device_id pmc_match[] __initconst = {
|
|||
};
|
||||
|
||||
static struct tegra_clk_init_table common_init_table[] __initdata = {
|
||||
{TEGRA124_CLK_UARTA, TEGRA124_CLK_PLL_P, 408000000, 0},
|
||||
{TEGRA124_CLK_UARTB, TEGRA124_CLK_PLL_P, 408000000, 0},
|
||||
{TEGRA124_CLK_UARTC, TEGRA124_CLK_PLL_P, 408000000, 0},
|
||||
{TEGRA124_CLK_UARTD, TEGRA124_CLK_PLL_P, 408000000, 0},
|
||||
{TEGRA124_CLK_PLL_A, TEGRA124_CLK_CLK_MAX, 564480000, 1},
|
||||
{TEGRA124_CLK_PLL_A_OUT0, TEGRA124_CLK_CLK_MAX, 11289600, 1},
|
||||
{TEGRA124_CLK_EXTERN1, TEGRA124_CLK_PLL_A_OUT0, 0, 1},
|
||||
{TEGRA124_CLK_CLK_OUT_1_MUX, TEGRA124_CLK_EXTERN1, 0, 1},
|
||||
{TEGRA124_CLK_CLK_OUT_1, TEGRA124_CLK_CLK_MAX, 0, 1},
|
||||
{TEGRA124_CLK_I2S0, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0},
|
||||
{TEGRA124_CLK_I2S1, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0},
|
||||
{TEGRA124_CLK_I2S2, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0},
|
||||
{TEGRA124_CLK_I2S3, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0},
|
||||
{TEGRA124_CLK_I2S4, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0},
|
||||
{TEGRA124_CLK_VDE, TEGRA124_CLK_PLL_P, 0, 0},
|
||||
{TEGRA124_CLK_HOST1X, TEGRA124_CLK_PLL_P, 136000000, 1},
|
||||
{TEGRA124_CLK_DSIALP, TEGRA124_CLK_PLL_P, 68000000, 0},
|
||||
{TEGRA124_CLK_DSIBLP, TEGRA124_CLK_PLL_P, 68000000, 0},
|
||||
{TEGRA124_CLK_SCLK, TEGRA124_CLK_PLL_P_OUT2, 102000000, 1},
|
||||
{TEGRA124_CLK_DFLL_SOC, TEGRA124_CLK_PLL_P, 51000000, 1},
|
||||
{TEGRA124_CLK_DFLL_REF, TEGRA124_CLK_PLL_P, 51000000, 1},
|
||||
{TEGRA124_CLK_PLL_C, TEGRA124_CLK_CLK_MAX, 768000000, 0},
|
||||
{TEGRA124_CLK_PLL_C_OUT1, TEGRA124_CLK_CLK_MAX, 100000000, 0},
|
||||
{TEGRA124_CLK_SBC4, TEGRA124_CLK_PLL_P, 12000000, 1},
|
||||
{TEGRA124_CLK_TSEC, TEGRA124_CLK_PLL_C3, 0, 0},
|
||||
{TEGRA124_CLK_MSENC, TEGRA124_CLK_PLL_C3, 0, 0},
|
||||
{TEGRA124_CLK_PLL_RE_VCO, TEGRA124_CLK_CLK_MAX, 672000000, 0},
|
||||
{TEGRA124_CLK_XUSB_SS_SRC, TEGRA124_CLK_PLL_U_480M, 120000000, 0},
|
||||
{TEGRA124_CLK_XUSB_FS_SRC, TEGRA124_CLK_PLL_U_48M, 48000000, 0},
|
||||
{TEGRA124_CLK_XUSB_HS_SRC, TEGRA124_CLK_PLL_U_60M, 60000000, 0},
|
||||
{TEGRA124_CLK_XUSB_FALCON_SRC, TEGRA124_CLK_PLL_RE_OUT, 224000000, 0},
|
||||
{TEGRA124_CLK_XUSB_HOST_SRC, TEGRA124_CLK_PLL_RE_OUT, 112000000, 0},
|
||||
{TEGRA124_CLK_SATA, TEGRA124_CLK_PLL_P, 104000000, 0},
|
||||
{TEGRA124_CLK_SATA_OOB, TEGRA124_CLK_PLL_P, 204000000, 0},
|
||||
{TEGRA124_CLK_MSELECT, TEGRA124_CLK_CLK_MAX, 0, 1},
|
||||
{TEGRA124_CLK_CSITE, TEGRA124_CLK_CLK_MAX, 0, 1},
|
||||
{TEGRA124_CLK_TSENSOR, TEGRA124_CLK_CLK_M, 400000, 0},
|
||||
/* This MUST be the last entry. */
|
||||
{TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0},
|
||||
{ TEGRA124_CLK_UARTA, TEGRA124_CLK_PLL_P, 408000000, 0 },
|
||||
{ TEGRA124_CLK_UARTB, TEGRA124_CLK_PLL_P, 408000000, 0 },
|
||||
{ TEGRA124_CLK_UARTC, TEGRA124_CLK_PLL_P, 408000000, 0 },
|
||||
{ TEGRA124_CLK_UARTD, TEGRA124_CLK_PLL_P, 408000000, 0 },
|
||||
{ TEGRA124_CLK_PLL_A, TEGRA124_CLK_CLK_MAX, 564480000, 1 },
|
||||
{ TEGRA124_CLK_PLL_A_OUT0, TEGRA124_CLK_CLK_MAX, 11289600, 1 },
|
||||
{ TEGRA124_CLK_EXTERN1, TEGRA124_CLK_PLL_A_OUT0, 0, 1 },
|
||||
{ TEGRA124_CLK_CLK_OUT_1_MUX, TEGRA124_CLK_EXTERN1, 0, 1 },
|
||||
{ TEGRA124_CLK_CLK_OUT_1, TEGRA124_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA124_CLK_I2S0, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA124_CLK_I2S1, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA124_CLK_I2S2, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA124_CLK_I2S3, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA124_CLK_I2S4, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA124_CLK_VDE, TEGRA124_CLK_PLL_P, 0, 0 },
|
||||
{ TEGRA124_CLK_HOST1X, TEGRA124_CLK_PLL_P, 136000000, 1 },
|
||||
{ TEGRA124_CLK_DSIALP, TEGRA124_CLK_PLL_P, 68000000, 0 },
|
||||
{ TEGRA124_CLK_DSIBLP, TEGRA124_CLK_PLL_P, 68000000, 0 },
|
||||
{ TEGRA124_CLK_SCLK, TEGRA124_CLK_PLL_P_OUT2, 102000000, 1 },
|
||||
{ TEGRA124_CLK_DFLL_SOC, TEGRA124_CLK_PLL_P, 51000000, 1 },
|
||||
{ TEGRA124_CLK_DFLL_REF, TEGRA124_CLK_PLL_P, 51000000, 1 },
|
||||
{ TEGRA124_CLK_PLL_C, TEGRA124_CLK_CLK_MAX, 768000000, 0 },
|
||||
{ TEGRA124_CLK_PLL_C_OUT1, TEGRA124_CLK_CLK_MAX, 100000000, 0 },
|
||||
{ TEGRA124_CLK_SBC4, TEGRA124_CLK_PLL_P, 12000000, 1 },
|
||||
{ TEGRA124_CLK_TSEC, TEGRA124_CLK_PLL_C3, 0, 0 },
|
||||
{ TEGRA124_CLK_MSENC, TEGRA124_CLK_PLL_C3, 0, 0 },
|
||||
{ TEGRA124_CLK_PLL_RE_VCO, TEGRA124_CLK_CLK_MAX, 672000000, 0 },
|
||||
{ TEGRA124_CLK_XUSB_SS_SRC, TEGRA124_CLK_PLL_U_480M, 120000000, 0 },
|
||||
{ TEGRA124_CLK_XUSB_FS_SRC, TEGRA124_CLK_PLL_U_48M, 48000000, 0 },
|
||||
{ TEGRA124_CLK_XUSB_HS_SRC, TEGRA124_CLK_PLL_U_60M, 60000000, 0 },
|
||||
{ TEGRA124_CLK_XUSB_FALCON_SRC, TEGRA124_CLK_PLL_RE_OUT, 224000000, 0 },
|
||||
{ TEGRA124_CLK_XUSB_HOST_SRC, TEGRA124_CLK_PLL_RE_OUT, 112000000, 0 },
|
||||
{ TEGRA124_CLK_SATA, TEGRA124_CLK_PLL_P, 104000000, 0 },
|
||||
{ TEGRA124_CLK_SATA_OOB, TEGRA124_CLK_PLL_P, 204000000, 0 },
|
||||
{ TEGRA124_CLK_MSELECT, TEGRA124_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA124_CLK_CSITE, TEGRA124_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA124_CLK_TSENSOR, TEGRA124_CLK_CLK_M, 400000, 0 },
|
||||
/* must be the last entry */
|
||||
{ TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_init_table tegra124_init_table[] __initdata = {
|
||||
{TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 0},
|
||||
{TEGRA124_CLK_CCLK_G, TEGRA124_CLK_CLK_MAX, 0, 1},
|
||||
{TEGRA124_CLK_HDA, TEGRA124_CLK_PLL_P, 102000000, 0},
|
||||
{TEGRA124_CLK_HDA2CODEC_2X, TEGRA124_CLK_PLL_P, 48000000, 0},
|
||||
/* This MUST be the last entry. */
|
||||
{TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0},
|
||||
{ TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 0 },
|
||||
{ TEGRA124_CLK_CCLK_G, TEGRA124_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA124_CLK_HDA, TEGRA124_CLK_PLL_P, 102000000, 0 },
|
||||
{ TEGRA124_CLK_HDA2CODEC_2X, TEGRA124_CLK_PLL_P, 48000000, 0 },
|
||||
/* must be the last entry */
|
||||
{ TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 },
|
||||
};
|
||||
|
||||
/* Tegra132 requires the SOC_THERM clock to remain active */
|
||||
static struct tegra_clk_init_table tegra132_init_table[] __initdata = {
|
||||
{TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 1},
|
||||
/* This MUST be the last entry. */
|
||||
{TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0},
|
||||
{ TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 1 },
|
||||
/* must be the last entry */
|
||||
{ TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_audio_clk_info tegra124_audio_plls[] = {
|
||||
|
|
|
|||
|
|
@ -170,122 +170,111 @@ static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
|
|||
{ 13000000, 600000000, 600, 13, 0, 8 },
|
||||
{ 19200000, 600000000, 500, 16, 0, 6 },
|
||||
{ 26000000, 600000000, 600, 26, 0, 8 },
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
|
||||
{ 12000000, 666000000, 666, 12, 0, 8},
|
||||
{ 13000000, 666000000, 666, 13, 0, 8},
|
||||
{ 19200000, 666000000, 555, 16, 0, 8},
|
||||
{ 26000000, 666000000, 666, 26, 0, 8},
|
||||
{ 12000000, 600000000, 600, 12, 0, 8},
|
||||
{ 13000000, 600000000, 600, 13, 0, 8},
|
||||
{ 19200000, 600000000, 375, 12, 0, 6},
|
||||
{ 26000000, 600000000, 600, 26, 0, 8},
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
{ 12000000, 666000000, 666, 12, 0, 8 },
|
||||
{ 13000000, 666000000, 666, 13, 0, 8 },
|
||||
{ 19200000, 666000000, 555, 16, 0, 8 },
|
||||
{ 26000000, 666000000, 666, 26, 0, 8 },
|
||||
{ 12000000, 600000000, 600, 12, 0, 8 },
|
||||
{ 13000000, 600000000, 600, 13, 0, 8 },
|
||||
{ 19200000, 600000000, 375, 12, 0, 6 },
|
||||
{ 26000000, 600000000, 600, 26, 0, 8 },
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
|
||||
{ 12000000, 216000000, 432, 12, 1, 8},
|
||||
{ 13000000, 216000000, 432, 13, 1, 8},
|
||||
{ 19200000, 216000000, 90, 4, 1, 1},
|
||||
{ 26000000, 216000000, 432, 26, 1, 8},
|
||||
{ 12000000, 432000000, 432, 12, 0, 8},
|
||||
{ 13000000, 432000000, 432, 13, 0, 8},
|
||||
{ 19200000, 432000000, 90, 4, 0, 1},
|
||||
{ 26000000, 432000000, 432, 26, 0, 8},
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
{ 12000000, 216000000, 432, 12, 1, 8 },
|
||||
{ 13000000, 216000000, 432, 13, 1, 8 },
|
||||
{ 19200000, 216000000, 90, 4, 1, 1 },
|
||||
{ 26000000, 216000000, 432, 26, 1, 8 },
|
||||
{ 12000000, 432000000, 432, 12, 0, 8 },
|
||||
{ 13000000, 432000000, 432, 13, 0, 8 },
|
||||
{ 19200000, 432000000, 90, 4, 0, 1 },
|
||||
{ 26000000, 432000000, 432, 26, 0, 8 },
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
|
||||
{ 28800000, 56448000, 49, 25, 0, 1},
|
||||
{ 28800000, 73728000, 64, 25, 0, 1},
|
||||
{ 28800000, 24000000, 5, 6, 0, 1},
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
{ 28800000, 56448000, 49, 25, 0, 1 },
|
||||
{ 28800000, 73728000, 64, 25, 0, 1 },
|
||||
{ 28800000, 24000000, 5, 6, 0, 1 },
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
|
||||
{ 12000000, 216000000, 216, 12, 0, 4},
|
||||
{ 13000000, 216000000, 216, 13, 0, 4},
|
||||
{ 19200000, 216000000, 135, 12, 0, 3},
|
||||
{ 26000000, 216000000, 216, 26, 0, 4},
|
||||
|
||||
{ 12000000, 594000000, 594, 12, 0, 8},
|
||||
{ 13000000, 594000000, 594, 13, 0, 8},
|
||||
{ 19200000, 594000000, 495, 16, 0, 8},
|
||||
{ 26000000, 594000000, 594, 26, 0, 8},
|
||||
|
||||
{ 12000000, 1000000000, 1000, 12, 0, 12},
|
||||
{ 13000000, 1000000000, 1000, 13, 0, 12},
|
||||
{ 19200000, 1000000000, 625, 12, 0, 8},
|
||||
{ 26000000, 1000000000, 1000, 26, 0, 12},
|
||||
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
{ 12000000, 216000000, 216, 12, 0, 4 },
|
||||
{ 13000000, 216000000, 216, 13, 0, 4 },
|
||||
{ 19200000, 216000000, 135, 12, 0, 3 },
|
||||
{ 26000000, 216000000, 216, 26, 0, 4 },
|
||||
{ 12000000, 594000000, 594, 12, 0, 8 },
|
||||
{ 13000000, 594000000, 594, 13, 0, 8 },
|
||||
{ 19200000, 594000000, 495, 16, 0, 8 },
|
||||
{ 26000000, 594000000, 594, 26, 0, 8 },
|
||||
{ 12000000, 1000000000, 1000, 12, 0, 12 },
|
||||
{ 13000000, 1000000000, 1000, 13, 0, 12 },
|
||||
{ 19200000, 1000000000, 625, 12, 0, 8 },
|
||||
{ 26000000, 1000000000, 1000, 26, 0, 12 },
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
|
||||
{ 12000000, 480000000, 960, 12, 0, 0},
|
||||
{ 13000000, 480000000, 960, 13, 0, 0},
|
||||
{ 19200000, 480000000, 200, 4, 0, 0},
|
||||
{ 26000000, 480000000, 960, 26, 0, 0},
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
{ 12000000, 480000000, 960, 12, 0, 0 },
|
||||
{ 13000000, 480000000, 960, 13, 0, 0 },
|
||||
{ 19200000, 480000000, 200, 4, 0, 0 },
|
||||
{ 26000000, 480000000, 960, 26, 0, 0 },
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
|
||||
/* 1 GHz */
|
||||
{ 12000000, 1000000000, 1000, 12, 0, 12},
|
||||
{ 13000000, 1000000000, 1000, 13, 0, 12},
|
||||
{ 19200000, 1000000000, 625, 12, 0, 8},
|
||||
{ 26000000, 1000000000, 1000, 26, 0, 12},
|
||||
|
||||
{ 12000000, 1000000000, 1000, 12, 0, 12 },
|
||||
{ 13000000, 1000000000, 1000, 13, 0, 12 },
|
||||
{ 19200000, 1000000000, 625, 12, 0, 8 },
|
||||
{ 26000000, 1000000000, 1000, 26, 0, 12 },
|
||||
/* 912 MHz */
|
||||
{ 12000000, 912000000, 912, 12, 0, 12},
|
||||
{ 13000000, 912000000, 912, 13, 0, 12},
|
||||
{ 19200000, 912000000, 760, 16, 0, 8},
|
||||
{ 26000000, 912000000, 912, 26, 0, 12},
|
||||
|
||||
{ 12000000, 912000000, 912, 12, 0, 12 },
|
||||
{ 13000000, 912000000, 912, 13, 0, 12 },
|
||||
{ 19200000, 912000000, 760, 16, 0, 8 },
|
||||
{ 26000000, 912000000, 912, 26, 0, 12 },
|
||||
/* 816 MHz */
|
||||
{ 12000000, 816000000, 816, 12, 0, 12},
|
||||
{ 13000000, 816000000, 816, 13, 0, 12},
|
||||
{ 19200000, 816000000, 680, 16, 0, 8},
|
||||
{ 26000000, 816000000, 816, 26, 0, 12},
|
||||
|
||||
{ 12000000, 816000000, 816, 12, 0, 12 },
|
||||
{ 13000000, 816000000, 816, 13, 0, 12 },
|
||||
{ 19200000, 816000000, 680, 16, 0, 8 },
|
||||
{ 26000000, 816000000, 816, 26, 0, 12 },
|
||||
/* 760 MHz */
|
||||
{ 12000000, 760000000, 760, 12, 0, 12},
|
||||
{ 13000000, 760000000, 760, 13, 0, 12},
|
||||
{ 19200000, 760000000, 950, 24, 0, 8},
|
||||
{ 26000000, 760000000, 760, 26, 0, 12},
|
||||
|
||||
{ 12000000, 760000000, 760, 12, 0, 12 },
|
||||
{ 13000000, 760000000, 760, 13, 0, 12 },
|
||||
{ 19200000, 760000000, 950, 24, 0, 8 },
|
||||
{ 26000000, 760000000, 760, 26, 0, 12 },
|
||||
/* 750 MHz */
|
||||
{ 12000000, 750000000, 750, 12, 0, 12},
|
||||
{ 13000000, 750000000, 750, 13, 0, 12},
|
||||
{ 19200000, 750000000, 625, 16, 0, 8},
|
||||
{ 26000000, 750000000, 750, 26, 0, 12},
|
||||
|
||||
{ 12000000, 750000000, 750, 12, 0, 12 },
|
||||
{ 13000000, 750000000, 750, 13, 0, 12 },
|
||||
{ 19200000, 750000000, 625, 16, 0, 8 },
|
||||
{ 26000000, 750000000, 750, 26, 0, 12 },
|
||||
/* 608 MHz */
|
||||
{ 12000000, 608000000, 608, 12, 0, 12},
|
||||
{ 13000000, 608000000, 608, 13, 0, 12},
|
||||
{ 19200000, 608000000, 380, 12, 0, 8},
|
||||
{ 26000000, 608000000, 608, 26, 0, 12},
|
||||
|
||||
{ 12000000, 608000000, 608, 12, 0, 12 },
|
||||
{ 13000000, 608000000, 608, 13, 0, 12 },
|
||||
{ 19200000, 608000000, 380, 12, 0, 8 },
|
||||
{ 26000000, 608000000, 608, 26, 0, 12 },
|
||||
/* 456 MHz */
|
||||
{ 12000000, 456000000, 456, 12, 0, 12},
|
||||
{ 13000000, 456000000, 456, 13, 0, 12},
|
||||
{ 19200000, 456000000, 380, 16, 0, 8},
|
||||
{ 26000000, 456000000, 456, 26, 0, 12},
|
||||
|
||||
{ 12000000, 456000000, 456, 12, 0, 12 },
|
||||
{ 13000000, 456000000, 456, 13, 0, 12 },
|
||||
{ 19200000, 456000000, 380, 16, 0, 8 },
|
||||
{ 26000000, 456000000, 456, 26, 0, 12 },
|
||||
/* 312 MHz */
|
||||
{ 12000000, 312000000, 312, 12, 0, 12},
|
||||
{ 13000000, 312000000, 312, 13, 0, 12},
|
||||
{ 19200000, 312000000, 260, 16, 0, 8},
|
||||
{ 26000000, 312000000, 312, 26, 0, 12},
|
||||
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
{ 12000000, 312000000, 312, 12, 0, 12 },
|
||||
{ 13000000, 312000000, 312, 13, 0, 12 },
|
||||
{ 19200000, 312000000, 260, 16, 0, 8 },
|
||||
{ 26000000, 312000000, 312, 26, 0, 12 },
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
|
||||
{ 12000000, 100000000, 200, 24, 0, 0 },
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
{ 12000000, 100000000, 200, 24, 0, 0 },
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
/* PLL parameters */
|
||||
|
|
@ -733,9 +722,9 @@ static void tegra20_super_clk_init(void)
|
|||
clks[TEGRA20_CLK_TWD] = clk;
|
||||
}
|
||||
|
||||
static const char *audio_parents[] = {"spdif_in", "i2s1", "i2s2", "unused",
|
||||
"pll_a_out0", "unused", "unused",
|
||||
"unused"};
|
||||
static const char *audio_parents[] = { "spdif_in", "i2s1", "i2s2", "unused",
|
||||
"pll_a_out0", "unused", "unused",
|
||||
"unused" };
|
||||
|
||||
static void __init tegra20_audio_clk_init(void)
|
||||
{
|
||||
|
|
@ -761,16 +750,16 @@ static void __init tegra20_audio_clk_init(void)
|
|||
clks[TEGRA20_CLK_AUDIO_2X] = clk;
|
||||
}
|
||||
|
||||
static const char *i2s1_parents[] = {"pll_a_out0", "audio_2x", "pll_p",
|
||||
"clk_m"};
|
||||
static const char *i2s2_parents[] = {"pll_a_out0", "audio_2x", "pll_p",
|
||||
"clk_m"};
|
||||
static const char *pwm_parents[] = {"pll_p", "pll_c", "audio", "clk_m",
|
||||
"clk_32k"};
|
||||
static const char *mux_pllpcm_clkm[] = {"pll_p", "pll_c", "pll_m", "clk_m"};
|
||||
static const char *mux_pllpdc_clkm[] = {"pll_p", "pll_d_out0", "pll_c",
|
||||
"clk_m"};
|
||||
static const char *mux_pllmcp_clkm[] = {"pll_m", "pll_c", "pll_p", "clk_m"};
|
||||
static const char *i2s1_parents[] = { "pll_a_out0", "audio_2x", "pll_p",
|
||||
"clk_m" };
|
||||
static const char *i2s2_parents[] = { "pll_a_out0", "audio_2x", "pll_p",
|
||||
"clk_m" };
|
||||
static const char *pwm_parents[] = { "pll_p", "pll_c", "audio", "clk_m",
|
||||
"clk_32k" };
|
||||
static const char *mux_pllpcm_clkm[] = { "pll_p", "pll_c", "pll_m", "clk_m" };
|
||||
static const char *mux_pllpdc_clkm[] = { "pll_p", "pll_d_out0", "pll_c",
|
||||
"clk_m" };
|
||||
static const char *mux_pllmcp_clkm[] = { "pll_m", "pll_c", "pll_p", "clk_m" };
|
||||
|
||||
static struct tegra_periph_init_data tegra_periph_clk_list[] = {
|
||||
TEGRA_INIT_DATA_MUX("i2s1", i2s1_parents, CLK_SOURCE_I2S1, 11, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2S1),
|
||||
|
|
@ -1024,44 +1013,45 @@ static struct tegra_cpu_car_ops tegra20_cpu_car_ops = {
|
|||
};
|
||||
|
||||
static struct tegra_clk_init_table init_table[] __initdata = {
|
||||
{TEGRA20_CLK_PLL_P, TEGRA20_CLK_CLK_MAX, 216000000, 1},
|
||||
{TEGRA20_CLK_PLL_P_OUT1, TEGRA20_CLK_CLK_MAX, 28800000, 1},
|
||||
{TEGRA20_CLK_PLL_P_OUT2, TEGRA20_CLK_CLK_MAX, 48000000, 1},
|
||||
{TEGRA20_CLK_PLL_P_OUT3, TEGRA20_CLK_CLK_MAX, 72000000, 1},
|
||||
{TEGRA20_CLK_PLL_P_OUT4, TEGRA20_CLK_CLK_MAX, 24000000, 1},
|
||||
{TEGRA20_CLK_PLL_C, TEGRA20_CLK_CLK_MAX, 600000000, 1},
|
||||
{TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 120000000, 1},
|
||||
{TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 0, 1},
|
||||
{TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 0, 1},
|
||||
{TEGRA20_CLK_PCLK, TEGRA20_CLK_CLK_MAX, 60000000, 1},
|
||||
{TEGRA20_CLK_CSITE, TEGRA20_CLK_CLK_MAX, 0, 1},
|
||||
{TEGRA20_CLK_EMC, TEGRA20_CLK_CLK_MAX, 0, 1},
|
||||
{TEGRA20_CLK_CCLK, TEGRA20_CLK_CLK_MAX, 0, 1},
|
||||
{TEGRA20_CLK_UARTA, TEGRA20_CLK_PLL_P, 0, 0},
|
||||
{TEGRA20_CLK_UARTB, TEGRA20_CLK_PLL_P, 0, 0},
|
||||
{TEGRA20_CLK_UARTC, TEGRA20_CLK_PLL_P, 0, 0},
|
||||
{TEGRA20_CLK_UARTD, TEGRA20_CLK_PLL_P, 0, 0},
|
||||
{TEGRA20_CLK_UARTE, TEGRA20_CLK_PLL_P, 0, 0},
|
||||
{TEGRA20_CLK_PLL_A, TEGRA20_CLK_CLK_MAX, 56448000, 1},
|
||||
{TEGRA20_CLK_PLL_A_OUT0, TEGRA20_CLK_CLK_MAX, 11289600, 1},
|
||||
{TEGRA20_CLK_CDEV1, TEGRA20_CLK_CLK_MAX, 0, 1},
|
||||
{TEGRA20_CLK_BLINK, TEGRA20_CLK_CLK_MAX, 32768, 1},
|
||||
{TEGRA20_CLK_I2S1, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0},
|
||||
{TEGRA20_CLK_I2S2, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0},
|
||||
{TEGRA20_CLK_SDMMC1, TEGRA20_CLK_PLL_P, 48000000, 0},
|
||||
{TEGRA20_CLK_SDMMC3, TEGRA20_CLK_PLL_P, 48000000, 0},
|
||||
{TEGRA20_CLK_SDMMC4, TEGRA20_CLK_PLL_P, 48000000, 0},
|
||||
{TEGRA20_CLK_SPI, TEGRA20_CLK_PLL_P, 20000000, 0},
|
||||
{TEGRA20_CLK_SBC1, TEGRA20_CLK_PLL_P, 100000000, 0},
|
||||
{TEGRA20_CLK_SBC2, TEGRA20_CLK_PLL_P, 100000000, 0},
|
||||
{TEGRA20_CLK_SBC3, TEGRA20_CLK_PLL_P, 100000000, 0},
|
||||
{TEGRA20_CLK_SBC4, TEGRA20_CLK_PLL_P, 100000000, 0},
|
||||
{TEGRA20_CLK_HOST1X, TEGRA20_CLK_PLL_C, 150000000, 0},
|
||||
{TEGRA20_CLK_DISP1, TEGRA20_CLK_PLL_P, 600000000, 0},
|
||||
{TEGRA20_CLK_DISP2, TEGRA20_CLK_PLL_P, 600000000, 0},
|
||||
{TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 300000000, 0},
|
||||
{TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0},
|
||||
{TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0}, /* This MUST be the last entry */
|
||||
{ TEGRA20_CLK_PLL_P, TEGRA20_CLK_CLK_MAX, 216000000, 1 },
|
||||
{ TEGRA20_CLK_PLL_P_OUT1, TEGRA20_CLK_CLK_MAX, 28800000, 1 },
|
||||
{ TEGRA20_CLK_PLL_P_OUT2, TEGRA20_CLK_CLK_MAX, 48000000, 1 },
|
||||
{ TEGRA20_CLK_PLL_P_OUT3, TEGRA20_CLK_CLK_MAX, 72000000, 1 },
|
||||
{ TEGRA20_CLK_PLL_P_OUT4, TEGRA20_CLK_CLK_MAX, 24000000, 1 },
|
||||
{ TEGRA20_CLK_PLL_C, TEGRA20_CLK_CLK_MAX, 600000000, 1 },
|
||||
{ TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 120000000, 1 },
|
||||
{ TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 0, 1 },
|
||||
{ TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA20_CLK_PCLK, TEGRA20_CLK_CLK_MAX, 60000000, 1 },
|
||||
{ TEGRA20_CLK_CSITE, TEGRA20_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA20_CLK_EMC, TEGRA20_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA20_CLK_CCLK, TEGRA20_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA20_CLK_UARTA, TEGRA20_CLK_PLL_P, 0, 0 },
|
||||
{ TEGRA20_CLK_UARTB, TEGRA20_CLK_PLL_P, 0, 0 },
|
||||
{ TEGRA20_CLK_UARTC, TEGRA20_CLK_PLL_P, 0, 0 },
|
||||
{ TEGRA20_CLK_UARTD, TEGRA20_CLK_PLL_P, 0, 0 },
|
||||
{ TEGRA20_CLK_UARTE, TEGRA20_CLK_PLL_P, 0, 0 },
|
||||
{ TEGRA20_CLK_PLL_A, TEGRA20_CLK_CLK_MAX, 56448000, 1 },
|
||||
{ TEGRA20_CLK_PLL_A_OUT0, TEGRA20_CLK_CLK_MAX, 11289600, 1 },
|
||||
{ TEGRA20_CLK_CDEV1, TEGRA20_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA20_CLK_BLINK, TEGRA20_CLK_CLK_MAX, 32768, 1 },
|
||||
{ TEGRA20_CLK_I2S1, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA20_CLK_I2S2, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA20_CLK_SDMMC1, TEGRA20_CLK_PLL_P, 48000000, 0 },
|
||||
{ TEGRA20_CLK_SDMMC3, TEGRA20_CLK_PLL_P, 48000000, 0 },
|
||||
{ TEGRA20_CLK_SDMMC4, TEGRA20_CLK_PLL_P, 48000000, 0 },
|
||||
{ TEGRA20_CLK_SPI, TEGRA20_CLK_PLL_P, 20000000, 0 },
|
||||
{ TEGRA20_CLK_SBC1, TEGRA20_CLK_PLL_P, 100000000, 0 },
|
||||
{ TEGRA20_CLK_SBC2, TEGRA20_CLK_PLL_P, 100000000, 0 },
|
||||
{ TEGRA20_CLK_SBC3, TEGRA20_CLK_PLL_P, 100000000, 0 },
|
||||
{ TEGRA20_CLK_SBC4, TEGRA20_CLK_PLL_P, 100000000, 0 },
|
||||
{ TEGRA20_CLK_HOST1X, TEGRA20_CLK_PLL_C, 150000000, 0 },
|
||||
{ TEGRA20_CLK_DISP1, TEGRA20_CLK_PLL_P, 600000000, 0 },
|
||||
{ TEGRA20_CLK_DISP2, TEGRA20_CLK_PLL_P, 600000000, 0 },
|
||||
{ TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 300000000, 0 },
|
||||
{ TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0 },
|
||||
/* must be the last entry */
|
||||
{ TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0 },
|
||||
};
|
||||
|
||||
static void __init tegra20_clock_apply_init_table(void)
|
||||
|
|
@ -1075,11 +1065,12 @@ static void __init tegra20_clock_apply_init_table(void)
|
|||
* table under two names.
|
||||
*/
|
||||
static struct tegra_clk_duplicate tegra_clk_duplicates[] = {
|
||||
TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "utmip-pad", NULL),
|
||||
TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "tegra-ehci.0", NULL),
|
||||
TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "tegra-otg", NULL),
|
||||
TEGRA_CLK_DUPLICATE(TEGRA20_CLK_CCLK, NULL, "cpu"),
|
||||
TEGRA_CLK_DUPLICATE(TEGRA20_CLK_CLK_MAX, NULL, NULL), /* Must be the last entry */
|
||||
TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "utmip-pad", NULL),
|
||||
TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "tegra-ehci.0", NULL),
|
||||
TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "tegra-otg", NULL),
|
||||
TEGRA_CLK_DUPLICATE(TEGRA20_CLK_CCLK, NULL, "cpu"),
|
||||
/* must be the last entry */
|
||||
TEGRA_CLK_DUPLICATE(TEGRA20_CLK_CLK_MAX, NULL, NULL),
|
||||
};
|
||||
|
||||
static const struct of_device_id pmc_match[] __initconst = {
|
||||
|
|
|
|||
|
|
@ -224,106 +224,112 @@ struct utmi_clk_param {
|
|||
};
|
||||
|
||||
static const struct utmi_clk_param utmi_parameters[] = {
|
||||
/* OSC_FREQUENCY, ENABLE_DLY, STABLE_CNT, ACTIVE_DLY, XTAL_FREQ_CNT */
|
||||
{13000000, 0x02, 0x33, 0x05, 0x7F},
|
||||
{19200000, 0x03, 0x4B, 0x06, 0xBB},
|
||||
{12000000, 0x02, 0x2F, 0x04, 0x76},
|
||||
{26000000, 0x04, 0x66, 0x09, 0xFE},
|
||||
{16800000, 0x03, 0x41, 0x0A, 0xA4},
|
||||
{
|
||||
.osc_frequency = 13000000, .enable_delay_count = 0x02,
|
||||
.stable_count = 0x33, .active_delay_count = 0x05,
|
||||
.xtal_freq_count = 0x7f
|
||||
}, {
|
||||
.osc_frequency = 19200000, .enable_delay_count = 0x03,
|
||||
.stable_count = 0x4b, .active_delay_count = 0x06,
|
||||
.xtal_freq_count = 0xbb
|
||||
}, {
|
||||
.osc_frequency = 12000000, .enable_delay_count = 0x02,
|
||||
.stable_count = 0x2f, .active_delay_count = 0x04,
|
||||
.xtal_freq_count = 0x76
|
||||
}, {
|
||||
.osc_frequency = 26000000, .enable_delay_count = 0x04,
|
||||
.stable_count = 0x66, .active_delay_count = 0x09,
|
||||
.xtal_freq_count = 0xfe
|
||||
}, {
|
||||
.osc_frequency = 16800000, .enable_delay_count = 0x03,
|
||||
.stable_count = 0x41, .active_delay_count = 0x0a,
|
||||
.xtal_freq_count = 0xa4
|
||||
},
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
|
||||
{ 12000000, 1040000000, 520, 6, 0, 8},
|
||||
{ 13000000, 1040000000, 480, 6, 0, 8},
|
||||
{ 16800000, 1040000000, 495, 8, 0, 8}, /* actual: 1039.5 MHz */
|
||||
{ 19200000, 1040000000, 325, 6, 0, 6},
|
||||
{ 26000000, 1040000000, 520, 13, 0, 8},
|
||||
|
||||
{ 12000000, 832000000, 416, 6, 0, 8},
|
||||
{ 13000000, 832000000, 832, 13, 0, 8},
|
||||
{ 16800000, 832000000, 396, 8, 0, 8}, /* actual: 831.6 MHz */
|
||||
{ 19200000, 832000000, 260, 6, 0, 8},
|
||||
{ 26000000, 832000000, 416, 13, 0, 8},
|
||||
|
||||
{ 12000000, 624000000, 624, 12, 0, 8},
|
||||
{ 13000000, 624000000, 624, 13, 0, 8},
|
||||
{ 16800000, 600000000, 520, 14, 0, 8},
|
||||
{ 19200000, 624000000, 520, 16, 0, 8},
|
||||
{ 26000000, 624000000, 624, 26, 0, 8},
|
||||
|
||||
{ 12000000, 600000000, 600, 12, 0, 8},
|
||||
{ 13000000, 600000000, 600, 13, 0, 8},
|
||||
{ 16800000, 600000000, 500, 14, 0, 8},
|
||||
{ 19200000, 600000000, 375, 12, 0, 6},
|
||||
{ 26000000, 600000000, 600, 26, 0, 8},
|
||||
|
||||
{ 12000000, 520000000, 520, 12, 0, 8},
|
||||
{ 13000000, 520000000, 520, 13, 0, 8},
|
||||
{ 16800000, 520000000, 495, 16, 0, 8}, /* actual: 519.75 MHz */
|
||||
{ 19200000, 520000000, 325, 12, 0, 6},
|
||||
{ 26000000, 520000000, 520, 26, 0, 8},
|
||||
|
||||
{ 12000000, 416000000, 416, 12, 0, 8},
|
||||
{ 13000000, 416000000, 416, 13, 0, 8},
|
||||
{ 16800000, 416000000, 396, 16, 0, 8}, /* actual: 415.8 MHz */
|
||||
{ 19200000, 416000000, 260, 12, 0, 6},
|
||||
{ 26000000, 416000000, 416, 26, 0, 8},
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
{ 12000000, 1040000000, 520, 6, 0, 8 },
|
||||
{ 13000000, 1040000000, 480, 6, 0, 8 },
|
||||
{ 16800000, 1040000000, 495, 8, 0, 8 }, /* actual: 1039.5 MHz */
|
||||
{ 19200000, 1040000000, 325, 6, 0, 6 },
|
||||
{ 26000000, 1040000000, 520, 13, 0, 8 },
|
||||
{ 12000000, 832000000, 416, 6, 0, 8 },
|
||||
{ 13000000, 832000000, 832, 13, 0, 8 },
|
||||
{ 16800000, 832000000, 396, 8, 0, 8 }, /* actual: 831.6 MHz */
|
||||
{ 19200000, 832000000, 260, 6, 0, 8 },
|
||||
{ 26000000, 832000000, 416, 13, 0, 8 },
|
||||
{ 12000000, 624000000, 624, 12, 0, 8 },
|
||||
{ 13000000, 624000000, 624, 13, 0, 8 },
|
||||
{ 16800000, 600000000, 520, 14, 0, 8 },
|
||||
{ 19200000, 624000000, 520, 16, 0, 8 },
|
||||
{ 26000000, 624000000, 624, 26, 0, 8 },
|
||||
{ 12000000, 600000000, 600, 12, 0, 8 },
|
||||
{ 13000000, 600000000, 600, 13, 0, 8 },
|
||||
{ 16800000, 600000000, 500, 14, 0, 8 },
|
||||
{ 19200000, 600000000, 375, 12, 0, 6 },
|
||||
{ 26000000, 600000000, 600, 26, 0, 8 },
|
||||
{ 12000000, 520000000, 520, 12, 0, 8 },
|
||||
{ 13000000, 520000000, 520, 13, 0, 8 },
|
||||
{ 16800000, 520000000, 495, 16, 0, 8 }, /* actual: 519.75 MHz */
|
||||
{ 19200000, 520000000, 325, 12, 0, 6 },
|
||||
{ 26000000, 520000000, 520, 26, 0, 8 },
|
||||
{ 12000000, 416000000, 416, 12, 0, 8 },
|
||||
{ 13000000, 416000000, 416, 13, 0, 8 },
|
||||
{ 16800000, 416000000, 396, 16, 0, 8 }, /* actual: 415.8 MHz */
|
||||
{ 19200000, 416000000, 260, 12, 0, 6 },
|
||||
{ 26000000, 416000000, 416, 26, 0, 8 },
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
|
||||
{ 12000000, 666000000, 666, 12, 0, 8},
|
||||
{ 13000000, 666000000, 666, 13, 0, 8},
|
||||
{ 16800000, 666000000, 555, 14, 0, 8},
|
||||
{ 19200000, 666000000, 555, 16, 0, 8},
|
||||
{ 26000000, 666000000, 666, 26, 0, 8},
|
||||
{ 12000000, 600000000, 600, 12, 0, 8},
|
||||
{ 13000000, 600000000, 600, 13, 0, 8},
|
||||
{ 16800000, 600000000, 500, 14, 0, 8},
|
||||
{ 19200000, 600000000, 375, 12, 0, 6},
|
||||
{ 26000000, 600000000, 600, 26, 0, 8},
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
{ 12000000, 666000000, 666, 12, 0, 8 },
|
||||
{ 13000000, 666000000, 666, 13, 0, 8 },
|
||||
{ 16800000, 666000000, 555, 14, 0, 8 },
|
||||
{ 19200000, 666000000, 555, 16, 0, 8 },
|
||||
{ 26000000, 666000000, 666, 26, 0, 8 },
|
||||
{ 12000000, 600000000, 600, 12, 0, 8 },
|
||||
{ 13000000, 600000000, 600, 13, 0, 8 },
|
||||
{ 16800000, 600000000, 500, 14, 0, 8 },
|
||||
{ 19200000, 600000000, 375, 12, 0, 6 },
|
||||
{ 26000000, 600000000, 600, 26, 0, 8 },
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
|
||||
{ 12000000, 216000000, 432, 12, 1, 8},
|
||||
{ 13000000, 216000000, 432, 13, 1, 8},
|
||||
{ 16800000, 216000000, 360, 14, 1, 8},
|
||||
{ 19200000, 216000000, 360, 16, 1, 8},
|
||||
{ 26000000, 216000000, 432, 26, 1, 8},
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
{ 12000000, 216000000, 432, 12, 1, 8 },
|
||||
{ 13000000, 216000000, 432, 13, 1, 8 },
|
||||
{ 16800000, 216000000, 360, 14, 1, 8 },
|
||||
{ 19200000, 216000000, 360, 16, 1, 8 },
|
||||
{ 26000000, 216000000, 432, 26, 1, 8 },
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
|
||||
{ 9600000, 564480000, 294, 5, 0, 4},
|
||||
{ 9600000, 552960000, 288, 5, 0, 4},
|
||||
{ 9600000, 24000000, 5, 2, 0, 1},
|
||||
|
||||
{ 28800000, 56448000, 49, 25, 0, 1},
|
||||
{ 28800000, 73728000, 64, 25, 0, 1},
|
||||
{ 28800000, 24000000, 5, 6, 0, 1},
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
{ 9600000, 564480000, 294, 5, 0, 4 },
|
||||
{ 9600000, 552960000, 288, 5, 0, 4 },
|
||||
{ 9600000, 24000000, 5, 2, 0, 1 },
|
||||
{ 28800000, 56448000, 49, 25, 0, 1 },
|
||||
{ 28800000, 73728000, 64, 25, 0, 1 },
|
||||
{ 28800000, 24000000, 5, 6, 0, 1 },
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
|
||||
{ 12000000, 216000000, 216, 12, 0, 4},
|
||||
{ 13000000, 216000000, 216, 13, 0, 4},
|
||||
{ 16800000, 216000000, 180, 14, 0, 4},
|
||||
{ 19200000, 216000000, 180, 16, 0, 4},
|
||||
{ 26000000, 216000000, 216, 26, 0, 4},
|
||||
|
||||
{ 12000000, 594000000, 594, 12, 0, 8},
|
||||
{ 13000000, 594000000, 594, 13, 0, 8},
|
||||
{ 16800000, 594000000, 495, 14, 0, 8},
|
||||
{ 19200000, 594000000, 495, 16, 0, 8},
|
||||
{ 26000000, 594000000, 594, 26, 0, 8},
|
||||
|
||||
{ 12000000, 1000000000, 1000, 12, 0, 12},
|
||||
{ 13000000, 1000000000, 1000, 13, 0, 12},
|
||||
{ 19200000, 1000000000, 625, 12, 0, 8},
|
||||
{ 26000000, 1000000000, 1000, 26, 0, 12},
|
||||
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
{ 12000000, 216000000, 216, 12, 0, 4 },
|
||||
{ 13000000, 216000000, 216, 13, 0, 4 },
|
||||
{ 16800000, 216000000, 180, 14, 0, 4 },
|
||||
{ 19200000, 216000000, 180, 16, 0, 4 },
|
||||
{ 26000000, 216000000, 216, 26, 0, 4 },
|
||||
{ 12000000, 594000000, 594, 12, 0, 8 },
|
||||
{ 13000000, 594000000, 594, 13, 0, 8 },
|
||||
{ 16800000, 594000000, 495, 14, 0, 8 },
|
||||
{ 19200000, 594000000, 495, 16, 0, 8 },
|
||||
{ 26000000, 594000000, 594, 26, 0, 8 },
|
||||
{ 12000000, 1000000000, 1000, 12, 0, 12 },
|
||||
{ 13000000, 1000000000, 1000, 13, 0, 12 },
|
||||
{ 19200000, 1000000000, 625, 12, 0, 8 },
|
||||
{ 26000000, 1000000000, 1000, 26, 0, 12 },
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct pdiv_map pllu_p[] = {
|
||||
|
|
@ -333,79 +339,71 @@ static struct pdiv_map pllu_p[] = {
|
|||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
|
||||
{ 12000000, 480000000, 960, 12, 0, 12},
|
||||
{ 13000000, 480000000, 960, 13, 0, 12},
|
||||
{ 16800000, 480000000, 400, 7, 0, 5},
|
||||
{ 19200000, 480000000, 200, 4, 0, 3},
|
||||
{ 26000000, 480000000, 960, 26, 0, 12},
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
{ 12000000, 480000000, 960, 12, 0, 12 },
|
||||
{ 13000000, 480000000, 960, 13, 0, 12 },
|
||||
{ 16800000, 480000000, 400, 7, 0, 5 },
|
||||
{ 19200000, 480000000, 200, 4, 0, 3 },
|
||||
{ 26000000, 480000000, 960, 26, 0, 12 },
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
|
||||
/* 1.7 GHz */
|
||||
{ 12000000, 1700000000, 850, 6, 0, 8},
|
||||
{ 13000000, 1700000000, 915, 7, 0, 8}, /* actual: 1699.2 MHz */
|
||||
{ 16800000, 1700000000, 708, 7, 0, 8}, /* actual: 1699.2 MHz */
|
||||
{ 19200000, 1700000000, 885, 10, 0, 8}, /* actual: 1699.2 MHz */
|
||||
{ 26000000, 1700000000, 850, 13, 0, 8},
|
||||
|
||||
{ 12000000, 1700000000, 850, 6, 0, 8 },
|
||||
{ 13000000, 1700000000, 915, 7, 0, 8 }, /* actual: 1699.2 MHz */
|
||||
{ 16800000, 1700000000, 708, 7, 0, 8 }, /* actual: 1699.2 MHz */
|
||||
{ 19200000, 1700000000, 885, 10, 0, 8 }, /* actual: 1699.2 MHz */
|
||||
{ 26000000, 1700000000, 850, 13, 0, 8 },
|
||||
/* 1.6 GHz */
|
||||
{ 12000000, 1600000000, 800, 6, 0, 8},
|
||||
{ 13000000, 1600000000, 738, 6, 0, 8}, /* actual: 1599.0 MHz */
|
||||
{ 16800000, 1600000000, 857, 9, 0, 8}, /* actual: 1599.7 MHz */
|
||||
{ 19200000, 1600000000, 500, 6, 0, 8},
|
||||
{ 26000000, 1600000000, 800, 13, 0, 8},
|
||||
|
||||
{ 12000000, 1600000000, 800, 6, 0, 8 },
|
||||
{ 13000000, 1600000000, 738, 6, 0, 8 }, /* actual: 1599.0 MHz */
|
||||
{ 16800000, 1600000000, 857, 9, 0, 8 }, /* actual: 1599.7 MHz */
|
||||
{ 19200000, 1600000000, 500, 6, 0, 8 },
|
||||
{ 26000000, 1600000000, 800, 13, 0, 8 },
|
||||
/* 1.5 GHz */
|
||||
{ 12000000, 1500000000, 750, 6, 0, 8},
|
||||
{ 13000000, 1500000000, 923, 8, 0, 8}, /* actual: 1499.8 MHz */
|
||||
{ 16800000, 1500000000, 625, 7, 0, 8},
|
||||
{ 19200000, 1500000000, 625, 8, 0, 8},
|
||||
{ 26000000, 1500000000, 750, 13, 0, 8},
|
||||
|
||||
{ 12000000, 1500000000, 750, 6, 0, 8 },
|
||||
{ 13000000, 1500000000, 923, 8, 0, 8 }, /* actual: 1499.8 MHz */
|
||||
{ 16800000, 1500000000, 625, 7, 0, 8 },
|
||||
{ 19200000, 1500000000, 625, 8, 0, 8 },
|
||||
{ 26000000, 1500000000, 750, 13, 0, 8 },
|
||||
/* 1.4 GHz */
|
||||
{ 12000000, 1400000000, 700, 6, 0, 8},
|
||||
{ 13000000, 1400000000, 969, 9, 0, 8}, /* actual: 1399.7 MHz */
|
||||
{ 16800000, 1400000000, 1000, 12, 0, 8},
|
||||
{ 19200000, 1400000000, 875, 12, 0, 8},
|
||||
{ 26000000, 1400000000, 700, 13, 0, 8},
|
||||
|
||||
{ 12000000, 1400000000, 700, 6, 0, 8 },
|
||||
{ 13000000, 1400000000, 969, 9, 0, 8 }, /* actual: 1399.7 MHz */
|
||||
{ 16800000, 1400000000, 1000, 12, 0, 8 },
|
||||
{ 19200000, 1400000000, 875, 12, 0, 8 },
|
||||
{ 26000000, 1400000000, 700, 13, 0, 8 },
|
||||
/* 1.3 GHz */
|
||||
{ 12000000, 1300000000, 975, 9, 0, 8},
|
||||
{ 13000000, 1300000000, 1000, 10, 0, 8},
|
||||
{ 16800000, 1300000000, 928, 12, 0, 8}, /* actual: 1299.2 MHz */
|
||||
{ 19200000, 1300000000, 812, 12, 0, 8}, /* actual: 1299.2 MHz */
|
||||
{ 26000000, 1300000000, 650, 13, 0, 8},
|
||||
|
||||
{ 12000000, 1300000000, 975, 9, 0, 8 },
|
||||
{ 13000000, 1300000000, 1000, 10, 0, 8 },
|
||||
{ 16800000, 1300000000, 928, 12, 0, 8 }, /* actual: 1299.2 MHz */
|
||||
{ 19200000, 1300000000, 812, 12, 0, 8 }, /* actual: 1299.2 MHz */
|
||||
{ 26000000, 1300000000, 650, 13, 0, 8 },
|
||||
/* 1.2 GHz */
|
||||
{ 12000000, 1200000000, 1000, 10, 0, 8},
|
||||
{ 13000000, 1200000000, 923, 10, 0, 8}, /* actual: 1199.9 MHz */
|
||||
{ 16800000, 1200000000, 1000, 14, 0, 8},
|
||||
{ 19200000, 1200000000, 1000, 16, 0, 8},
|
||||
{ 26000000, 1200000000, 600, 13, 0, 8},
|
||||
|
||||
{ 12000000, 1200000000, 1000, 10, 0, 8 },
|
||||
{ 13000000, 1200000000, 923, 10, 0, 8 }, /* actual: 1199.9 MHz */
|
||||
{ 16800000, 1200000000, 1000, 14, 0, 8 },
|
||||
{ 19200000, 1200000000, 1000, 16, 0, 8 },
|
||||
{ 26000000, 1200000000, 600, 13, 0, 8 },
|
||||
/* 1.1 GHz */
|
||||
{ 12000000, 1100000000, 825, 9, 0, 8},
|
||||
{ 13000000, 1100000000, 846, 10, 0, 8}, /* actual: 1099.8 MHz */
|
||||
{ 16800000, 1100000000, 982, 15, 0, 8}, /* actual: 1099.8 MHz */
|
||||
{ 19200000, 1100000000, 859, 15, 0, 8}, /* actual: 1099.5 MHz */
|
||||
{ 26000000, 1100000000, 550, 13, 0, 8},
|
||||
|
||||
{ 12000000, 1100000000, 825, 9, 0, 8 },
|
||||
{ 13000000, 1100000000, 846, 10, 0, 8 }, /* actual: 1099.8 MHz */
|
||||
{ 16800000, 1100000000, 982, 15, 0, 8 }, /* actual: 1099.8 MHz */
|
||||
{ 19200000, 1100000000, 859, 15, 0, 8 }, /* actual: 1099.5 MHz */
|
||||
{ 26000000, 1100000000, 550, 13, 0, 8 },
|
||||
/* 1 GHz */
|
||||
{ 12000000, 1000000000, 1000, 12, 0, 8},
|
||||
{ 13000000, 1000000000, 1000, 13, 0, 8},
|
||||
{ 16800000, 1000000000, 833, 14, 0, 8}, /* actual: 999.6 MHz */
|
||||
{ 19200000, 1000000000, 625, 12, 0, 8},
|
||||
{ 26000000, 1000000000, 1000, 26, 0, 8},
|
||||
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
{ 12000000, 1000000000, 1000, 12, 0, 8 },
|
||||
{ 13000000, 1000000000, 1000, 13, 0, 8 },
|
||||
{ 16800000, 1000000000, 833, 14, 0, 8 }, /* actual: 999.6 MHz */
|
||||
{ 19200000, 1000000000, 625, 12, 0, 8 },
|
||||
{ 26000000, 1000000000, 1000, 26, 0, 8 },
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
|
||||
/* PLLE special case: use cpcon field to store cml divider value */
|
||||
{ 12000000, 100000000, 150, 1, 18, 11},
|
||||
{ 216000000, 100000000, 200, 18, 24, 13},
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
{ 12000000, 100000000, 150, 1, 18, 11 },
|
||||
{ 216000000, 100000000, 200, 18, 24, 13 },
|
||||
{ 0, 0, 0, 0, 0, 0 },
|
||||
};
|
||||
|
||||
/* PLL parameters */
|
||||
|
|
@ -576,12 +574,12 @@ static struct tegra_clk_pll_params pll_e_params = {
|
|||
};
|
||||
|
||||
static unsigned long tegra30_input_freq[] = {
|
||||
[0] = 13000000,
|
||||
[1] = 16800000,
|
||||
[4] = 19200000,
|
||||
[5] = 38400000,
|
||||
[8] = 12000000,
|
||||
[9] = 48000000,
|
||||
[ 0] = 13000000,
|
||||
[ 1] = 16800000,
|
||||
[ 4] = 19200000,
|
||||
[ 5] = 38400000,
|
||||
[ 8] = 12000000,
|
||||
[ 9] = 48000000,
|
||||
[12] = 26000000,
|
||||
};
|
||||
|
||||
|
|
@ -915,7 +913,7 @@ static void tegra30_utmi_param_configure(void)
|
|||
writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
|
||||
}
|
||||
|
||||
static const char *pll_e_parents[] = {"pll_ref", "pll_p"};
|
||||
static const char *pll_e_parents[] = { "pll_ref", "pll_p" };
|
||||
|
||||
static void __init tegra30_pll_init(void)
|
||||
{
|
||||
|
|
@ -1331,44 +1329,45 @@ static struct tegra_cpu_car_ops tegra30_cpu_car_ops = {
|
|||
};
|
||||
|
||||
static struct tegra_clk_init_table init_table[] __initdata = {
|
||||
{TEGRA30_CLK_UARTA, TEGRA30_CLK_PLL_P, 408000000, 0},
|
||||
{TEGRA30_CLK_UARTB, TEGRA30_CLK_PLL_P, 408000000, 0},
|
||||
{TEGRA30_CLK_UARTC, TEGRA30_CLK_PLL_P, 408000000, 0},
|
||||
{TEGRA30_CLK_UARTD, TEGRA30_CLK_PLL_P, 408000000, 0},
|
||||
{TEGRA30_CLK_UARTE, TEGRA30_CLK_PLL_P, 408000000, 0},
|
||||
{TEGRA30_CLK_PLL_A, TEGRA30_CLK_CLK_MAX, 564480000, 1},
|
||||
{TEGRA30_CLK_PLL_A_OUT0, TEGRA30_CLK_CLK_MAX, 11289600, 1},
|
||||
{TEGRA30_CLK_EXTERN1, TEGRA30_CLK_PLL_A_OUT0, 0, 1},
|
||||
{TEGRA30_CLK_CLK_OUT_1_MUX, TEGRA30_CLK_EXTERN1, 0, 0},
|
||||
{TEGRA30_CLK_CLK_OUT_1, TEGRA30_CLK_CLK_MAX, 0, 1},
|
||||
{TEGRA30_CLK_BLINK, TEGRA30_CLK_CLK_MAX, 0, 1},
|
||||
{TEGRA30_CLK_I2S0, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0},
|
||||
{TEGRA30_CLK_I2S1, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0},
|
||||
{TEGRA30_CLK_I2S2, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0},
|
||||
{TEGRA30_CLK_I2S3, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0},
|
||||
{TEGRA30_CLK_I2S4, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0},
|
||||
{TEGRA30_CLK_SDMMC1, TEGRA30_CLK_PLL_P, 48000000, 0},
|
||||
{TEGRA30_CLK_SDMMC2, TEGRA30_CLK_PLL_P, 48000000, 0},
|
||||
{TEGRA30_CLK_SDMMC3, TEGRA30_CLK_PLL_P, 48000000, 0},
|
||||
{TEGRA30_CLK_PLL_M, TEGRA30_CLK_CLK_MAX, 0, 1},
|
||||
{TEGRA30_CLK_PCLK, TEGRA30_CLK_CLK_MAX, 0, 1},
|
||||
{TEGRA30_CLK_CSITE, TEGRA30_CLK_CLK_MAX, 0, 1},
|
||||
{TEGRA30_CLK_EMC, TEGRA30_CLK_CLK_MAX, 0, 1},
|
||||
{TEGRA30_CLK_MSELECT, TEGRA30_CLK_CLK_MAX, 0, 1},
|
||||
{TEGRA30_CLK_SBC1, TEGRA30_CLK_PLL_P, 100000000, 0},
|
||||
{TEGRA30_CLK_SBC2, TEGRA30_CLK_PLL_P, 100000000, 0},
|
||||
{TEGRA30_CLK_SBC3, TEGRA30_CLK_PLL_P, 100000000, 0},
|
||||
{TEGRA30_CLK_SBC4, TEGRA30_CLK_PLL_P, 100000000, 0},
|
||||
{TEGRA30_CLK_SBC5, TEGRA30_CLK_PLL_P, 100000000, 0},
|
||||
{TEGRA30_CLK_SBC6, TEGRA30_CLK_PLL_P, 100000000, 0},
|
||||
{TEGRA30_CLK_HOST1X, TEGRA30_CLK_PLL_C, 150000000, 0},
|
||||
{TEGRA30_CLK_DISP1, TEGRA30_CLK_PLL_P, 600000000, 0},
|
||||
{TEGRA30_CLK_DISP2, TEGRA30_CLK_PLL_P, 600000000, 0},
|
||||
{TEGRA30_CLK_TWD, TEGRA30_CLK_CLK_MAX, 0, 1},
|
||||
{TEGRA30_CLK_GR2D, TEGRA30_CLK_PLL_C, 300000000, 0},
|
||||
{TEGRA30_CLK_GR3D, TEGRA30_CLK_PLL_C, 300000000, 0},
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||||
{TEGRA30_CLK_GR3D2, TEGRA30_CLK_PLL_C, 300000000, 0},
|
||||
{TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0}, /* This MUST be the last entry. */
|
||||
{ TEGRA30_CLK_UARTA, TEGRA30_CLK_PLL_P, 408000000, 0 },
|
||||
{ TEGRA30_CLK_UARTB, TEGRA30_CLK_PLL_P, 408000000, 0 },
|
||||
{ TEGRA30_CLK_UARTC, TEGRA30_CLK_PLL_P, 408000000, 0 },
|
||||
{ TEGRA30_CLK_UARTD, TEGRA30_CLK_PLL_P, 408000000, 0 },
|
||||
{ TEGRA30_CLK_UARTE, TEGRA30_CLK_PLL_P, 408000000, 0 },
|
||||
{ TEGRA30_CLK_PLL_A, TEGRA30_CLK_CLK_MAX, 564480000, 1 },
|
||||
{ TEGRA30_CLK_PLL_A_OUT0, TEGRA30_CLK_CLK_MAX, 11289600, 1 },
|
||||
{ TEGRA30_CLK_EXTERN1, TEGRA30_CLK_PLL_A_OUT0, 0, 1 },
|
||||
{ TEGRA30_CLK_CLK_OUT_1_MUX, TEGRA30_CLK_EXTERN1, 0, 0 },
|
||||
{ TEGRA30_CLK_CLK_OUT_1, TEGRA30_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA30_CLK_BLINK, TEGRA30_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA30_CLK_I2S0, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA30_CLK_I2S1, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA30_CLK_I2S2, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA30_CLK_I2S3, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA30_CLK_I2S4, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
|
||||
{ TEGRA30_CLK_SDMMC1, TEGRA30_CLK_PLL_P, 48000000, 0 },
|
||||
{ TEGRA30_CLK_SDMMC2, TEGRA30_CLK_PLL_P, 48000000, 0 },
|
||||
{ TEGRA30_CLK_SDMMC3, TEGRA30_CLK_PLL_P, 48000000, 0 },
|
||||
{ TEGRA30_CLK_PLL_M, TEGRA30_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA30_CLK_PCLK, TEGRA30_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA30_CLK_CSITE, TEGRA30_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA30_CLK_EMC, TEGRA30_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA30_CLK_MSELECT, TEGRA30_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA30_CLK_SBC1, TEGRA30_CLK_PLL_P, 100000000, 0 },
|
||||
{ TEGRA30_CLK_SBC2, TEGRA30_CLK_PLL_P, 100000000, 0 },
|
||||
{ TEGRA30_CLK_SBC3, TEGRA30_CLK_PLL_P, 100000000, 0 },
|
||||
{ TEGRA30_CLK_SBC4, TEGRA30_CLK_PLL_P, 100000000, 0 },
|
||||
{ TEGRA30_CLK_SBC5, TEGRA30_CLK_PLL_P, 100000000, 0 },
|
||||
{ TEGRA30_CLK_SBC6, TEGRA30_CLK_PLL_P, 100000000, 0 },
|
||||
{ TEGRA30_CLK_HOST1X, TEGRA30_CLK_PLL_C, 150000000, 0 },
|
||||
{ TEGRA30_CLK_DISP1, TEGRA30_CLK_PLL_P, 600000000, 0 },
|
||||
{ TEGRA30_CLK_DISP2, TEGRA30_CLK_PLL_P, 600000000, 0 },
|
||||
{ TEGRA30_CLK_TWD, TEGRA30_CLK_CLK_MAX, 0, 1 },
|
||||
{ TEGRA30_CLK_GR2D, TEGRA30_CLK_PLL_C, 300000000, 0 },
|
||||
{ TEGRA30_CLK_GR3D, TEGRA30_CLK_PLL_C, 300000000, 0 },
|
||||
{ TEGRA30_CLK_GR3D2, TEGRA30_CLK_PLL_C, 300000000, 0 },
|
||||
/* must be the last entry */
|
||||
{ TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0 },
|
||||
};
|
||||
|
||||
static void __init tegra30_clock_apply_init_table(void)
|
||||
|
|
@ -1393,7 +1392,8 @@ static struct tegra_clk_duplicate tegra_clk_duplicates[] = {
|
|||
TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CML1, "tegra_sata_cml", NULL),
|
||||
TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CML0, "tegra_pcie", "cml"),
|
||||
TEGRA_CLK_DUPLICATE(TEGRA30_CLK_VCP, "nvavp", "vcp"),
|
||||
TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CLK_MAX, NULL, NULL), /* MUST be the last entry */
|
||||
/* must be the last entry */
|
||||
TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CLK_MAX, NULL, NULL),
|
||||
};
|
||||
|
||||
static const struct of_device_id pmc_match[] __initconst = {
|
||||
|
|
|
|||
Loading…
Reference in New Issue