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[PATCH] sky2: fixes for Yukon EC_U chip revisions 

Update workarounds for 88E803X based on the latest SysKonnect vendor
driver version (8.41). Tested on EC_U rev A1, only.
These up the receive performance.

Signed-off-by: Stephen Hemminger <shemminger@osdl.org>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
Stephen Hemminger 2006-12-01 14:29:35 -08:00 committed by Jeff Garzik
parent 508f89e75a
commit 8df9a87604
2 changed files with 13 additions and 9 deletions
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13
drivers/net/sky2.c
View File

@ -677,17 +677,15 @@ static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
/* Flush Rx MAC FIFO on any flow control or error */
sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
/* Set threshold to 0xa (64 bytes)
* ASF disabled so no need to do WA dev #4.30
*/
sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
/* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
/* Configure Tx MAC FIFO */
sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 512/8);
sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
if (hw->dev[port]->mtu > ETH_DATA_LEN) {
/* set Tx GMAC FIFO Almost Empty Threshold */
@ -1061,7 +1059,8 @@ static int sky2_rx_start(struct sky2_port *sky2)
sky2->rx_put = sky2->rx_next = 0;
sky2_qset(hw, rxq);
if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
(hw->chip_rev == CHIP_REV_YU_EC_U_A1 || hw->chip_rev == CHIP_REV_YU_EC_U_B0)) {
/* MAC Rx RAM Read is controlled by hardware */
sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
}
@ -1510,7 +1509,7 @@ static int sky2_down(struct net_device *dev)
/* WA for dev. #4.209 */
if (hw->chip_id == CHIP_ID_YUKON_EC_U
&& hw->chip_rev == CHIP_REV_YU_EC_U_A1)
&& (hw->chip_rev == CHIP_REV_YU_EC_U_A1 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
sky2->speed != SPEED_1000 ?
TX_STFW_ENA : TX_STFW_DIS);

9
drivers/net/sky2.h
View File

@ -383,8 +383,13 @@ enum {
CHIP_REV_YU_EC_A2 = 1, /* Chip Rev. for Yukon-EC A2 */
CHIP_REV_YU_EC_A3 = 2, /* Chip Rev. for Yukon-EC A3 */
CHIP_REV_YU_EC_U_A0 = 0,
CHIP_REV_YU_EC_U_A1 = 1,
CHIP_REV_YU_EC_U_A0 = 1,
CHIP_REV_YU_EC_U_A1 = 2,
CHIP_REV_YU_EC_U_B0 = 3,
CHIP_REV_YU_FE_A1 = 1,
CHIP_REV_YU_FE_A2 = 2,
};
/* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */