arm/dt: tegra devicetree support
Everything required to populate NVIDIA Tegra devices from the device tree. This patch adds a new DT_MACHINE_DESC() which matches against a tegra20 device tree. So far it only registers the on-chip devices, but it will be refined in follow on patches to configure clocks and pin IO from the device tree also. Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
This commit is contained in:
Grant Likely
parent
3ba7222ac9
commit
8e267f3da5
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@ -0,0 +1,70 @@
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/dts-v1/;
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/memreserve/ 0x1c000000 0x04000000;
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/include/ "tegra20.dtsi"
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/ {
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model = "NVIDIA Tegra2 Harmony evaluation board";
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compatible = "nvidia,harmony", "nvidia,tegra20";
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chosen {
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bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk0p2 rw rootwait";
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};
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memory@0 {
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reg = < 0x00000000 0x40000000 >;
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};
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i2c@7000c000 {
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clock-frequency = <400000>;
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codec: wm8903@1a {
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compatible = "wlf,wm8903";
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reg = <0x1a>;
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interrupts = < 347 >;
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gpio-controller;
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#gpio-cells = <2>;
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/* 0x8000 = Not configured */
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gpio-cfg = < 0x8000 0x8000 0 0x8000 0x8000 >;
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};
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};
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i2c@7000c400 {
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clock-frequency = <400000>;
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};
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i2c@7000c500 {
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clock-frequency = <400000>;
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};
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i2c@7000d000 {
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clock-frequency = <400000>;
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};
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sound {
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compatible = "nvidia,harmony-sound", "nvidia,tegra-wm8903";
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spkr-en-gpios = <&codec 2 0>;
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hp-det-gpios = <&gpio 178 0>;
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int-mic-en-gpios = <&gpio 184 0>;
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ext-mic-en-gpios = <&gpio 185 0>;
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};
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serial@70006300 {
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clock-frequency = < 216000000 >;
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};
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sdhci@c8000200 {
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gpios = <&gpio 69 0>, /* cd, gpio PI5 */
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<&gpio 57 0>, /* wp, gpio PH1 */
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<&gpio 155 0>; /* power, gpio PT3 */
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};
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sdhci@c8000600 {
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gpios = <&gpio 58 0>, /* cd, gpio PH2 */
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<&gpio 59 0>, /* wp, gpio PH3 */
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<&gpio 70 0>; /* power, gpio PI6 */
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};
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};
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@ -0,0 +1,28 @@
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/dts-v1/;
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/memreserve/ 0x1c000000 0x04000000;
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/include/ "tegra20.dtsi"
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/ {
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model = "NVIDIA Seaboard";
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compatible = "nvidia,seaboard", "nvidia,tegra20";
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chosen {
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bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk1p3 rw rootwait";
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};
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memory {
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device_type = "memory";
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reg = < 0x00000000 0x40000000 >;
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};
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serial@70006300 {
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clock-frequency = < 216000000 >;
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};
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sdhci@c8000400 {
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gpios = <&gpio 69 0>, /* cd, gpio PI5 */
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<&gpio 57 0>, /* wp, gpio PH1 */
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<&gpio 70 0>; /* power, gpio PI6 */
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};
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};
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@ -0,0 +1,139 @@
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/include/ "skeleton.dtsi"
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/ {
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compatible = "nvidia,tegra20";
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interrupt-parent = <&intc>;
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intc: interrupt-controller@50041000 {
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compatible = "nvidia,tegra20-gic";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = < 0x50041000 0x1000 >,
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< 0x50040100 0x0100 >;
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};
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i2c@7000c000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nvidia,tegra20-i2c";
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reg = <0x7000C000 0x100>;
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interrupts = < 70 >;
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};
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i2c@7000c400 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nvidia,tegra20-i2c";
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reg = <0x7000C400 0x100>;
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interrupts = < 116 >;
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};
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i2c@7000c500 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nvidia,tegra20-i2c";
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reg = <0x7000C500 0x100>;
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interrupts = < 124 >;
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};
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i2c@7000d000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nvidia,tegra20-i2c";
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reg = <0x7000D000 0x200>;
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interrupts = < 85 >;
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};
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i2s@70002800 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nvidia,tegra20-i2s";
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reg = <0x70002800 0x200>;
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interrupts = < 45 >;
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dma-channel = < 2 >;
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};
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i2s@70002a00 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nvidia,tegra20-i2s";
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reg = <0x70002a00 0x200>;
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interrupts = < 35 >;
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dma-channel = < 1 >;
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};
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das@70000c00 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "nvidia,tegra20-das";
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reg = <0x70000c00 0x80>;
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};
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gpio: gpio@6000d000 {
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compatible = "nvidia,tegra20-gpio";
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reg = < 0x6000d000 0x1000 >;
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interrupts = < 64 65 66 67 87 119 121 >;
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#gpio-cells = <2>;
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gpio-controller;
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};
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serial@70006000 {
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compatible = "nvidia,tegra20-uart";
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reg = <0x70006000 0x40>;
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reg-shift = <2>;
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interrupts = < 68 >;
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};
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serial@70006040 {
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compatible = "nvidia,tegra20-uart";
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reg = <0x70006040 0x40>;
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reg-shift = <2>;
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interrupts = < 69 >;
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};
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serial@70006200 {
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compatible = "nvidia,tegra20-uart";
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reg = <0x70006200 0x100>;
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reg-shift = <2>;
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interrupts = < 78 >;
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};
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serial@70006300 {
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compatible = "nvidia,tegra20-uart";
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reg = <0x70006300 0x100>;
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reg-shift = <2>;
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interrupts = < 122 >;
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};
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serial@70006400 {
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compatible = "nvidia,tegra20-uart";
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reg = <0x70006400 0x100>;
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reg-shift = <2>;
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interrupts = < 123 >;
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};
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sdhci@c8000000 {
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compatible = "nvidia,tegra20-sdhci";
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reg = <0xc8000000 0x200>;
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interrupts = < 46 >;
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};
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sdhci@c8000200 {
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compatible = "nvidia,tegra20-sdhci";
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reg = <0xc8000200 0x200>;
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interrupts = < 47 >;
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};
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sdhci@c8000400 {
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compatible = "nvidia,tegra20-sdhci";
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reg = <0xc8000400 0x200>;
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interrupts = < 51 >;
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};
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sdhci@c8000600 {
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compatible = "nvidia,tegra20-sdhci";
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reg = <0xc8000600 0x200>;
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interrupts = < 63 >;
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};
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};
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@ -51,6 +51,12 @@ config MACH_SEABOARD
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also be included for some of the derivative boards that
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have large similarities with the seaboard design.
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config MACH_TEGRA_DT
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bool "Generic Tegra board (FDT support)"
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select USE_OF
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help
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Support for generic nVidia Tegra boards using Flattened Device Tree
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config MACH_TRIMSLICE
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bool "TrimSlice board"
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select TEGRA_PCI
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@ -29,5 +29,8 @@ obj-${CONFIG_MACH_PAZ00} += board-paz00-pinmux.o
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obj-${CONFIG_MACH_SEABOARD} += board-seaboard.o
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obj-${CONFIG_MACH_SEABOARD} += board-seaboard-pinmux.o
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obj-${CONFIG_MACH_TEGRA_DT} += board-dt.o
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obj-${CONFIG_MACH_TEGRA_DT} += board-harmony-pinmux.o
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obj-${CONFIG_MACH_TRIMSLICE} += board-trimslice.o
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obj-${CONFIG_MACH_TRIMSLICE} += board-trimslice-pinmux.o
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@ -1,3 +1,6 @@
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zreladdr-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00008000
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params_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00000100
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initrd_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00800000
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dtb-$(CONFIG_MACH_HARMONY) += tegra-harmony.dtb
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dtb-$(CONFIG_MACH_SEABOARD) += tegra-seaboard.dtb
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@ -0,0 +1,119 @@
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/*
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* nVidia Tegra device tree board support
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*
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* Copyright (C) 2010 Secret Lab Technologies, Ltd.
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* Copyright (C) 2010 Google, Inc.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/serial_8250.h>
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#include <linux/clk.h>
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#include <linux/dma-mapping.h>
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#include <linux/irqdomain.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_fdt.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/pda_power.h>
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#include <linux/io.h>
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#include <linux/i2c.h>
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#include <linux/i2c-tegra.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/time.h>
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#include <asm/setup.h>
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#include <mach/iomap.h>
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#include <mach/irqs.h>
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#include "board.h"
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#include "board-harmony.h"
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#include "clock.h"
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#include "devices.h"
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void harmony_pinmux_init(void);
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void seaboard_pinmux_init(void);
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struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
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OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL),
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OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC2_BASE, "sdhci-tegra.1", NULL),
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OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC3_BASE, "sdhci-tegra.2", NULL),
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OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC4_BASE, "sdhci-tegra.3", NULL),
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OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C_BASE, "tegra-i2c.0", NULL),
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OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C2_BASE, "tegra-i2c.1", NULL),
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OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C3_BASE, "tegra-i2c.2", NULL),
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OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_DVC_BASE, "tegra-i2c.3", NULL),
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OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S1_BASE, "tegra-i2s.0", NULL),
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OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S1_BASE, "tegra-i2s.1", NULL),
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OF_DEV_AUXDATA("nvidia,tegra20-das", TEGRA_APB_MISC_DAS_BASE, "tegra-das", NULL),
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{}
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};
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static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
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/* name parent rate enabled */
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{ "uartd", "pll_p", 216000000, true },
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{ NULL, NULL, 0, 0},
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};
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static struct of_device_id tegra_dt_match_table[] __initdata = {
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{ .compatible = "simple-bus", },
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{}
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};
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static struct of_device_id tegra_dt_gic_match[] __initdata = {
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{ .compatible = "nvidia,tegra20-gic", },
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{}
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};
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static void __init tegra_dt_init(void)
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{
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struct device_node *node;
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node = of_find_matching_node_by_address(NULL, tegra_dt_gic_match,
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TEGRA_ARM_INT_DIST_BASE);
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if (node)
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irq_domain_add_simple(node, INT_GIC_BASE);
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tegra_clk_init_from_table(tegra_dt_clk_init_table);
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if (of_machine_is_compatible("nvidia,harmony"))
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harmony_pinmux_init();
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else if (of_machine_is_compatible("nvidia,seaboard"))
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seaboard_pinmux_init();
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/*
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* Finished with the static registrations now; fill in the missing
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* devices
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*/
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of_platform_populate(NULL, tegra_dt_match_table, tegra20_auxdata_lookup, NULL);
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}
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static const char * tegra_dt_board_compat[] = {
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"nvidia,harmony",
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"nvidia,seaboard",
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NULL
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};
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DT_MACHINE_START(TEGRA_DT, "nVidia Tegra (Flattened Device Tree)")
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.map_io = tegra_map_common_io,
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.init_early = tegra_init_early,
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.init_irq = tegra_init_irq,
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.timer = &tegra_timer,
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.init_machine = tegra_dt_init,
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.dt_compat = tegra_dt_board_compat,
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MACHINE_END
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Loading…
Reference in New Issue