Merge branch 'omap2-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6 into omap-all
This commit is contained in:
Russell King
Russell King
commit
8e5bdc44ba
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@ -101,7 +101,7 @@ static inline void omap_init_mbox(void) { }
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#if defined(CONFIG_OMAP_STI)
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#define OMAP1_STI_BASE IO_ADDRESS(0xfffea000)
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#define OMAP1_STI_BASE 0xfffea000
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#define OMAP1_STI_CHANNEL_BASE (OMAP1_STI_BASE + 0x400)
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static struct resource sti_resources[] = {
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@ -14,7 +14,10 @@ obj-$(CONFIG_ARCH_OMAP2420) += sram242x.o
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obj-$(CONFIG_ARCH_OMAP2430) += sram243x.o
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# Power Management
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obj-$(CONFIG_PM) += pm.o sleep.o
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ifeq ($(CONFIG_PM),y)
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obj-y += pm.o
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obj-$(CONFIG_ARCH_OMAP24XX) += sleep24xx.o
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endif
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# Clock framework
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obj-$(CONFIG_ARCH_OMAP2) += clock24xx.o
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@ -21,6 +21,7 @@
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/* The maximum error between a target DPLL rate and the rounded rate in Hz */
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#define DEFAULT_DPLL_RATE_TOLERANCE 50000
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int omap2_clk_init(void);
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int omap2_clk_enable(struct clk *clk);
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void omap2_clk_disable(struct clk *clk);
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long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
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@ -23,50 +23,7 @@
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#include <mach/board.h>
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#include <mach/mux.h>
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#include <mach/gpio.h>
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#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
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#define OMAP2_I2C_BASE2 0x48072000
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#define OMAP2_I2C_INT2 57
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static struct resource i2c_resources2[] = {
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{
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.start = OMAP2_I2C_BASE2,
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.end = OMAP2_I2C_BASE2 + 0x3f,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = OMAP2_I2C_INT2,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device omap_i2c_device2 = {
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.name = "i2c_omap",
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.id = 2,
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.num_resources = ARRAY_SIZE(i2c_resources2),
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.resource = i2c_resources2,
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};
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/* See also arch/arm/plat-omap/devices.c for first I2C on 24xx */
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static void omap_init_i2c(void)
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{
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/* REVISIT: Second I2C not in use on H4? */
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if (machine_is_omap_h4())
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return;
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if (!cpu_is_omap2430()) {
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omap_cfg_reg(J15_24XX_I2C2_SCL);
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omap_cfg_reg(H19_24XX_I2C2_SDA);
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}
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(void) platform_device_register(&omap_i2c_device2);
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}
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#else
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static void omap_init_i2c(void) {}
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#endif
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#include <mach/eac.h>
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#if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE)
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#define OMAP2_MBOX_BASE IO_ADDRESS(OMAP24XX_MAILBOX_BASE)
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@ -104,7 +61,9 @@ static inline void omap_init_mbox(void) { }
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#if defined(CONFIG_OMAP_STI)
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#define OMAP2_STI_BASE IO_ADDRESS(0x48068000)
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#if defined(CONFIG_ARCH_OMAP2)
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#define OMAP2_STI_BASE 0x48068000
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#define OMAP2_STI_CHANNEL_BASE 0x54000000
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#define OMAP2_STI_IRQ 4
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@ -124,6 +83,25 @@ static struct resource sti_resources[] = {
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.flags = IORESOURCE_IRQ,
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}
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};
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#elif defined(CONFIG_ARCH_OMAP3)
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#define OMAP3_SDTI_BASE 0x54500000
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#define OMAP3_SDTI_CHANNEL_BASE 0x54600000
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static struct resource sti_resources[] = {
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{
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.start = OMAP3_SDTI_BASE,
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.end = OMAP3_SDTI_BASE + 0xFFF,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = OMAP3_SDTI_CHANNEL_BASE,
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.end = OMAP3_SDTI_CHANNEL_BASE + SZ_1M - 1,
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.flags = IORESOURCE_MEM,
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}
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};
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#endif
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static struct platform_device sti_device = {
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.name = "sti",
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@ -140,12 +118,14 @@ static inline void omap_init_sti(void)
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static inline void omap_init_sti(void) {}
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#endif
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#if defined(CONFIG_SPI_OMAP24XX)
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#if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
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#include <mach/mcspi.h>
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#define OMAP2_MCSPI1_BASE 0x48098000
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#define OMAP2_MCSPI2_BASE 0x4809a000
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#define OMAP2_MCSPI3_BASE 0x480b8000
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#define OMAP2_MCSPI4_BASE 0x480ba000
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static struct omap2_mcspi_platform_config omap2_mcspi1_config = {
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.num_cs = 4,
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@ -159,7 +139,7 @@ static struct resource omap2_mcspi1_resources[] = {
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},
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};
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struct platform_device omap2_mcspi1 = {
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static struct platform_device omap2_mcspi1 = {
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.name = "omap2_mcspi",
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.id = 1,
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.num_resources = ARRAY_SIZE(omap2_mcspi1_resources),
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@ -181,7 +161,7 @@ static struct resource omap2_mcspi2_resources[] = {
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},
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};
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struct platform_device omap2_mcspi2 = {
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static struct platform_device omap2_mcspi2 = {
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.name = "omap2_mcspi",
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.id = 2,
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.num_resources = ARRAY_SIZE(omap2_mcspi2_resources),
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@ -191,16 +171,162 @@ struct platform_device omap2_mcspi2 = {
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},
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};
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#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
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static struct omap2_mcspi_platform_config omap2_mcspi3_config = {
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.num_cs = 2,
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};
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static struct resource omap2_mcspi3_resources[] = {
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{
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.start = OMAP2_MCSPI3_BASE,
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.end = OMAP2_MCSPI3_BASE + 0xff,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device omap2_mcspi3 = {
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.name = "omap2_mcspi",
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.id = 3,
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.num_resources = ARRAY_SIZE(omap2_mcspi3_resources),
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.resource = omap2_mcspi3_resources,
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.dev = {
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.platform_data = &omap2_mcspi3_config,
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},
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};
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#endif
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#ifdef CONFIG_ARCH_OMAP3
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static struct omap2_mcspi_platform_config omap2_mcspi4_config = {
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.num_cs = 1,
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};
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static struct resource omap2_mcspi4_resources[] = {
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{
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.start = OMAP2_MCSPI4_BASE,
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.end = OMAP2_MCSPI4_BASE + 0xff,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device omap2_mcspi4 = {
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.name = "omap2_mcspi",
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.id = 4,
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.num_resources = ARRAY_SIZE(omap2_mcspi4_resources),
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.resource = omap2_mcspi4_resources,
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.dev = {
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.platform_data = &omap2_mcspi4_config,
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},
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};
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#endif
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static void omap_init_mcspi(void)
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{
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platform_device_register(&omap2_mcspi1);
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platform_device_register(&omap2_mcspi2);
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#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
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platform_device_register(&omap2_mcspi3);
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#endif
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#ifdef CONFIG_ARCH_OMAP3
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platform_device_register(&omap2_mcspi4);
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#endif
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}
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#else
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static inline void omap_init_mcspi(void) {}
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#endif
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#ifdef CONFIG_SND_OMAP24XX_EAC
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#define OMAP2_EAC_BASE 0x48090000
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static struct resource omap2_eac_resources[] = {
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{
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.start = OMAP2_EAC_BASE,
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.end = OMAP2_EAC_BASE + 0x109,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device omap2_eac_device = {
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.name = "omap24xx-eac",
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.id = -1,
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.num_resources = ARRAY_SIZE(omap2_eac_resources),
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.resource = omap2_eac_resources,
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.dev = {
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.platform_data = NULL,
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},
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};
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void omap_init_eac(struct eac_platform_data *pdata)
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{
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omap2_eac_device.dev.platform_data = pdata;
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platform_device_register(&omap2_eac_device);
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}
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#else
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void omap_init_eac(struct eac_platform_data *pdata) {}
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#endif
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#ifdef CONFIG_OMAP_SHA1_MD5
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static struct resource sha1_md5_resources[] = {
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{
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.start = OMAP24XX_SEC_SHA1MD5_BASE,
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.end = OMAP24XX_SEC_SHA1MD5_BASE + 0x64,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = INT_24XX_SHA1MD5,
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.flags = IORESOURCE_IRQ,
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}
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};
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static struct platform_device sha1_md5_device = {
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.name = "OMAP SHA1/MD5",
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.id = -1,
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.num_resources = ARRAY_SIZE(sha1_md5_resources),
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.resource = sha1_md5_resources,
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};
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static void omap_init_sha1_md5(void)
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{
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platform_device_register(&sha1_md5_device);
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}
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#else
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static inline void omap_init_sha1_md5(void) { }
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#endif
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#if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
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#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
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#define OMAP_HDQ_BASE 0x480B2000
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#endif
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static struct resource omap_hdq_resources[] = {
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{
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.start = OMAP_HDQ_BASE,
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.end = OMAP_HDQ_BASE + 0x1C,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = INT_24XX_HDQ_IRQ,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device omap_hdq_dev = {
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.name = "omap_hdq",
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.id = 0,
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.dev = {
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.platform_data = NULL,
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},
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.num_resources = ARRAY_SIZE(omap_hdq_resources),
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.resource = omap_hdq_resources,
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};
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static inline void omap_hdq_init(void)
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{
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(void) platform_device_register(&omap_hdq_dev);
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}
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#else
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static inline void omap_hdq_init(void) {}
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#endif
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/*-------------------------------------------------------------------------*/
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static int __init omap2_init_devices(void)
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@ -208,10 +334,11 @@ static int __init omap2_init_devices(void)
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/* please keep these calls, and their implementations above,
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* in alphabetical order so they're easier to sort through.
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*/
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omap_init_i2c();
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omap_init_mbox();
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omap_init_mcspi();
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omap_hdq_init();
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omap_init_sti();
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omap_init_sha1_md5();
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return 0;
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}
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@ -9,27 +9,23 @@
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#undef DEBUG
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/ioport.h>
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#include <linux/spinlock.h>
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#include <linux/module.h>
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#include <asm/io.h>
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#include <asm/mach-types.h>
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#include <mach/gpmc.h>
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#undef DEBUG
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#ifdef CONFIG_ARCH_OMAP2420
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#define GPMC_BASE 0x6800a000
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#endif
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#ifdef CONFIG_ARCH_OMAP2430
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#define GPMC_BASE 0x6E000000
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#endif
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#include <mach/sdrc.h>
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/* GPMC register offsets */
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#define GPMC_REVISION 0x00
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#define GPMC_SYSCONFIG 0x10
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#define GPMC_SYSSTATUS 0x14
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@ -51,7 +47,6 @@
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#define GPMC_CS0 0x60
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#define GPMC_CS_SIZE 0x30
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#define GPMC_CS_NUM 8
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#define GPMC_MEM_START 0x00000000
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#define GPMC_MEM_END 0x3FFFFFFF
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#define BOOT_ROM_SPACE 0x100000 /* 1MB */
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@ -64,10 +59,9 @@ static struct resource gpmc_cs_mem[GPMC_CS_NUM];
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static DEFINE_SPINLOCK(gpmc_mem_lock);
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static unsigned gpmc_cs_map;
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static void __iomem *gpmc_base = IO_ADDRESS(GPMC_BASE);
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static void __iomem *gpmc_cs_base = IO_ADDRESS(GPMC_BASE) + GPMC_CS0;
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static void __iomem *gpmc_base;
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static struct clk *gpmc_fck;
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static struct clk *gpmc_l3_clk;
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static void gpmc_write_reg(int idx, u32 val)
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{
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@ -83,19 +77,32 @@ void gpmc_cs_write_reg(int cs, int idx, u32 val)
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{
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void __iomem *reg_addr;
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reg_addr = gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx;
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reg_addr = gpmc_base + GPMC_CS0 + (cs * GPMC_CS_SIZE) + idx;
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__raw_writel(val, reg_addr);
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}
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u32 gpmc_cs_read_reg(int cs, int idx)
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{
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return __raw_readl(gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx);
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void __iomem *reg_addr;
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reg_addr = gpmc_base + GPMC_CS0 + (cs * GPMC_CS_SIZE) + idx;
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return __raw_readl(reg_addr);
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}
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/* TODO: Add support for gpmc_fck to clock framework and use it */
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unsigned long gpmc_get_fclk_period(void)
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{
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/* In picoseconds */
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return 1000000000 / ((clk_get_rate(gpmc_fck)) / 1000);
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unsigned long rate = clk_get_rate(gpmc_l3_clk);
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if (rate == 0) {
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printk(KERN_WARNING "gpmc_l3_clk not enabled\n");
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return 0;
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}
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rate /= 1000;
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rate = 1000000000 / rate; /* In picoseconds */
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return rate;
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}
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unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
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@ -108,6 +115,11 @@ unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
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return (time_ns * 1000 + tick_ps - 1) / tick_ps;
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}
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unsigned int gpmc_ticks_to_ns(unsigned int ticks)
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{
|
||||
return ticks * gpmc_get_fclk_period() / 1000;
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}
|
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|
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unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
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{
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||||
unsigned long ticks = gpmc_ns_to_ticks(time_ns);
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@ -348,6 +360,7 @@ out:
|
|||
spin_unlock(&gpmc_mem_lock);
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return r;
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||||
}
|
||||
EXPORT_SYMBOL(gpmc_cs_request);
|
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|
||||
void gpmc_cs_free(int cs)
|
||||
{
|
||||
|
|
@ -363,8 +376,9 @@ void gpmc_cs_free(int cs)
|
|||
gpmc_cs_set_reserved(cs, 0);
|
||||
spin_unlock(&gpmc_mem_lock);
|
||||
}
|
||||
EXPORT_SYMBOL(gpmc_cs_free);
|
||||
|
||||
void __init gpmc_mem_init(void)
|
||||
static void __init gpmc_mem_init(void)
|
||||
{
|
||||
int cs;
|
||||
unsigned long boot_rom_space = 0;
|
||||
|
|
@ -394,12 +408,33 @@ void __init gpmc_mem_init(void)
|
|||
void __init gpmc_init(void)
|
||||
{
|
||||
u32 l;
|
||||
char *ck;
|
||||
|
||||
gpmc_fck = clk_get(NULL, "gpmc_fck"); /* Always on ENABLE_ON_INIT */
|
||||
if (IS_ERR(gpmc_fck))
|
||||
WARN_ON(1);
|
||||
else
|
||||
clk_enable(gpmc_fck);
|
||||
if (cpu_is_omap24xx()) {
|
||||
ck = "core_l3_ck";
|
||||
if (cpu_is_omap2420())
|
||||
l = OMAP2420_GPMC_BASE;
|
||||
else
|
||||
l = OMAP34XX_GPMC_BASE;
|
||||
} else if (cpu_is_omap34xx()) {
|
||||
ck = "gpmc_fck";
|
||||
l = OMAP34XX_GPMC_BASE;
|
||||
}
|
||||
|
||||
gpmc_l3_clk = clk_get(NULL, ck);
|
||||
if (IS_ERR(gpmc_l3_clk)) {
|
||||
printk(KERN_ERR "Could not get GPMC clock %s\n", ck);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
gpmc_base = ioremap(l, SZ_4K);
|
||||
if (!gpmc_base) {
|
||||
clk_put(gpmc_l3_clk);
|
||||
printk(KERN_ERR "Could not get GPMC register memory\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
BUG_ON(IS_ERR(gpmc_l3_clk));
|
||||
|
||||
l = gpmc_read_reg(GPMC_REVISION);
|
||||
printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
|
||||
|
|
|
|||
|
|
@ -17,24 +17,15 @@
|
|||
|
||||
#include <asm/io.h>
|
||||
|
||||
#include <mach/common.h>
|
||||
#include <mach/control.h>
|
||||
#include <mach/cpu.h>
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP2420)
|
||||
#define TAP_BASE IO_ADDRESS(0x48014000)
|
||||
#elif defined(CONFIG_ARCH_OMAP2430)
|
||||
#define TAP_BASE IO_ADDRESS(0x4900A000)
|
||||
#elif defined(CONFIG_ARCH_OMAP34XX)
|
||||
#define TAP_BASE IO_ADDRESS(0x4830A000)
|
||||
#endif
|
||||
static u32 class;
|
||||
static void __iomem *tap_base;
|
||||
static u16 tap_prod_id;
|
||||
|
||||
#define OMAP_TAP_IDCODE 0x0204
|
||||
#if defined(CONFIG_ARCH_OMAP34XX)
|
||||
#define OMAP_TAP_PROD_ID 0x0210
|
||||
#else
|
||||
#define OMAP_TAP_PROD_ID 0x0208
|
||||
#endif
|
||||
|
||||
#define OMAP_TAP_DIE_ID_0 0x0218
|
||||
#define OMAP_TAP_DIE_ID_1 0x021C
|
||||
#define OMAP_TAP_DIE_ID_2 0x0220
|
||||
|
|
@ -93,18 +84,24 @@ static u32 __init read_tap_reg(int reg)
|
|||
* it means its Cortex r0p0 which is 3430 ES1
|
||||
*/
|
||||
if ((((cpuid >> 4) & 0xFFF) == 0xC08) && ((cpuid & 0xF) == 0x0)) {
|
||||
|
||||
if (reg == tap_prod_id) {
|
||||
regval = 0x000F00F0;
|
||||
goto out;
|
||||
}
|
||||
|
||||
switch (reg) {
|
||||
case OMAP_TAP_IDCODE : regval = 0x0B7AE02F; break;
|
||||
/* Making DevType as 0xF in ES1 to differ from ES2 */
|
||||
case OMAP_TAP_PROD_ID : regval = 0x000F00F0; break;
|
||||
case OMAP_TAP_DIE_ID_0: regval = 0x01000000; break;
|
||||
case OMAP_TAP_DIE_ID_1: regval = 0x1012d687; break;
|
||||
case OMAP_TAP_DIE_ID_2: regval = 0x00000000; break;
|
||||
case OMAP_TAP_DIE_ID_3: regval = 0x2d2c0000; break;
|
||||
}
|
||||
} else
|
||||
regval = __raw_readl(TAP_BASE + reg);
|
||||
regval = __raw_readl(tap_base + reg);
|
||||
|
||||
out:
|
||||
return regval;
|
||||
|
||||
}
|
||||
|
|
@ -203,7 +200,7 @@ void __init omap2_check_revision(void)
|
|||
u8 rev;
|
||||
|
||||
idcode = read_tap_reg(OMAP_TAP_IDCODE);
|
||||
prod_id = read_tap_reg(OMAP_TAP_PROD_ID);
|
||||
prod_id = read_tap_reg(tap_prod_id);
|
||||
hawkeye = (idcode >> 12) & 0xffff;
|
||||
rev = (idcode >> 28) & 0x0f;
|
||||
dev_type = (prod_id >> 16) & 0x0f;
|
||||
|
|
@ -268,3 +265,13 @@ void __init omap2_check_revision(void)
|
|||
|
||||
}
|
||||
|
||||
void __init omap2_set_globals_tap(struct omap_globals *omap2_globals)
|
||||
{
|
||||
class = omap2_globals->class;
|
||||
tap_base = omap2_globals->tap;
|
||||
|
||||
if (class == 0x3430)
|
||||
tap_prod_id = 0x0210;
|
||||
else
|
||||
tap_prod_id = 0x0208;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -4,8 +4,11 @@
|
|||
* OMAP2 I/O mapping code
|
||||
*
|
||||
* Copyright (C) 2005 Nokia Corporation
|
||||
* Author: Juha Yrjölä <juha.yrjola@nokia.com>
|
||||
* Updated map desc to add 2430 support : <x0khasim@ti.com>
|
||||
* Copyright (C) 2007 Texas Instruments
|
||||
*
|
||||
* Author:
|
||||
* Juha Yrjola <juha.yrjola@nokia.com>
|
||||
* Syed Khasim <x0khasim@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
|
|
@ -23,6 +26,11 @@
|
|||
|
||||
#include <mach/mux.h>
|
||||
#include <mach/omapfb.h>
|
||||
#include <mach/sram.h>
|
||||
|
||||
#include "memory.h"
|
||||
|
||||
#include "clock.h"
|
||||
|
||||
#include <mach/powerdomain.h>
|
||||
|
||||
|
|
@ -31,13 +39,6 @@
|
|||
#include <mach/clockdomain.h>
|
||||
#include "clockdomains.h"
|
||||
|
||||
extern void omap_sram_init(void);
|
||||
extern int omap2_clk_init(void);
|
||||
extern void omap2_check_revision(void);
|
||||
extern void omap2_init_memory(void);
|
||||
extern void gpmc_init(void);
|
||||
extern void omapfb_reserve_sdram(void);
|
||||
|
||||
/*
|
||||
* The machine specific code may provide the extra mapping besides the
|
||||
* default mapping provided here.
|
||||
|
|
|
|||
|
|
@ -13,17 +13,23 @@
|
|||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/io.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <asm/mach/irq.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#define INTC_REVISION 0x0000
|
||||
#define INTC_SYSCONFIG 0x0010
|
||||
#define INTC_SYSSTATUS 0x0014
|
||||
#define INTC_CONTROL 0x0048
|
||||
#define INTC_MIR_CLEAR0 0x0088
|
||||
#define INTC_MIR_SET0 0x008c
|
||||
|
||||
/* selected INTC register offsets */
|
||||
|
||||
#define INTC_REVISION 0x0000
|
||||
#define INTC_SYSCONFIG 0x0010
|
||||
#define INTC_SYSSTATUS 0x0014
|
||||
#define INTC_CONTROL 0x0048
|
||||
#define INTC_MIR_CLEAR0 0x0088
|
||||
#define INTC_MIR_SET0 0x008c
|
||||
#define INTC_PENDING_IRQ0 0x0098
|
||||
|
||||
/* Number of IRQ state bits in each MIR register */
|
||||
#define IRQ_BITS_PER_REG 32
|
||||
|
||||
/*
|
||||
* OMAP2 has a number of different interrupt controllers, each interrupt
|
||||
|
|
@ -37,43 +43,45 @@ static struct omap_irq_bank {
|
|||
} __attribute__ ((aligned(4))) irq_banks[] = {
|
||||
{
|
||||
/* MPU INTC */
|
||||
.base_reg = IO_ADDRESS(OMAP24XX_IC_BASE),
|
||||
.base_reg = 0,
|
||||
.nr_irqs = 96,
|
||||
}, {
|
||||
/* XXX: DSP INTC */
|
||||
}
|
||||
},
|
||||
};
|
||||
|
||||
/* INTC bank register get/set */
|
||||
|
||||
static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
|
||||
{
|
||||
__raw_writel(val, bank->base_reg + reg);
|
||||
}
|
||||
|
||||
static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg)
|
||||
{
|
||||
return __raw_readl(bank->base_reg + reg);
|
||||
}
|
||||
|
||||
/* XXX: FIQ and additional INTC support (only MPU at the moment) */
|
||||
static void omap_ack_irq(unsigned int irq)
|
||||
{
|
||||
__raw_writel(0x1, irq_banks[0].base_reg + INTC_CONTROL);
|
||||
intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL);
|
||||
}
|
||||
|
||||
static void omap_mask_irq(unsigned int irq)
|
||||
{
|
||||
int offset = (irq >> 5) << 5;
|
||||
int offset = irq & (~(IRQ_BITS_PER_REG - 1));
|
||||
|
||||
if (irq >= 64) {
|
||||
irq %= 64;
|
||||
} else if (irq >= 32) {
|
||||
irq %= 32;
|
||||
}
|
||||
irq &= (IRQ_BITS_PER_REG - 1);
|
||||
|
||||
__raw_writel(1 << irq, irq_banks[0].base_reg + INTC_MIR_SET0 + offset);
|
||||
intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_SET0 + offset);
|
||||
}
|
||||
|
||||
static void omap_unmask_irq(unsigned int irq)
|
||||
{
|
||||
int offset = (irq >> 5) << 5;
|
||||
int offset = irq & (~(IRQ_BITS_PER_REG - 1));
|
||||
|
||||
if (irq >= 64) {
|
||||
irq %= 64;
|
||||
} else if (irq >= 32) {
|
||||
irq %= 32;
|
||||
}
|
||||
irq &= (IRQ_BITS_PER_REG - 1);
|
||||
|
||||
__raw_writel(1 << irq, irq_banks[0].base_reg + INTC_MIR_CLEAR0 + offset);
|
||||
intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_CLEAR0 + offset);
|
||||
}
|
||||
|
||||
static void omap_mask_ack_irq(unsigned int irq)
|
||||
|
|
@ -93,20 +101,20 @@ static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
|
|||
{
|
||||
unsigned long tmp;
|
||||
|
||||
tmp = __raw_readl(bank->base_reg + INTC_REVISION) & 0xff;
|
||||
tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff;
|
||||
printk(KERN_INFO "IRQ: Found an INTC at 0x%p "
|
||||
"(revision %ld.%ld) with %d interrupts\n",
|
||||
bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
|
||||
|
||||
tmp = __raw_readl(bank->base_reg + INTC_SYSCONFIG);
|
||||
tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG);
|
||||
tmp |= 1 << 1; /* soft reset */
|
||||
__raw_writel(tmp, bank->base_reg + INTC_SYSCONFIG);
|
||||
intc_bank_write_reg(tmp, bank, INTC_SYSCONFIG);
|
||||
|
||||
while (!(__raw_readl(bank->base_reg + INTC_SYSSTATUS) & 0x1))
|
||||
while (!(intc_bank_read_reg(bank, INTC_SYSSTATUS) & 0x1))
|
||||
/* Wait for reset to complete */;
|
||||
|
||||
/* Enable autoidle */
|
||||
__raw_writel(1 << 0, bank->base_reg + INTC_SYSCONFIG);
|
||||
intc_bank_write_reg(1 << 0, bank, INTC_SYSCONFIG);
|
||||
}
|
||||
|
||||
void __init omap_init_irq(void)
|
||||
|
|
@ -118,9 +126,8 @@ void __init omap_init_irq(void)
|
|||
for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
|
||||
struct omap_irq_bank *bank = irq_banks + i;
|
||||
|
||||
/* XXX */
|
||||
if (!bank->base_reg)
|
||||
continue;
|
||||
if (cpu_is_omap24xx())
|
||||
bank->base_reg = OMAP2_IO_ADDRESS(OMAP24XX_IC_BASE);
|
||||
|
||||
omap_irq_bank_init_one(bank);
|
||||
|
||||
|
|
|
|||
|
|
@ -14,6 +14,9 @@
|
|||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef ARCH_ARM_MACH_OMAP2_MEMORY_H
|
||||
#define ARCH_ARM_MACH_OMAP2_MEMORY_H
|
||||
|
||||
/* Memory timings */
|
||||
#define M_DDR 1
|
||||
#define M_LOCK_CTRL (1 << 2)
|
||||
|
|
@ -34,3 +37,7 @@ extern u32 omap2_memory_get_fast_dll_ctrl(void);
|
|||
extern u32 omap2_memory_get_type(void);
|
||||
u32 omap2_dll_force_needed(void);
|
||||
u32 omap2_reprogram_sdrc(u32 level, u32 force);
|
||||
void __init omap2_init_memory(void);
|
||||
void __init gpmc_init(void);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-omap2/mux.c
|
||||
*
|
||||
* OMAP2 pin multiplexing configurations
|
||||
* OMAP2 and OMAP3 pin multiplexing configurations
|
||||
*
|
||||
* Copyright (C) 2004 - 2008 Texas Instruments Inc.
|
||||
* Copyright (C) 2003 - 2008 Nokia Corporation
|
||||
|
|
@ -219,16 +219,179 @@ MUX_CFG_24XX("AD13_2430_MCBSP2_DR_OFF", 0x0131, 0, 0, 0, 1)
|
|||
#define OMAP24XX_PINS_SZ 0
|
||||
#endif /* CONFIG_ARCH_OMAP24XX */
|
||||
|
||||
#define OMAP24XX_PULL_ENA (1 << 3)
|
||||
#define OMAP24XX_PULL_UP (1 << 4)
|
||||
#ifdef CONFIG_ARCH_OMAP34XX
|
||||
static struct pin_config __initdata_or_module omap34xx_pins[] = {
|
||||
/*
|
||||
* Name, reg-offset,
|
||||
* mux-mode | [active-mode | off-mode]
|
||||
*/
|
||||
|
||||
/* 34xx I2C */
|
||||
MUX_CFG_34XX("K21_34XX_I2C1_SCL", 0x1ba,
|
||||
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
|
||||
MUX_CFG_34XX("J21_34XX_I2C1_SDA", 0x1bc,
|
||||
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
|
||||
MUX_CFG_34XX("AF15_34XX_I2C2_SCL", 0x1be,
|
||||
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
|
||||
MUX_CFG_34XX("AE15_34XX_I2C2_SDA", 0x1c0,
|
||||
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
|
||||
MUX_CFG_34XX("AF14_34XX_I2C3_SCL", 0x1c2,
|
||||
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
|
||||
MUX_CFG_34XX("AG14_34XX_I2C3_SDA", 0x1c4,
|
||||
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
|
||||
MUX_CFG_34XX("AD26_34XX_I2C4_SCL", 0xa00,
|
||||
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
|
||||
MUX_CFG_34XX("AE26_34XX_I2C4_SDA", 0xa02,
|
||||
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
|
||||
|
||||
/* PHY - HSUSB: 12-pin ULPI PHY: Port 1*/
|
||||
MUX_CFG_34XX("Y8_3430_USB1HS_PHY_CLK", 0x5da,
|
||||
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT)
|
||||
MUX_CFG_34XX("Y9_3430_USB1HS_PHY_STP", 0x5d8,
|
||||
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT)
|
||||
MUX_CFG_34XX("AA14_3430_USB1HS_PHY_DIR", 0x5ec,
|
||||
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("AA11_3430_USB1HS_PHY_NXT", 0x5ee,
|
||||
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("W13_3430_USB1HS_PHY_D0", 0x5dc,
|
||||
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("W12_3430_USB1HS_PHY_D1", 0x5de,
|
||||
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("W11_3430_USB1HS_PHY_D2", 0x5e0,
|
||||
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("Y11_3430_USB1HS_PHY_D3", 0x5ea,
|
||||
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("W9_3430_USB1HS_PHY_D4", 0x5e4,
|
||||
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("Y12_3430_USB1HS_PHY_D5", 0x5e6,
|
||||
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("W8_3430_USB1HS_PHY_D6", 0x5e8,
|
||||
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("Y13_3430_USB1HS_PHY_D7", 0x5e2,
|
||||
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
|
||||
/* PHY - HSUSB: 12-pin ULPI PHY: Port 2*/
|
||||
MUX_CFG_34XX("AA8_3430_USB2HS_PHY_CLK", 0x5f0,
|
||||
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT)
|
||||
MUX_CFG_34XX("AA10_3430_USB2HS_PHY_STP", 0x5f2,
|
||||
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT)
|
||||
MUX_CFG_34XX("AA9_3430_USB2HS_PHY_DIR", 0x5f4,
|
||||
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("AB11_3430_USB2HS_PHY_NXT", 0x5f6,
|
||||
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("AB10_3430_USB2HS_PHY_D0", 0x5f8,
|
||||
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("AB9_3430_USB2HS_PHY_D1", 0x5fa,
|
||||
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("W3_3430_USB2HS_PHY_D2", 0x1d4,
|
||||
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("T4_3430_USB2HS_PHY_D3", 0x1de,
|
||||
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("T3_3430_USB2HS_PHY_D4", 0x1d8,
|
||||
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("R3_3430_USB2HS_PHY_D5", 0x1da,
|
||||
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("R4_3430_USB2HS_PHY_D6", 0x1dc,
|
||||
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("T2_3430_USB2HS_PHY_D7", 0x1d6,
|
||||
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
|
||||
/* TLL - HSUSB: 12-pin TLL Port 1*/
|
||||
MUX_CFG_34XX("Y8_3430_USB1HS_TLL_CLK", 0x5da,
|
||||
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT)
|
||||
MUX_CFG_34XX("Y9_3430_USB1HS_TLL_STP", 0x5d8,
|
||||
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("AA14_3430_USB1HS_TLL_DIR", 0x5ec,
|
||||
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT)
|
||||
MUX_CFG_34XX("AA11_3430_USB1HS_TLL_NXT", 0x5ee,
|
||||
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT)
|
||||
MUX_CFG_34XX("W13_3430_USB1HS_TLL_D0", 0x5dc,
|
||||
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("W12_3430_USB1HS_TLL_D1", 0x5de,
|
||||
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("W11_3430_USB1HS_TLL_D2", 0x5e0,
|
||||
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("Y11_3430_USB1HS_TLL_D3", 0x5ea,
|
||||
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("W9_3430_USB1HS_TLL_D4", 0x5e4,
|
||||
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("Y12_3430_USB1HS_TLL_D5", 0x5e6,
|
||||
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("W8_3430_USB1HS_TLL_D6", 0x5e8,
|
||||
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("Y13_3430_USB1HS_TLL_D7", 0x5e2,
|
||||
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
|
||||
/* TLL - HSUSB: 12-pin TLL Port 2*/
|
||||
MUX_CFG_34XX("AA8_3430_USB2HS_TLL_CLK", 0x5f0,
|
||||
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT)
|
||||
MUX_CFG_34XX("AA10_3430_USB2HS_TLL_STP", 0x5f2,
|
||||
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("AA9_3430_USB2HS_TLL_DIR", 0x5f4,
|
||||
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT)
|
||||
MUX_CFG_34XX("AB11_3430_USB2HS_TLL_NXT", 0x5f6,
|
||||
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT)
|
||||
MUX_CFG_34XX("AB10_3430_USB2HS_TLL_D0", 0x5f8,
|
||||
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("AB9_3430_USB2HS_TLL_D1", 0x5fa,
|
||||
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("W3_3430_USB2HS_TLL_D2", 0x1d4,
|
||||
OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("T4_3430_USB2HS_TLL_D3", 0x1de,
|
||||
OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("T3_3430_USB2HS_TLL_D4", 0x1d8,
|
||||
OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("R3_3430_USB2HS_TLL_D5", 0x1da,
|
||||
OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("R4_3430_USB2HS_TLL_D6", 0x1dc,
|
||||
OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("T2_3430_USB2HS_TLL_D7", 0x1d6,
|
||||
OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
|
||||
/* TLL - HSUSB: 12-pin TLL Port 3*/
|
||||
MUX_CFG_34XX("AA6_3430_USB3HS_TLL_CLK", 0x180,
|
||||
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_OUTPUT)
|
||||
MUX_CFG_34XX("AB3_3430_USB3HS_TLL_STP", 0x166,
|
||||
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("AA3_3430_USB3HS_TLL_DIR", 0x168,
|
||||
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_OUTPUT)
|
||||
MUX_CFG_34XX("Y3_3430_USB3HS_TLL_NXT", 0x16a,
|
||||
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_OUTPUT)
|
||||
MUX_CFG_34XX("AA5_3430_USB3HS_TLL_D0", 0x186,
|
||||
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("Y4_3430_USB3HS_TLL_D1", 0x184,
|
||||
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("Y5_3430_USB3HS_TLL_D2", 0x188,
|
||||
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("W5_3430_USB3HS_TLL_D3", 0x18a,
|
||||
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("AB12_3430_USB3HS_TLL_D4", 0x16c,
|
||||
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("AB13_3430_USB3HS_TLL_D5", 0x16e,
|
||||
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("AA13_3430_USB3HS_TLL_D6", 0x170,
|
||||
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
MUX_CFG_34XX("AA12_3430_USB3HS_TLL_D7", 0x172,
|
||||
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
|
||||
};
|
||||
|
||||
#define OMAP34XX_PINS_SZ ARRAY_SIZE(omap34xx_pins)
|
||||
|
||||
#else
|
||||
#define omap34xx_pins NULL
|
||||
#define OMAP34XX_PINS_SZ 0
|
||||
#endif /* CONFIG_ARCH_OMAP34XX */
|
||||
|
||||
#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
|
||||
void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u8 reg)
|
||||
static void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u16 reg)
|
||||
{
|
||||
u16 orig;
|
||||
u8 warn = 0, debug = 0;
|
||||
|
||||
orig = omap_ctrl_readb(cfg->mux_reg);
|
||||
if (cpu_is_omap24xx())
|
||||
orig = omap_ctrl_readb(cfg->mux_reg);
|
||||
else
|
||||
orig = omap_ctrl_readw(cfg->mux_reg);
|
||||
|
||||
#ifdef CONFIG_OMAP_MUX_DEBUG
|
||||
debug = cfg->debug;
|
||||
|
|
@ -254,9 +417,9 @@ int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg)
|
|||
spin_lock_irqsave(&mux_spin_lock, flags);
|
||||
reg |= cfg->mask & 0x7;
|
||||
if (cfg->pull_val)
|
||||
reg |= OMAP24XX_PULL_ENA;
|
||||
reg |= OMAP2_PULL_ENA;
|
||||
if (cfg->pu_pd_val)
|
||||
reg |= OMAP24XX_PULL_UP;
|
||||
reg |= OMAP2_PULL_UP;
|
||||
omap2_cfg_debug(cfg, reg);
|
||||
omap_ctrl_writeb(reg, cfg->mux_reg);
|
||||
spin_unlock_irqrestore(&mux_spin_lock, flags);
|
||||
|
|
@ -264,7 +427,26 @@ int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg)
|
|||
return 0;
|
||||
}
|
||||
#else
|
||||
#define omap24xx_cfg_reg 0
|
||||
#define omap24xx_cfg_reg NULL
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP34XX
|
||||
static int __init_or_module omap34xx_cfg_reg(const struct pin_config *cfg)
|
||||
{
|
||||
static DEFINE_SPINLOCK(mux_spin_lock);
|
||||
unsigned long flags;
|
||||
u16 reg = 0;
|
||||
|
||||
spin_lock_irqsave(&mux_spin_lock, flags);
|
||||
reg |= cfg->mux_val;
|
||||
omap2_cfg_debug(cfg, reg);
|
||||
omap_ctrl_writew(reg, cfg->mux_reg);
|
||||
spin_unlock_irqrestore(&mux_spin_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
#define omap34xx_cfg_reg NULL
|
||||
#endif
|
||||
|
||||
int __init omap2_mux_init(void)
|
||||
|
|
@ -273,6 +455,10 @@ int __init omap2_mux_init(void)
|
|||
arch_mux_cfg.pins = omap24xx_pins;
|
||||
arch_mux_cfg.size = OMAP24XX_PINS_SZ;
|
||||
arch_mux_cfg.cfg_reg = omap24xx_cfg_reg;
|
||||
} else if (cpu_is_omap34xx()) {
|
||||
arch_mux_cfg.pins = omap34xx_pins;
|
||||
arch_mux_cfg.size = OMAP34XX_PINS_SZ;
|
||||
arch_mux_cfg.cfg_reg = omap34xx_cfg_reg;
|
||||
}
|
||||
|
||||
return omap_mux_register(&arch_mux_cfg);
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
*
|
||||
* OMAP2 serial support.
|
||||
*
|
||||
* Copyright (C) 2005 Nokia Corporation
|
||||
* Copyright (C) 2005-2008 Nokia Corporation
|
||||
* Author: Paul Mundt <paul.mundt@nokia.com>
|
||||
*
|
||||
* Based off of arch/arm/mach-omap/omap1/serial.c
|
||||
|
|
@ -23,12 +23,8 @@
|
|||
#include <mach/common.h>
|
||||
#include <mach/board.h>
|
||||
|
||||
static struct clk * uart1_ick = NULL;
|
||||
static struct clk * uart1_fck = NULL;
|
||||
static struct clk * uart2_ick = NULL;
|
||||
static struct clk * uart2_fck = NULL;
|
||||
static struct clk * uart3_ick = NULL;
|
||||
static struct clk * uart3_fck = NULL;
|
||||
static struct clk *uart_ick[OMAP_MAX_NR_PORTS];
|
||||
static struct clk *uart_fck[OMAP_MAX_NR_PORTS];
|
||||
|
||||
static struct plat_serial8250_port serial_platform_data[] = {
|
||||
{
|
||||
|
|
@ -38,7 +34,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
|
|||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.iotype = UPIO_MEM,
|
||||
.regshift = 2,
|
||||
.uartclk = OMAP16XX_BASE_BAUD * 16,
|
||||
.uartclk = OMAP24XX_BASE_BAUD * 16,
|
||||
}, {
|
||||
.membase = IO_ADDRESS(OMAP_UART2_BASE),
|
||||
.mapbase = OMAP_UART2_BASE,
|
||||
|
|
@ -46,7 +42,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
|
|||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.iotype = UPIO_MEM,
|
||||
.regshift = 2,
|
||||
.uartclk = OMAP16XX_BASE_BAUD * 16,
|
||||
.uartclk = OMAP24XX_BASE_BAUD * 16,
|
||||
}, {
|
||||
.membase = IO_ADDRESS(OMAP_UART3_BASE),
|
||||
.mapbase = OMAP_UART3_BASE,
|
||||
|
|
@ -54,7 +50,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
|
|||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.iotype = UPIO_MEM,
|
||||
.regshift = 2,
|
||||
.uartclk = OMAP16XX_BASE_BAUD * 16,
|
||||
.uartclk = OMAP24XX_BASE_BAUD * 16,
|
||||
}, {
|
||||
.flags = 0
|
||||
}
|
||||
|
|
@ -87,10 +83,27 @@ static inline void __init omap_serial_reset(struct plat_serial8250_port *p)
|
|||
serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0));
|
||||
}
|
||||
|
||||
void __init omap_serial_init()
|
||||
void omap_serial_enable_clocks(int enable)
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
|
||||
if (uart_ick[i] && uart_fck[i]) {
|
||||
if (enable) {
|
||||
clk_enable(uart_ick[i]);
|
||||
clk_enable(uart_fck[i]);
|
||||
} else {
|
||||
clk_disable(uart_ick[i]);
|
||||
clk_disable(uart_fck[i]);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void __init omap_serial_init(void)
|
||||
{
|
||||
int i;
|
||||
const struct omap_uart_config *info;
|
||||
char name[16];
|
||||
|
||||
/*
|
||||
* Make sure the serial ports are muxed on at this point.
|
||||
|
|
@ -98,8 +111,7 @@ void __init omap_serial_init()
|
|||
* if not needed.
|
||||
*/
|
||||
|
||||
info = omap_get_config(OMAP_TAG_UART,
|
||||
struct omap_uart_config);
|
||||
info = omap_get_config(OMAP_TAG_UART, struct omap_uart_config);
|
||||
|
||||
if (info == NULL)
|
||||
return;
|
||||
|
|
@ -113,53 +125,21 @@ void __init omap_serial_init()
|
|||
continue;
|
||||
}
|
||||
|
||||
switch (i) {
|
||||
case 0:
|
||||
uart1_ick = clk_get(NULL, "uart1_ick");
|
||||
if (IS_ERR(uart1_ick))
|
||||
printk("Could not get uart1_ick\n");
|
||||
else {
|
||||
clk_enable(uart1_ick);
|
||||
}
|
||||
sprintf(name, "uart%d_ick", i+1);
|
||||
uart_ick[i] = clk_get(NULL, name);
|
||||
if (IS_ERR(uart_ick[i])) {
|
||||
printk(KERN_ERR "Could not get uart%d_ick\n", i+1);
|
||||
uart_ick[i] = NULL;
|
||||
} else
|
||||
clk_enable(uart_ick[i]);
|
||||
|
||||
uart1_fck = clk_get(NULL, "uart1_fck");
|
||||
if (IS_ERR(uart1_fck))
|
||||
printk("Could not get uart1_fck\n");
|
||||
else {
|
||||
clk_enable(uart1_fck);
|
||||
}
|
||||
break;
|
||||
case 1:
|
||||
uart2_ick = clk_get(NULL, "uart2_ick");
|
||||
if (IS_ERR(uart2_ick))
|
||||
printk("Could not get uart2_ick\n");
|
||||
else {
|
||||
clk_enable(uart2_ick);
|
||||
}
|
||||
|
||||
uart2_fck = clk_get(NULL, "uart2_fck");
|
||||
if (IS_ERR(uart2_fck))
|
||||
printk("Could not get uart2_fck\n");
|
||||
else {
|
||||
clk_enable(uart2_fck);
|
||||
}
|
||||
break;
|
||||
case 2:
|
||||
uart3_ick = clk_get(NULL, "uart3_ick");
|
||||
if (IS_ERR(uart3_ick))
|
||||
printk("Could not get uart3_ick\n");
|
||||
else {
|
||||
clk_enable(uart3_ick);
|
||||
}
|
||||
|
||||
uart3_fck = clk_get(NULL, "uart3_fck");
|
||||
if (IS_ERR(uart3_fck))
|
||||
printk("Could not get uart3_fck\n");
|
||||
else {
|
||||
clk_enable(uart3_fck);
|
||||
}
|
||||
break;
|
||||
}
|
||||
sprintf(name, "uart%d_fck", i+1);
|
||||
uart_fck[i] = clk_get(NULL, name);
|
||||
if (IS_ERR(uart_fck[i])) {
|
||||
printk(KERN_ERR "Could not get uart%d_fck\n", i+1);
|
||||
uart_fck[i] = NULL;
|
||||
} else
|
||||
clk_enable(uart_fck[i]);
|
||||
|
||||
omap_serial_reset(p);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -5,6 +5,10 @@
|
|||
* Texas Instruments, <www.ti.com>
|
||||
* Richard Woodruff <r-woodruff2@ti.com>
|
||||
*
|
||||
* (C) Copyright 2006 Nokia Corporation
|
||||
* Fixed idle loop sleep
|
||||
* Igor Stoppa <igor.stoppa@nokia.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
|
|
@ -26,6 +30,8 @@
|
|||
#include <mach/io.h>
|
||||
#include <mach/pm.h>
|
||||
|
||||
#include <mach/omap24xx.h>
|
||||
|
||||
#include "sdrc.h"
|
||||
|
||||
/* First address of reserved address space? apparently valid for OMAP2 & 3 */
|
||||
|
|
@ -52,15 +58,14 @@ ENTRY(omap24xx_idle_loop_suspend_sz)
|
|||
.word . - omap24xx_idle_loop_suspend
|
||||
|
||||
/*
|
||||
* omap242x_cpu_suspend() - Forces OMAP into deep sleep state by completing
|
||||
* omap24xx_cpu_suspend() - Forces OMAP into deep sleep state by completing
|
||||
* SDRC shutdown then ARM shutdown. Upon wake MPU is back on so just restore
|
||||
* SDRC.
|
||||
*
|
||||
* Input:
|
||||
* R0 : DLL ctrl value pre-Sleep
|
||||
* R1 : Processor+Revision
|
||||
* 2420: 0x21 = 242xES1, 0x26 = 242xES2.2
|
||||
* 2430: 0x31 = 2430ES1, 0x32 = 2430ES2
|
||||
* R1 : SDRC_DLLA_CTRL
|
||||
* R2 : SDRC_POWER
|
||||
*
|
||||
* The if the DPLL is going to AutoIdle. It seems like the DPLL may be back on
|
||||
* when we get called, but the DLL probably isn't. We will wait a bit more in
|
||||
|
|
@ -80,15 +85,14 @@ ENTRY(omap24xx_idle_loop_suspend_sz)
|
|||
*/
|
||||
ENTRY(omap24xx_cpu_suspend)
|
||||
stmfd sp!, {r0 - r12, lr} @ save registers on stack
|
||||
mov r3, #0x0 @ clear for mrc call
|
||||
mov r3, #0x0 @ clear for mcr call
|
||||
mcr p15, 0, r3, c7, c10, 4 @ memory barrier, hope SDR/DDR finished
|
||||
nop
|
||||
nop
|
||||
ldr r3, A_SDRC_POWER @ addr of sdrc power
|
||||
ldr r4, [r3] @ value of sdrc power
|
||||
ldr r4, [r2] @ read SDRC_POWER
|
||||
orr r4, r4, #0x40 @ enable self refresh on idle req
|
||||
mov r5, #0x2000 @ set delay (DPLL relock + DLL relock)
|
||||
str r4, [r3] @ make it so
|
||||
str r4, [r2] @ make it so
|
||||
mov r2, #0
|
||||
nop
|
||||
mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt
|
||||
|
|
@ -97,14 +101,13 @@ loop:
|
|||
subs r5, r5, #0x1 @ awake, wait just a bit
|
||||
bne loop
|
||||
|
||||
/* The DPLL has on before we take the DDR out of self refresh */
|
||||
/* The DPLL has to be on before we take the DDR out of self refresh */
|
||||
bic r4, r4, #0x40 @ now clear self refresh bit.
|
||||
str r4, [r3] @ put vlaue back.
|
||||
str r4, [r2] @ write to SDRC_POWER
|
||||
ldr r4, A_SDRC0 @ make a clock happen
|
||||
ldr r4, [r4]
|
||||
ldr r4, [r4] @ read A_SDRC0
|
||||
nop @ start auto refresh only after clk ok
|
||||
movs r0, r0 @ see if DDR or SDR
|
||||
ldrne r1, A_SDRC_DLLA_CTRL_S @ get addr of DLL ctrl
|
||||
strne r0, [r1] @ rewrite DLLA to force DLL reload
|
||||
addne r1, r1, #0x8 @ move to DLLB
|
||||
strne r0, [r1] @ rewrite DLLB to force DLL reload
|
||||
|
|
@ -116,13 +119,8 @@ loop2:
|
|||
/* resume*/
|
||||
ldmfd sp!, {r0 - r12, pc} @ restore regs and return
|
||||
|
||||
A_SDRC_POWER:
|
||||
.word OMAP242X_SDRC_REGADDR(SDRC_POWER)
|
||||
A_SDRC0:
|
||||
.word A_SDRC0_V
|
||||
A_SDRC_DLLA_CTRL_S:
|
||||
.word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
|
||||
|
||||
ENTRY(omap24xx_cpu_suspend_sz)
|
||||
.word . - omap24xx_cpu_suspend
|
||||
|
||||
|
|
@ -248,6 +248,7 @@ static struct omap_globals *omap2_globals;
|
|||
|
||||
static void __init __omap2_set_globals(void)
|
||||
{
|
||||
omap2_set_globals_tap(omap2_globals);
|
||||
omap2_set_globals_memory(omap2_globals);
|
||||
omap2_set_globals_control(omap2_globals);
|
||||
omap2_set_globals_prcm(omap2_globals);
|
||||
|
|
@ -258,6 +259,7 @@ static void __init __omap2_set_globals(void)
|
|||
#if defined(CONFIG_ARCH_OMAP2420)
|
||||
|
||||
static struct omap_globals omap242x_globals = {
|
||||
.class = OMAP242X_CLASS,
|
||||
.tap = OMAP2_IO_ADDRESS(0x48014000),
|
||||
.sdrc = OMAP2_IO_ADDRESS(OMAP2420_SDRC_BASE),
|
||||
.sms = OMAP2_IO_ADDRESS(OMAP2420_SMS_BASE),
|
||||
|
|
@ -276,6 +278,7 @@ void __init omap2_set_globals_242x(void)
|
|||
#if defined(CONFIG_ARCH_OMAP2430)
|
||||
|
||||
static struct omap_globals omap243x_globals = {
|
||||
.class = OMAP243X_CLASS,
|
||||
.tap = OMAP2_IO_ADDRESS(0x4900a000),
|
||||
.sdrc = OMAP2_IO_ADDRESS(OMAP243X_SDRC_BASE),
|
||||
.sms = OMAP2_IO_ADDRESS(OMAP243X_SMS_BASE),
|
||||
|
|
@ -294,6 +297,7 @@ void __init omap2_set_globals_243x(void)
|
|||
#if defined(CONFIG_ARCH_OMAP3430)
|
||||
|
||||
static struct omap_globals omap343x_globals = {
|
||||
.class = OMAP343X_CLASS,
|
||||
.tap = OMAP2_IO_ADDRESS(0x4830A000),
|
||||
.sdrc = OMAP2_IO_ADDRESS(OMAP343X_SDRC_BASE),
|
||||
.sms = OMAP2_IO_ADDRESS(OMAP343X_SMS_BASE),
|
||||
|
|
|
|||
|
|
@ -20,16 +20,16 @@
|
|||
#include <asm/mach/map.h>
|
||||
|
||||
#include <mach/tc.h>
|
||||
#include <mach/control.h>
|
||||
#include <mach/board.h>
|
||||
#include <mach/mux.h>
|
||||
#include <mach/gpio.h>
|
||||
#include <mach/menelaus.h>
|
||||
#include <mach/mcbsp.h>
|
||||
#include <mach/dsp_common.h>
|
||||
|
||||
#if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE)
|
||||
|
||||
#include "../plat-omap/dsp/dsp_common.h"
|
||||
|
||||
static struct dsp_platform_data dsp_pdata = {
|
||||
.kdev_list = LIST_HEAD_INIT(dsp_pdata.kdev_list),
|
||||
};
|
||||
|
|
@ -75,7 +75,7 @@ int dsp_kfunc_device_register(struct dsp_kfunc_device *kdev)
|
|||
{
|
||||
static DEFINE_MUTEX(dsp_pdata_lock);
|
||||
|
||||
mutex_init(&kdev->lock);
|
||||
spin_lock_init(&kdev->lock);
|
||||
|
||||
mutex_lock(&dsp_pdata_lock);
|
||||
list_add_tail(&kdev->entry, &dsp_pdata.kdev_list);
|
||||
|
|
@ -479,10 +479,6 @@ static inline void omap_init_rng(void) {}
|
|||
*/
|
||||
static int __init omap_init_devices(void)
|
||||
{
|
||||
/*
|
||||
* Need to enable relevant once for 2430 SDP
|
||||
*/
|
||||
#ifndef CONFIG_MACH_OMAP_2430SDP
|
||||
/* please keep these calls, and their implementations above,
|
||||
* in alphabetical order so they're easier to sort through.
|
||||
*/
|
||||
|
|
@ -492,7 +488,6 @@ static int __init omap_init_devices(void)
|
|||
omap_init_uwire();
|
||||
omap_init_wdt();
|
||||
omap_init_rng();
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(omap_init_devices);
|
||||
|
|
|
|||
|
|
@ -30,10 +30,12 @@
|
|||
#define __ASM_ARCH_OMAP_2430SDP_H
|
||||
|
||||
/* Placeholder for 2430SDP specific defines */
|
||||
#define OMAP24XX_ETHR_START 0x08000300
|
||||
#define OMAP24XX_ETHR_START 0x08000300
|
||||
#define OMAP24XX_ETHR_GPIO_IRQ 149
|
||||
#define SDP2430_CS0_BASE 0x04000000
|
||||
|
||||
#define TWL4030_IRQNUM INT_24XX_SYS_NIRQ
|
||||
/* Function prototypes */
|
||||
extern void sdp2430_flash_init(void);
|
||||
extern void sdp2430_usb_init(void);
|
||||
|
||||
#endif /* __ASM_ARCH_OMAP_2430SDP_H */
|
||||
|
|
|
|||
|
|
@ -31,6 +31,12 @@
|
|||
|
||||
extern void apollon_mmc_init(void);
|
||||
|
||||
static inline int apollon_plus(void)
|
||||
{
|
||||
/* The apollon plus has IDCODE revision 5 */
|
||||
return system_rev & 0xc0;
|
||||
}
|
||||
|
||||
/* Placeholder for APOLLON specific defines */
|
||||
#define APOLLON_ETHR_GPIO_IRQ 74
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* arch/arm/plat-omap/include/mach/board-h4.h
|
||||
*
|
||||
* Hardware definitions for TI OMAP1610 H4 board.
|
||||
* Hardware definitions for TI OMAP2420 H4 board.
|
||||
*
|
||||
* Initial creation by Dirk Behme <dirk.behme@de.bosch.com>
|
||||
*
|
||||
|
|
@ -29,6 +29,9 @@
|
|||
#ifndef __ASM_ARCH_OMAP_H4_H
|
||||
#define __ASM_ARCH_OMAP_H4_H
|
||||
|
||||
/* MMC Prototypes */
|
||||
extern void h4_mmc_init(void);
|
||||
|
||||
/* Placeholder for H4 specific defines */
|
||||
#define OMAP24XX_ETHR_GPIO_IRQ 92
|
||||
#endif /* __ASM_ARCH_OMAP_H4_H */
|
||||
|
|
|
|||
|
|
@ -45,6 +45,8 @@ struct omap_mmc_conf {
|
|||
unsigned cover:1;
|
||||
/* 4 wire signaling is optional, and is only used for SD/SDIO */
|
||||
unsigned wire4:1;
|
||||
/* use the internal clock */
|
||||
unsigned internal_clock:1;
|
||||
s16 power_pin;
|
||||
s16 switch_pin;
|
||||
s16 wp_pin;
|
||||
|
|
|
|||
|
|
@ -34,6 +34,7 @@ struct sys_timer;
|
|||
extern void omap_map_common_io(void);
|
||||
extern struct sys_timer omap_timer;
|
||||
extern void omap_serial_init(void);
|
||||
extern void omap_serial_enable_clocks(int enable);
|
||||
#ifdef CONFIG_I2C_OMAP
|
||||
extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
|
||||
struct i2c_board_info const *info,
|
||||
|
|
@ -49,6 +50,7 @@ static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
|
|||
|
||||
/* IO bases for various OMAP processors */
|
||||
struct omap_globals {
|
||||
u32 class; /* OMAP class to detect */
|
||||
void __iomem *tap; /* Control module ID code */
|
||||
void __iomem *sdrc; /* SDRAM Controller */
|
||||
void __iomem *sms; /* SDRAM Memory Scheduler */
|
||||
|
|
@ -62,6 +64,7 @@ void omap2_set_globals_243x(void);
|
|||
void omap2_set_globals_343x(void);
|
||||
|
||||
/* These get called from omap2_set_globals_xxxx(), do not call these */
|
||||
void omap2_set_globals_tap(struct omap_globals *);
|
||||
void omap2_set_globals_memory(struct omap_globals *);
|
||||
void omap2_set_globals_control(struct omap_globals *);
|
||||
void omap2_set_globals_prcm(struct omap_globals *);
|
||||
|
|
|
|||
|
|
@ -1,13 +1,10 @@
|
|||
#ifndef __ASM_ARCH_CONTROL_H
|
||||
#define __ASM_ARCH_CONTROL_H
|
||||
|
||||
/*
|
||||
* arch/arm/plat-omap/include/mach/control.h
|
||||
*
|
||||
* OMAP2/3 System Control Module definitions
|
||||
*
|
||||
* Copyright (C) 2007 Texas Instruments, Inc.
|
||||
* Copyright (C) 2007 Nokia Corporation
|
||||
* Copyright (C) 2007-2008 Texas Instruments, Inc.
|
||||
* Copyright (C) 2007-2008 Nokia Corporation
|
||||
*
|
||||
* Written by Paul Walmsley
|
||||
*
|
||||
|
|
@ -16,14 +13,23 @@
|
|||
* the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_CONTROL_H
|
||||
#define __ASM_ARCH_CONTROL_H
|
||||
|
||||
#include <mach/io.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#define OMAP242X_CTRL_REGADDR(reg) \
|
||||
IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
|
||||
#define OMAP243X_CTRL_REGADDR(reg) \
|
||||
IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
|
||||
#define OMAP343X_CTRL_REGADDR(reg) \
|
||||
IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
|
||||
#else
|
||||
#define OMAP242X_CTRL_REGADDR(reg) IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
|
||||
#define OMAP243X_CTRL_REGADDR(reg) IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
|
||||
#define OMAP343X_CTRL_REGADDR(reg) IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
/*
|
||||
* As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for
|
||||
|
|
@ -134,6 +140,7 @@
|
|||
#define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc)
|
||||
#define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
|
||||
#define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
|
||||
#define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02b4)
|
||||
|
||||
/*
|
||||
* REVISIT: This list of registers is not comprehensive - there are more
|
||||
|
|
|
|||
|
|
@ -346,9 +346,14 @@ IS_OMAP_TYPE(3430, 0x3430)
|
|||
get_sil_revision(system_rev)
|
||||
|
||||
/* Various silicon macros defined here */
|
||||
#define OMAP242X_CLASS 0x24200000
|
||||
#define OMAP2420_REV_ES1_0 0x24200000
|
||||
#define OMAP2420_REV_ES2_0 0x24201000
|
||||
|
||||
#define OMAP243X_CLASS 0x24300000
|
||||
#define OMAP2430_REV_ES1_0 0x24300000
|
||||
|
||||
#define OMAP343X_CLASS 0x34300000
|
||||
#define OMAP3430_REV_ES1_0 0x34300000
|
||||
#define OMAP3430_REV_ES2_0 0x34301000
|
||||
#define OMAP3430_REV_ES2_1 0x34302000
|
||||
|
|
|
|||
|
|
@ -76,6 +76,8 @@ extern void omap_free_gpio(int gpio);
|
|||
extern void omap_set_gpio_direction(int gpio, int is_input);
|
||||
extern void omap_set_gpio_dataout(int gpio, int enable);
|
||||
extern int omap_get_gpio_datain(int gpio);
|
||||
extern void omap2_gpio_prepare_for_retention(void);
|
||||
extern void omap2_gpio_resume_after_retention(void);
|
||||
extern void omap_set_gpio_debounce(int gpio, int enable);
|
||||
extern void omap_set_gpio_debounce_time(int gpio, int enable);
|
||||
|
||||
|
|
|
|||
|
|
@ -11,6 +11,9 @@
|
|||
#ifndef __OMAP2_GPMC_H
|
||||
#define __OMAP2_GPMC_H
|
||||
|
||||
/* Maximum Number of Chip Selects */
|
||||
#define GPMC_CS_NUM 8
|
||||
|
||||
#define GPMC_CS_CONFIG1 0x00
|
||||
#define GPMC_CS_CONFIG2 0x04
|
||||
#define GPMC_CS_CONFIG3 0x08
|
||||
|
|
@ -22,6 +25,9 @@
|
|||
#define GPMC_CS_NAND_ADDRESS 0x20
|
||||
#define GPMC_CS_NAND_DATA 0x24
|
||||
|
||||
#define GPMC_CONFIG 0x50
|
||||
#define GPMC_STATUS 0x54
|
||||
|
||||
#define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
|
||||
#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
|
||||
#define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
|
||||
|
|
@ -81,6 +87,7 @@ struct gpmc_timings {
|
|||
};
|
||||
|
||||
extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
|
||||
extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
|
||||
extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns);
|
||||
extern unsigned long gpmc_get_fclk_period(void);
|
||||
|
||||
|
|
@ -92,5 +99,6 @@ extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
|
|||
extern void gpmc_cs_free(int cs);
|
||||
extern int gpmc_cs_set_reserved(int cs, int reserved);
|
||||
extern int gpmc_cs_reserved(int cs);
|
||||
extern void gpmc_init(void);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -282,8 +282,8 @@
|
|||
|
||||
#include "omap730.h"
|
||||
#include "omap1510.h"
|
||||
#include "omap24xx.h"
|
||||
#include "omap16xx.h"
|
||||
#include "omap24xx.h"
|
||||
#include "omap34xx.h"
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
|
|
|
|||
|
|
@ -125,6 +125,7 @@
|
|||
#define INT_UART2 (15 + IH2_BASE)
|
||||
#define INT_BT_MCSI1TX (16 + IH2_BASE)
|
||||
#define INT_BT_MCSI1RX (17 + IH2_BASE)
|
||||
#define INT_SOSSI_MATCH (19 + IH2_BASE)
|
||||
#define INT_USB_W2FC (20 + IH2_BASE)
|
||||
#define INT_1WIRE (21 + IH2_BASE)
|
||||
#define INT_OS_TIMER (22 + IH2_BASE)
|
||||
|
|
@ -176,6 +177,7 @@
|
|||
#define INT_1610_DMA_CH14 (61 + IH2_BASE)
|
||||
#define INT_1610_DMA_CH15 (62 + IH2_BASE)
|
||||
#define INT_1610_NAND (63 + IH2_BASE)
|
||||
#define INT_1610_SHA1MD5 (91 + IH2_BASE)
|
||||
|
||||
/*
|
||||
* OMAP-730 specific IRQ numbers for interrupt handler 2
|
||||
|
|
@ -263,12 +265,16 @@
|
|||
#define INT_24XX_GPTIMER10 46
|
||||
#define INT_24XX_GPTIMER11 47
|
||||
#define INT_24XX_GPTIMER12 48
|
||||
#define INT_24XX_SHA1MD5 51
|
||||
#define INT_24XX_I2C1_IRQ 56
|
||||
#define INT_24XX_I2C2_IRQ 57
|
||||
#define INT_24XX_HDQ_IRQ 58
|
||||
#define INT_24XX_MCBSP1_IRQ_TX 59
|
||||
#define INT_24XX_MCBSP1_IRQ_RX 60
|
||||
#define INT_24XX_MCBSP2_IRQ_TX 62
|
||||
#define INT_24XX_MCBSP2_IRQ_RX 63
|
||||
#define INT_24XX_SPI1_IRQ 65
|
||||
#define INT_24XX_SPI2_IRQ 66
|
||||
#define INT_24XX_UART1_IRQ 72
|
||||
#define INT_24XX_UART2_IRQ 73
|
||||
#define INT_24XX_UART3_IRQ 74
|
||||
|
|
|
|||
|
|
@ -125,20 +125,64 @@
|
|||
.pu_pd_val = pull_mode, \
|
||||
},
|
||||
|
||||
/* 24xx/34xx mux bit defines */
|
||||
#define OMAP2_PULL_ENA (1 << 3)
|
||||
#define OMAP2_PULL_UP (1 << 4)
|
||||
#define OMAP2_ALTELECTRICALSEL (1 << 5)
|
||||
|
||||
#define PULL_DISABLED 0
|
||||
#define PULL_ENABLED 1
|
||||
/* 34xx specific mux bit defines */
|
||||
#define OMAP3_INPUT_EN (1 << 8)
|
||||
#define OMAP3_OFF_EN (1 << 9)
|
||||
#define OMAP3_OFFOUT_EN (1 << 10)
|
||||
#define OMAP3_OFFOUT_VAL (1 << 11)
|
||||
#define OMAP3_OFF_PULL_EN (1 << 12)
|
||||
#define OMAP3_OFF_PULL_UP (1 << 13)
|
||||
#define OMAP3_WAKEUP_EN (1 << 14)
|
||||
|
||||
#define PULL_DOWN 0
|
||||
#define PULL_UP 1
|
||||
/* 34xx mux mode options for each pin. See TRM for options */
|
||||
#define OMAP34XX_MUX_MODE0 0
|
||||
#define OMAP34XX_MUX_MODE1 1
|
||||
#define OMAP34XX_MUX_MODE2 2
|
||||
#define OMAP34XX_MUX_MODE3 3
|
||||
#define OMAP34XX_MUX_MODE4 4
|
||||
#define OMAP34XX_MUX_MODE5 5
|
||||
#define OMAP34XX_MUX_MODE6 6
|
||||
#define OMAP34XX_MUX_MODE7 7
|
||||
|
||||
/* 34xx active pin states */
|
||||
#define OMAP34XX_PIN_OUTPUT 0
|
||||
#define OMAP34XX_PIN_INPUT OMAP3_INPUT_EN
|
||||
#define OMAP34XX_PIN_INPUT_PULLUP (OMAP2_PULL_ENA | OMAP3_INPUT_EN \
|
||||
| OMAP2_PULL_UP)
|
||||
#define OMAP34XX_PIN_INPUT_PULLDOWN (OMAP2_PULL_ENA | OMAP3_INPUT_EN)
|
||||
|
||||
/* 34xx off mode states */
|
||||
#define OMAP34XX_PIN_OFF_NONE 0
|
||||
#define OMAP34XX_PIN_OFF_OUTPUT_HIGH (OMAP3_OFF_EN | OMAP3_OFFOUT_EN \
|
||||
| OMAP3_OFFOUT_VAL)
|
||||
#define OMAP34XX_PIN_OFF_OUTPUT_LOW (OMAP3_OFF_EN | OMAP3_OFFOUT_EN)
|
||||
#define OMAP34XX_PIN_OFF_INPUT_PULLUP (OMAP3_OFF_EN | OMAP3_OFF_PULL_EN \
|
||||
| OMAP3_OFF_PULL_UP)
|
||||
#define OMAP34XX_PIN_OFF_INPUT_PULLDOWN (OMAP3_OFF_EN | OMAP3_OFF_PULL_EN)
|
||||
#define OMAP34XX_PIN_OFF_WAKEUPENABLE OMAP3_WAKEUP_EN
|
||||
|
||||
#define MUX_CFG_34XX(desc, reg_offset, mux_value) { \
|
||||
.name = desc, \
|
||||
.debug = 0, \
|
||||
.mux_reg = reg_offset, \
|
||||
.mux_val = mux_value \
|
||||
},
|
||||
|
||||
struct pin_config {
|
||||
char *name;
|
||||
unsigned char busy;
|
||||
unsigned char debug;
|
||||
char *name;
|
||||
const unsigned int mux_reg;
|
||||
unsigned char debug;
|
||||
|
||||
const char *mux_reg_name;
|
||||
const unsigned int mux_reg;
|
||||
#if defined(CONFIG_ARCH_OMAP34XX)
|
||||
u16 mux_val; /* Wake-up, off mode, pull, mux mode */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP24XX)
|
||||
const unsigned char mask_offset;
|
||||
const unsigned char mask;
|
||||
|
||||
|
|
@ -150,6 +194,12 @@ struct pin_config {
|
|||
const char *pu_pd_name;
|
||||
const unsigned int pu_pd_reg;
|
||||
const unsigned char pu_pd_val;
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
|
||||
const char *mux_reg_name;
|
||||
#endif
|
||||
|
||||
};
|
||||
|
||||
enum omap730_index {
|
||||
|
|
@ -593,6 +643,90 @@ enum omap24xx_index {
|
|||
|
||||
};
|
||||
|
||||
enum omap34xx_index {
|
||||
/* 34xx I2C */
|
||||
K21_34XX_I2C1_SCL,
|
||||
J21_34XX_I2C1_SDA,
|
||||
AF15_34XX_I2C2_SCL,
|
||||
AE15_34XX_I2C2_SDA,
|
||||
AF14_34XX_I2C3_SCL,
|
||||
AG14_34XX_I2C3_SDA,
|
||||
AD26_34XX_I2C4_SCL,
|
||||
AE26_34XX_I2C4_SDA,
|
||||
|
||||
/* PHY - HSUSB: 12-pin ULPI PHY: Port 1*/
|
||||
Y8_3430_USB1HS_PHY_CLK,
|
||||
Y9_3430_USB1HS_PHY_STP,
|
||||
AA14_3430_USB1HS_PHY_DIR,
|
||||
AA11_3430_USB1HS_PHY_NXT,
|
||||
W13_3430_USB1HS_PHY_DATA0,
|
||||
W12_3430_USB1HS_PHY_DATA1,
|
||||
W11_3430_USB1HS_PHY_DATA2,
|
||||
Y11_3430_USB1HS_PHY_DATA3,
|
||||
W9_3430_USB1HS_PHY_DATA4,
|
||||
Y12_3430_USB1HS_PHY_DATA5,
|
||||
W8_3430_USB1HS_PHY_DATA6,
|
||||
Y13_3430_USB1HS_PHY_DATA7,
|
||||
|
||||
/* PHY - HSUSB: 12-pin ULPI PHY: Port 2*/
|
||||
AA8_3430_USB2HS_PHY_CLK,
|
||||
AA10_3430_USB2HS_PHY_STP,
|
||||
AA9_3430_USB2HS_PHY_DIR,
|
||||
AB11_3430_USB2HS_PHY_NXT,
|
||||
AB10_3430_USB2HS_PHY_DATA0,
|
||||
AB9_3430_USB2HS_PHY_DATA1,
|
||||
W3_3430_USB2HS_PHY_DATA2,
|
||||
T4_3430_USB2HS_PHY_DATA3,
|
||||
T3_3430_USB2HS_PHY_DATA4,
|
||||
R3_3430_USB2HS_PHY_DATA5,
|
||||
R4_3430_USB2HS_PHY_DATA6,
|
||||
T2_3430_USB2HS_PHY_DATA7,
|
||||
|
||||
|
||||
/* TLL - HSUSB: 12-pin TLL Port 1*/
|
||||
Y8_3430_USB1HS_TLL_CLK,
|
||||
Y9_3430_USB1HS_TLL_STP,
|
||||
AA14_3430_USB1HS_TLL_DIR,
|
||||
AA11_3430_USB1HS_TLL_NXT,
|
||||
W13_3430_USB1HS_TLL_DATA0,
|
||||
W12_3430_USB1HS_TLL_DATA1,
|
||||
W11_3430_USB1HS_TLL_DATA2,
|
||||
Y11_3430_USB1HS_TLL_DATA3,
|
||||
W9_3430_USB1HS_TLL_DATA4,
|
||||
Y12_3430_USB1HS_TLL_DATA5,
|
||||
W8_3430_USB1HS_TLL_DATA6,
|
||||
Y13_3430_USB1HS_TLL_DATA7,
|
||||
|
||||
/* TLL - HSUSB: 12-pin TLL Port 2*/
|
||||
AA8_3430_USB2HS_TLL_CLK,
|
||||
AA10_3430_USB2HS_TLL_STP,
|
||||
AA9_3430_USB2HS_TLL_DIR,
|
||||
AB11_3430_USB2HS_TLL_NXT,
|
||||
AB10_3430_USB2HS_TLL_DATA0,
|
||||
AB9_3430_USB2HS_TLL_DATA1,
|
||||
W3_3430_USB2HS_TLL_DATA2,
|
||||
T4_3430_USB2HS_TLL_DATA3,
|
||||
T3_3430_USB2HS_TLL_DATA4,
|
||||
R3_3430_USB2HS_TLL_DATA5,
|
||||
R4_3430_USB2HS_TLL_DATA6,
|
||||
T2_3430_USB2HS_TLL_DATA7,
|
||||
|
||||
/* TLL - HSUSB: 12-pin TLL Port 3*/
|
||||
AA6_3430_USB3HS_TLL_CLK,
|
||||
AB3_3430_USB3HS_TLL_STP,
|
||||
AA3_3430_USB3HS_TLL_DIR,
|
||||
Y3_3430_USB3HS_TLL_NXT,
|
||||
AA5_3430_USB3HS_TLL_DATA0,
|
||||
Y4_3430_USB3HS_TLL_DATA1,
|
||||
Y5_3430_USB3HS_TLL_DATA2,
|
||||
W5_3430_USB3HS_TLL_DATA3,
|
||||
AB12_3430_USB3HS_TLL_DATA4,
|
||||
AB13_3430_USB3HS_TLL_DATA5,
|
||||
AA13_3430_USB3HS_TLL_DATA6,
|
||||
AA12_3430_USB3HS_TLL_DATA7
|
||||
|
||||
};
|
||||
|
||||
struct omap_mux_cfg {
|
||||
struct pin_config *pins;
|
||||
unsigned long size;
|
||||
|
|
|
|||
|
|
@ -44,5 +44,7 @@
|
|||
#define OMAP1510_DSPREG_SIZE SZ_128K
|
||||
#define OMAP1510_DSPREG_START 0xE1000000
|
||||
|
||||
#define OMAP1510_DSP_MMU_BASE (0xfffed200)
|
||||
|
||||
#endif /* __ASM_ARCH_OMAP15XX_H */
|
||||
|
||||
|
|
|
|||
|
|
@ -44,6 +44,11 @@
|
|||
#define OMAP16XX_DSPREG_SIZE SZ_128K
|
||||
#define OMAP16XX_DSPREG_START 0xE1000000
|
||||
|
||||
#define OMAP16XX_SEC_BASE 0xFFFE4000
|
||||
#define OMAP16XX_SEC_DES (OMAP16XX_SEC_BASE + 0x0000)
|
||||
#define OMAP16XX_SEC_SHA1MD5 (OMAP16XX_SEC_BASE + 0x0800)
|
||||
#define OMAP16XX_SEC_RNG (OMAP16XX_SEC_BASE + 0x1000)
|
||||
|
||||
/*
|
||||
* ---------------------------------------------------------------------------
|
||||
* Interrupts
|
||||
|
|
@ -190,7 +195,7 @@
|
|||
#define WSPR_DISABLE_0 (0x0000aaaa)
|
||||
#define WSPR_DISABLE_1 (0x00005555)
|
||||
|
||||
/* Mailbox */
|
||||
#define OMAP16XX_DSP_MMU_BASE (0xfffed200)
|
||||
#define OMAP16XX_MAILBOX_BASE (0xfffcf000)
|
||||
|
||||
#endif /* __ASM_ARCH_OMAP16XX_H */
|
||||
|
|
|
|||
|
|
@ -48,6 +48,7 @@
|
|||
#define OMAP2420_PRM_BASE OMAP2420_CM_BASE
|
||||
#define OMAP2420_SDRC_BASE (L3_24XX_BASE + 0x9000)
|
||||
#define OMAP2420_SMS_BASE 0x68008000
|
||||
#define OMAP2420_GPMC_BASE 0x6800a000
|
||||
|
||||
#define OMAP2430_32KSYNCT_BASE (L4_WK_243X_BASE + 0x20000)
|
||||
#define OMAP2430_PRCM_BASE (L4_WK_243X_BASE + 0x6000)
|
||||
|
|
|
|||
|
|
@ -62,6 +62,7 @@
|
|||
#define OMAPFB_CAPS_WINDOW_PIXEL_DOUBLE 0x00010000
|
||||
#define OMAPFB_CAPS_WINDOW_SCALE 0x00020000
|
||||
#define OMAPFB_CAPS_WINDOW_OVERLAY 0x00040000
|
||||
#define OMAPFB_CAPS_WINDOW_ROTATE 0x00080000
|
||||
#define OMAPFB_CAPS_SET_BACKLIGHT 0x01000000
|
||||
|
||||
/* Values from DSP must map to lower 16-bits */
|
||||
|
|
@ -305,6 +306,7 @@ struct lcd_ctrl {
|
|||
int screen_width,
|
||||
int pos_x, int pos_y, int width,
|
||||
int height, int color_mode);
|
||||
int (*set_rotate) (int angle);
|
||||
int (*setup_mem) (int plane, size_t size,
|
||||
int mem_type, unsigned long *paddr);
|
||||
int (*mmap) (struct fb_info *info,
|
||||
|
|
@ -374,6 +376,7 @@ extern struct lcd_ctrl omap1_lcd_ctrl;
|
|||
extern struct lcd_ctrl omap2_disp_ctrl;
|
||||
#endif
|
||||
|
||||
extern void omapfb_reserve_sdram(void);
|
||||
extern void omapfb_register_panel(struct lcd_panel *panel);
|
||||
extern void omapfb_write_first_pixel(struct omapfb_device *fbdev, u16 pixval);
|
||||
extern void omapfb_notify_clients(struct omapfb_device *fbdev,
|
||||
|
|
|
|||
|
|
@ -135,7 +135,8 @@ extern void omap_pm_suspend(void);
|
|||
extern void omap730_cpu_suspend(unsigned short, unsigned short);
|
||||
extern void omap1510_cpu_suspend(unsigned short, unsigned short);
|
||||
extern void omap1610_cpu_suspend(unsigned short, unsigned short);
|
||||
extern void omap24xx_cpu_suspend(u32 dll_ctrl, u32 cpu_revision);
|
||||
extern void omap24xx_cpu_suspend(u32 dll_ctrl, void __iomem *sdrc_dlla_ctrl,
|
||||
void __iomem *sdrc_power);
|
||||
extern void omap730_idle_loop_suspend(void);
|
||||
extern void omap1510_idle_loop_suspend(void);
|
||||
extern void omap1610_idle_loop_suspend(void);
|
||||
|
|
|
|||
|
|
@ -25,6 +25,8 @@
|
|||
#define SDRC_DLLB_STATUS 0x06C
|
||||
#define SDRC_POWER 0x070
|
||||
#define SDRC_MR_0 0x084
|
||||
#define SDRC_ACTIM_CTRL_A 0x09c
|
||||
#define SDRC_ACTIM_CTRL_B 0x0a0
|
||||
#define SDRC_RFR_CTRL_0 0x0a4
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -20,11 +20,17 @@
|
|||
#define OMAP_UART1_BASE 0x4806a000
|
||||
#define OMAP_UART2_BASE 0x4806c000
|
||||
#define OMAP_UART3_BASE 0x4806e000
|
||||
#elif defined(CONFIG_ARCH_OMAP3)
|
||||
/* OMAP3 serial ports */
|
||||
#define OMAP_UART1_BASE 0x4806a000
|
||||
#define OMAP_UART2_BASE 0x4806c000
|
||||
#define OMAP_UART3_BASE 0x49020000
|
||||
#endif
|
||||
|
||||
#define OMAP_MAX_NR_PORTS 3
|
||||
#define OMAP1510_BASE_BAUD (12000000/16)
|
||||
#define OMAP16XX_BASE_BAUD (48000000/16)
|
||||
#define OMAP24XX_BASE_BAUD (48000000/16)
|
||||
|
||||
#define is_omap_port(pt) ({int __ret = 0; \
|
||||
if ((pt)->port.mapbase == OMAP_UART1_BASE || \
|
||||
|
|
|
|||
Loading…
Reference in New Issue