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ARM: SoC cleanups for 3.12 

This branch contains code cleanups, moves and removals for 3.12.
 
 There's a large number of various cleanups, and a nice net removal of
 13500 lines of code.
 
 Highlights worth mentioning are:
 
 - A series of patches from Stephen Boyd removing the ARM local timer API.
 - Move of Qualcomm MSM IOMMU code to drivers/iommu.
 - Samsung PWM driver cleanups from Tomasz Figa, removing legacy PWM driver
   and switching over to the drivers/pwm one.
 - Removal of some unusued auto-generated headers for OMAP2+ (PRM/CM).
 
 There's also a move of a header file out of include/linux/i2c/ to
 platform_data, where it really belongs. It touches mostly ARM platform
 code for include changes so we took it through our tree.
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Merge tag 'cleanup-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC cleanups from Olof Johansson:
 "This branch contains code cleanups, moves and removals for 3.12.

  There's a large number of various cleanups, and a nice net removal of
  13500 lines of code.

  Highlights worth mentioning are:

   - A series of patches from Stephen Boyd removing the ARM local timer
     API.
   - Move of Qualcomm MSM IOMMU code to drivers/iommu.
   - Samsung PWM driver cleanups from Tomasz Figa, removing legacy PWM
     driver and switching over to the drivers/pwm one.
   - Removal of some unusued auto-generated headers for OMAP2+ (PRM/CM).

  There's also a move of a header file out of include/linux/i2c/ to
  platform_data, where it really belongs.  It touches mostly ARM
  platform code for include changes so we took it through our tree"

* tag 'cleanup-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (83 commits)
  ARM: OMAP2+: Add back the define for AM33XX_RST_GLOBAL_WARM_SW_MASK
  gpio: (gpio-pca953x) move header to linux/platform_data/
  arm: zynq: hotplug: Remove unreachable code
  ARM: SAMSUNG: Remove unnecessary exynos4_default_sdhci*()
  tegra: simplify use of devm_ioremap_resource
  ARM: SAMSUNG: Remove plat/regs-timer.h header
  ARM: SAMSUNG: Remove remaining uses of plat/regs-timer.h header
  ARM: SAMSUNG: Remove pwm-clock infrastructure
  ARM: SAMSUNG: Remove old PWM timer platform devices
  pwm: Remove superseded pwm-samsung-legacy driver
  ARM: SAMSUNG: Modify board files to use new PWM platform device
  ARM: SAMSUNG: Rework private data handling in dev-backlight
  pwm: Add new pwm-samsung driver
  ARM: mach-mvebu: remove redundant DT parsing and validation
  ARM: msm: Only compile io.c on platforms that use it
  iommu/msm: Move mach includes to iommu directory
  ARM: msm: Remove devices-iommu.c
  ARM: msm: Move mach/board.h contents to common.h
  ARM: msm: Migrate msm_timer to CLOCKSOURCE_OF_DECLARE
  ARM: msm: Remove TMR and TMR0 static mappings
  ...
This commit is contained in:
Linus Torvalds 2013-09-06 13:21:16 -07:00
parent d2f3e9eb7c 7323f21953
commit 8e73e367f7
168 changed files with 1327 additions and 14821 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
arch/arm/Kconfig
View File

@ -631,6 +631,7 @@ config ARCH_MSM
bool "Qualcomm MSM"
select ARCH_REQUIRE_GPIOLIB
select CLKDEV_LOOKUP
select CLKSRC_OF if OF
select COMMON_CLK
select GENERIC_CLOCKEVENTS
help
@ -646,7 +647,7 @@ config ARCH_SHMOBILE
select CLKDEV_LOOKUP
select GENERIC_CLOCKEVENTS
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if LOCAL_TIMERS
select HAVE_ARM_TWD if SMP
select HAVE_CLK
select HAVE_MACH_CLKDEV
select HAVE_SMP
@ -701,7 +702,7 @@ config ARCH_S3C24XX
select ARCH_HAS_CPUFREQ
select ARCH_REQUIRE_GPIOLIB
select CLKDEV_LOOKUP
select CLKSRC_MMIO
select CLKSRC_SAMSUNG_PWM
select GENERIC_CLOCKEVENTS
select GPIO_SAMSUNG
select HAVE_CLK
@ -724,7 +725,7 @@ config ARCH_S3C64XX
select ARCH_REQUIRE_GPIOLIB
select ARM_VIC
select CLKDEV_LOOKUP
select CLKSRC_MMIO
select CLKSRC_SAMSUNG_PWM
select CPU_V6
select GENERIC_CLOCKEVENTS
select GPIO_SAMSUNG
@ -740,7 +741,6 @@ config ARCH_S3C64XX
select SAMSUNG_ATAGS
select SAMSUNG_CLKSRC
select SAMSUNG_GPIOLIB_4BIT
select SAMSUNG_IRQ_VIC_TIMER
select SAMSUNG_WDT_RESET
select USB_ARCH_HAS_OHCI
help
@ -749,7 +749,7 @@ config ARCH_S3C64XX
config ARCH_S5P64X0
bool "Samsung S5P6440 S5P6450"
select CLKDEV_LOOKUP
select CLKSRC_MMIO
select CLKSRC_SAMSUNG_PWM
select CPU_V6
select GENERIC_CLOCKEVENTS
select GPIO_SAMSUNG
@ -768,7 +768,7 @@ config ARCH_S5PC100
bool "Samsung S5PC100"
select ARCH_REQUIRE_GPIOLIB
select CLKDEV_LOOKUP
select CLKSRC_MMIO
select CLKSRC_SAMSUNG_PWM
select CPU_V7
select GENERIC_CLOCKEVENTS
select GPIO_SAMSUNG
@ -788,7 +788,7 @@ config ARCH_S5PV210
select ARCH_HAS_HOLES_MEMORYMODEL
select ARCH_SPARSEMEM_ENABLE
select CLKDEV_LOOKUP
select CLKSRC_MMIO
select CLKSRC_SAMSUNG_PWM
select CPU_V7
select GENERIC_CLOCKEVENTS
select GPIO_SAMSUNG
@ -1594,16 +1594,6 @@ config ARM_PSCI
0022A ("Power State Coordination Interface System Software on
ARM processors").
config LOCAL_TIMERS
bool "Use local timer interrupts"
depends on SMP
default y
help
Enable support for local timers on SMP platforms, rather then the
legacy IPI broadcast method. Local timers allows the system
accounting to be spread across the timer interval, preventing a
"thundering herd" at every timer tick.
# The GPIO number here must be sorted by descending number. In case of
# a multiplatform kernel, we just want the highest value required by the
# selected platforms.

9
arch/arm/Kconfig.debug
View File

@ -895,6 +895,11 @@ config DEBUG_LL_INCLUDE
DEBUG_IMX53_UART ||\
DEBUG_IMX6Q_UART || \
DEBUG_IMX6SL_UART
default "debug/msm.S" if DEBUG_MSM_UART1 || \
DEBUG_MSM_UART2 || \
DEBUG_MSM_UART3 || \
DEBUG_MSM8660_UART || \
DEBUG_MSM8960_UART
default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART
default "debug/sirf.S" if DEBUG_SIRFPRIMA2_UART1 || DEBUG_SIRFMARCO_UART1
default "debug/sti.S" if DEBUG_STI_UART
@ -1056,7 +1061,7 @@ config DEBUG_UART_8250_FLOW_CONTROL
config DEBUG_UNCOMPRESS
bool
depends on ARCH_MULTIPLATFORM
depends on ARCH_MULTIPLATFORM || ARCH_MSM
default y if DEBUG_LL && !DEBUG_OMAP2PLUS_UART && \
(!DEBUG_TEGRA_UART || !ZBOOT_ROM)
help
@ -1072,7 +1077,7 @@ config DEBUG_UNCOMPRESS
config UNCOMPRESS_INCLUDE
string
default "debug/uncompress.h" if ARCH_MULTIPLATFORM
default "debug/uncompress.h" if ARCH_MULTIPLATFORM || ARCH_MSM
default "mach/uncompress.h"
config EARLY_PRINTK

2
arch/arm/boot/dts/exynos4210.dtsi
View File

@ -72,7 +72,7 @@
};
};
clock: clock-controller@0x10030000 {
clock: clock-controller@10030000 {
compatible = "samsung,exynos4210-clock";
reg = <0x10030000 0x20000>;
#clock-cells = <1>;

2
arch/arm/boot/dts/exynos4x12.dtsi
View File

@ -28,7 +28,7 @@
pinctrl3 = &pinctrl_3;
};
clock: clock-controller@0x10030000 {
clock: clock-controller@10030000 {
compatible = "samsung,exynos4412-clock";
reg = <0x10030000 0x20000>;
#clock-cells = <1>;

14
arch/arm/boot/dts/exynos5250.dtsi
View File

@ -68,17 +68,17 @@
};
};
pd_gsc: gsc-power-domain@0x10044000 {
pd_gsc: gsc-power-domain@10044000 {
compatible = "samsung,exynos4210-pd";
reg = <0x10044000 0x20>;
};
pd_mfc: mfc-power-domain@0x10044040 {
pd_mfc: mfc-power-domain@10044040 {
compatible = "samsung,exynos4210-pd";
reg = <0x10044040 0x20>;
};
clock: clock-controller@0x10010000 {
clock: clock-controller@10010000 {
compatible = "samsung,exynos5250-clock";
reg = <0x10010000 0x30000>;
#clock-cells = <1>;
@ -559,7 +559,7 @@
};
};
gsc_0: gsc@0x13e00000 {
gsc_0: gsc@13e00000 {
compatible = "samsung,exynos5-gsc";
reg = <0x13e00000 0x1000>;
interrupts = <0 85 0>;
@ -568,7 +568,7 @@
clock-names = "gscl";
};
gsc_1: gsc@0x13e10000 {
gsc_1: gsc@13e10000 {
compatible = "samsung,exynos5-gsc";
reg = <0x13e10000 0x1000>;
interrupts = <0 86 0>;
@ -577,7 +577,7 @@
clock-names = "gscl";
};
gsc_2: gsc@0x13e20000 {
gsc_2: gsc@13e20000 {
compatible = "samsung,exynos5-gsc";
reg = <0x13e20000 0x1000>;
interrupts = <0 87 0>;
@ -586,7 +586,7 @@
clock-names = "gscl";
};
gsc_3: gsc@0x13e30000 {
gsc_3: gsc@13e30000 {
compatible = "samsung,exynos5-gsc";
reg = <0x13e30000 0x1000>;
interrupts = <0 88 0>;

2
arch/arm/boot/dts/exynos5420.dtsi
View File

@ -59,7 +59,7 @@
};
};
clock: clock-controller@0x10010000 {
clock: clock-controller@10010000 {
compatible = "samsung,exynos5420-clock";
reg = <0x10010000 0x30000>;
#clock-cells = <1>;

2
arch/arm/boot/dts/exynos5440.dtsi
View File

@ -20,7 +20,7 @@
spi0 = &spi_0;
};
clock: clock-controller@0x160000 {
clock: clock-controller@160000 {
compatible = "samsung,exynos5440-clock";
reg = <0x160000 0x1000>;
#clock-cells = <1>;

68
arch/arm/configs/exynos4_defconfig
View File

@ -1,68 +0,0 @@
CONFIG_EXPERIMENTAL=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_KALLSYMS_ALL=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_ARCH_EXYNOS=y
CONFIG_S3C_LOWLEVEL_UART_PORT=1
CONFIG_MACH_SMDKC210=y
CONFIG_MACH_ARMLEX4210=y
CONFIG_MACH_UNIVERSAL_C210=y
CONFIG_MACH_NURI=y
CONFIG_MACH_ORIGEN=y
CONFIG_MACH_SMDK4412=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_SMP=y
CONFIG_NR_CPUS=2
CONFIG_PREEMPT=y
CONFIG_AEABI=y
CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc mem=256M"
CONFIG_VFP=y
CONFIG_NEON=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=8192
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_CHR_DEV_SG=y
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_SAMSUNG=y
CONFIG_SERIAL_SAMSUNG_CONSOLE=y
CONFIG_HW_RANDOM=y
CONFIG_I2C=y
# CONFIG_HWMON is not set
# CONFIG_MFD_SUPPORT is not set
# CONFIG_HID_SUPPORT is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_EXT2_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_CRAMFS=y
CONFIG_ROMFS_FS=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_BSD_DISKLABEL=y
CONFIG_SOLARIS_X86_PARTITION=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ASCII=y
CONFIG_NLS_ISO8859_1=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DETECT_HUNG_TASK=y
CONFIG_DEBUG_RT_MUTEXES=y
CONFIG_DEBUG_SPINLOCK=y
CONFIG_DEBUG_MUTEXES=y
CONFIG_DEBUG_INFO=y
CONFIG_SYSCTL_SYSCALL_CHECK=y
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_LL=y
CONFIG_EARLY_PRINTK=y
CONFIG_CRC_CCITT=y

34
arch/arm/include/asm/localtimer.h
View File

@ -1,34 +0,0 @@
/*
* arch/arm/include/asm/localtimer.h
*
* Copyright (C) 2004-2005 ARM Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARM_LOCALTIMER_H
#define __ASM_ARM_LOCALTIMER_H
#include <linux/errno.h>
struct clock_event_device;
struct local_timer_ops {
int (*setup)(struct clock_event_device *);
void (*stop)(struct clock_event_device *);
};
#ifdef CONFIG_LOCAL_TIMERS
/*
* Register a local timer driver
*/
int local_timer_register(struct local_timer_ops *);
#else
static inline int local_timer_register(struct local_timer_ops *ops)
{
return -ENXIO;
}
#endif
#endif

32
arch/arm/mach-msm/include/mach/debug-macro.S → arch/arm/include/debug/msm.S
View File

@ -15,8 +15,36 @@
*
*/
#include <mach/hardware.h>
#include <mach/msm_iomap.h>
#if defined(CONFIG_ARCH_MSM7X00A) || defined(CONFIG_ARCH_QSD8X50)
#define MSM_UART1_PHYS 0xA9A00000
#define MSM_UART2_PHYS 0xA9B00000
#define MSM_UART3_PHYS 0xA9C00000
#elif defined(CONFIG_ARCH_MSM7X30)
#define MSM_UART1_PHYS 0xACA00000
#define MSM_UART2_PHYS 0xACB00000
#define MSM_UART3_PHYS 0xACC00000
#endif
#if defined(CONFIG_DEBUG_MSM_UART1)
#define MSM_DEBUG_UART_BASE 0xE1000000
#define MSM_DEBUG_UART_PHYS MSM_UART1_PHYS
#elif defined(CONFIG_DEBUG_MSM_UART2)
#define MSM_DEBUG_UART_BASE 0xE1000000
#define MSM_DEBUG_UART_PHYS MSM_UART2_PHYS
#elif defined(CONFIG_DEBUG_MSM_UART3)
#define MSM_DEBUG_UART_BASE 0xE1000000
#define MSM_DEBUG_UART_PHYS MSM_UART3_PHYS
#endif
#ifdef CONFIG_DEBUG_MSM8660_UART
#define MSM_DEBUG_UART_BASE 0xF0040000
#define MSM_DEBUG_UART_PHYS 0x19C40000
#endif
#ifdef CONFIG_DEBUG_MSM8960_UART
#define MSM_DEBUG_UART_BASE 0xF0040000
#define MSM_DEBUG_UART_PHYS 0x16440000
#endif
.macro addruart, rp, rv, tmp
#ifdef MSM_DEBUG_UART_PHYS

87
arch/arm/kernel/smp.c
View File

@ -41,7 +41,6 @@
#include <asm/sections.h>
#include <asm/tlbflush.h>
#include <asm/ptrace.h>
#include <asm/localtimer.h>
#include <asm/smp_plat.h>
#include <asm/virt.h>
#include <asm/mach/arch.h>
@ -156,8 +155,6 @@ int platform_can_cpu_hotplug(void)
}
#ifdef CONFIG_HOTPLUG_CPU
static void percpu_timer_stop(void);
static int platform_cpu_kill(unsigned int cpu)
{
if (smp_ops.cpu_kill)
@ -200,11 +197,6 @@ int __cpu_disable(void)
*/
migrate_irqs();
/*
* Stop the local timer for this CPU.
*/
percpu_timer_stop();
/*
* Flush user cache and TLB mappings, and then remove this CPU
* from the vm mask set of all processes.
@ -326,8 +318,6 @@ static void smp_store_cpu_info(unsigned int cpuid)
store_cpu_topology(cpuid);
}
static void percpu_timer_setup(void);
/*
* This is the secondary CPU boot entry. We're using this CPUs
* idle thread stack, but a set of temporary page tables.
@ -382,11 +372,6 @@ asmlinkage void secondary_start_kernel(void)
set_cpu_online(cpu, true);
complete(&cpu_running);
/*
* Setup the percpu timer for this CPU.
*/
percpu_timer_setup();
local_irq_enable();
local_fiq_enable();
@ -423,12 +408,6 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
if (max_cpus > ncores)
max_cpus = ncores;
if (ncores > 1 && max_cpus) {
/*
* Enable the local timer or broadcast device for the
* boot CPU, but only if we have more than one CPU.
*/
percpu_timer_setup();
/*
* Initialise the present map, which describes the set of CPUs
* actually populated at the present time. A platform should
@ -505,11 +484,6 @@ u64 smp_irq_stat_cpu(unsigned int cpu)
return sum;
}
/*
* Timer (local or broadcast) support
*/
static DEFINE_PER_CPU(struct clock_event_device, percpu_clockevent);
#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
void tick_broadcast(const struct cpumask *mask)
{
@ -517,67 +491,6 @@ void tick_broadcast(const struct cpumask *mask)
}
#endif
static void broadcast_timer_set_mode(enum clock_event_mode mode,
struct clock_event_device *evt)
{
}
static void broadcast_timer_setup(struct clock_event_device *evt)
{
evt->name = "dummy_timer";
evt->features = CLOCK_EVT_FEAT_ONESHOT |
CLOCK_EVT_FEAT_PERIODIC |
CLOCK_EVT_FEAT_DUMMY;
evt->rating = 100;
evt->mult = 1;
evt->set_mode = broadcast_timer_set_mode;
clockevents_register_device(evt);
}
static struct local_timer_ops *lt_ops;
#ifdef CONFIG_LOCAL_TIMERS
int local_timer_register(struct local_timer_ops *ops)
{
if (!is_smp() || !setup_max_cpus)
return -ENXIO;
if (lt_ops)
return -EBUSY;
lt_ops = ops;
return 0;
}
#endif
static void percpu_timer_setup(void)
{
unsigned int cpu = smp_processor_id();
struct clock_event_device *evt = &per_cpu(percpu_clockevent, cpu);
evt->cpumask = cpumask_of(cpu);
if (!lt_ops || lt_ops->setup(evt))
broadcast_timer_setup(evt);
}
#ifdef CONFIG_HOTPLUG_CPU
/*
* The generic clock events code purposely does not stop the local timer
* on CPU_DEAD/CPU_DEAD_FROZEN hotplug events, so we have to do it
* manually here.
*/
static void percpu_timer_stop(void)
{
unsigned int cpu = smp_processor_id();
struct clock_event_device *evt = &per_cpu(percpu_clockevent, cpu);
if (lt_ops)
lt_ops->stop(evt);
}
#endif
static DEFINE_RAW_SPINLOCK(stop_lock);
/*

66
arch/arm/kernel/smp_twd.c
View File

@ -11,6 +11,7 @@
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/cpu.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/err.h>
@ -24,7 +25,6 @@
#include <asm/smp_plat.h>
#include <asm/smp_twd.h>
#include <asm/localtimer.h>
/* set up by the platform code */
static void __iomem *twd_base;
@ -33,7 +33,7 @@ static struct clk *twd_clk;
static unsigned long twd_timer_rate;
static DEFINE_PER_CPU(bool, percpu_setup_called);
static struct clock_event_device __percpu **twd_evt;
static struct clock_event_device __percpu *twd_evt;
static int twd_ppi;
static void twd_set_mode(enum clock_event_mode mode,
@ -90,8 +90,10 @@ static int twd_timer_ack(void)
return 0;
}
static void twd_timer_stop(struct clock_event_device *clk)
static void twd_timer_stop(void)
{
struct clock_event_device *clk = __this_cpu_ptr(twd_evt);
twd_set_mode(CLOCK_EVT_MODE_UNUSED, clk);
disable_percpu_irq(clk->irq);
}
@ -106,7 +108,7 @@ static void twd_update_frequency(void *new_rate)
{
twd_timer_rate = *((unsigned long *) new_rate);
clockevents_update_freq(*__this_cpu_ptr(twd_evt), twd_timer_rate);
clockevents_update_freq(__this_cpu_ptr(twd_evt), twd_timer_rate);
}
static int twd_rate_change(struct notifier_block *nb,
@ -132,7 +134,7 @@ static struct notifier_block twd_clk_nb = {
static int twd_clk_init(void)
{
if (twd_evt && *__this_cpu_ptr(twd_evt) && !IS_ERR(twd_clk))
if (twd_evt && __this_cpu_ptr(twd_evt) && !IS_ERR(twd_clk))
return clk_notifier_register(twd_clk, &twd_clk_nb);
return 0;
@ -151,7 +153,7 @@ static void twd_update_frequency(void *data)
{
twd_timer_rate = clk_get_rate(twd_clk);
clockevents_update_freq(*__this_cpu_ptr(twd_evt), twd_timer_rate);
clockevents_update_freq(__this_cpu_ptr(twd_evt), twd_timer_rate);
}
static int twd_cpufreq_transition(struct notifier_block *nb,
@ -177,7 +179,7 @@ static struct notifier_block twd_cpufreq_nb = {
static int twd_cpufreq_init(void)
{
if (twd_evt && *__this_cpu_ptr(twd_evt) && !IS_ERR(twd_clk))
if (twd_evt && __this_cpu_ptr(twd_evt) && !IS_ERR(twd_clk))
return cpufreq_register_notifier(&twd_cpufreq_nb,
CPUFREQ_TRANSITION_NOTIFIER);
@ -228,7 +230,7 @@ static void twd_calibrate_rate(void)
static irqreturn_t twd_handler(int irq, void *dev_id)
{
struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
struct clock_event_device *evt = dev_id;
if (twd_timer_ack()) {
evt->event_handler(evt);
@ -265,9 +267,9 @@ static void twd_get_clock(struct device_node *np)
/*
* Setup the local clock events for a CPU.
*/
static int twd_timer_setup(struct clock_event_device *clk)
static void twd_timer_setup(void)
{
struct clock_event_device **this_cpu_clk;
struct clock_event_device *clk = __this_cpu_ptr(twd_evt);
int cpu = smp_processor_id();
/*
@ -276,9 +278,9 @@ static int twd_timer_setup(struct clock_event_device *clk)
*/
if (per_cpu(percpu_setup_called, cpu)) {
__raw_writel(0, twd_base + TWD_TIMER_CONTROL);
clockevents_register_device(*__this_cpu_ptr(twd_evt));
clockevents_register_device(clk);
enable_percpu_irq(clk->irq, 0);
return 0;
return;
}
per_cpu(percpu_setup_called, cpu) = true;
@ -297,27 +299,37 @@ static int twd_timer_setup(struct clock_event_device *clk)
clk->set_mode = twd_set_mode;
clk->set_next_event = twd_set_next_event;
clk->irq = twd_ppi;
this_cpu_clk = __this_cpu_ptr(twd_evt);
*this_cpu_clk = clk;
clk->cpumask = cpumask_of(cpu);
clockevents_config_and_register(clk, twd_timer_rate,
0xf, 0xffffffff);
enable_percpu_irq(clk->irq, 0);
return 0;
}
static struct local_timer_ops twd_lt_ops = {
.setup = twd_timer_setup,
.stop = twd_timer_stop,
static int twd_timer_cpu_notify(struct notifier_block *self,
unsigned long action, void *hcpu)
{
switch (action & ~CPU_TASKS_FROZEN) {
case CPU_STARTING:
twd_timer_setup();
break;
case CPU_DYING:
twd_timer_stop();
break;
}
return NOTIFY_OK;
}
static struct notifier_block twd_timer_cpu_nb = {
.notifier_call = twd_timer_cpu_notify,
};
static int __init twd_local_timer_common_register(struct device_node *np)
{
int err;
twd_evt = alloc_percpu(struct clock_event_device *);
twd_evt = alloc_percpu(struct clock_event_device);
if (!twd_evt) {
err = -ENOMEM;
goto out_free;
@ -329,12 +341,22 @@ static int __init twd_local_timer_common_register(struct device_node *np)
goto out_free;
}
err = local_timer_register(&twd_lt_ops);
err = register_cpu_notifier(&twd_timer_cpu_nb);
if (err)
goto out_irq;
twd_get_clock(np);
/*
* Immediately configure the timer on the boot CPU, unless we need
* jiffies to be incrementing to calibrate the rate in which case
* setup the timer in late_time_init.
*/
if (twd_timer_rate)
twd_timer_setup();
else
late_time_init = twd_timer_setup;
return 0;
out_irq:

2
arch/arm/mach-at91/board-snapper9260.c
View File

@ -26,7 +26,7 @@
#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/i2c/pca953x.h>
#include <linux/platform_data/pca953x.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>

2
arch/arm/mach-davinci/board-da850-evm.c
View File

@ -19,7 +19,7 @@
#include <linux/kernel.h>
#include <linux/i2c.h>
#include <linux/i2c/at24.h>
#include <linux/i2c/pca953x.h>
#include <linux/platform_data/pca953x.h>
#include <linux/input.h>
#include <linux/input/tps6507x-ts.h>
#include <linux/mfd/tps6507x.h>

2
arch/arm/mach-ep93xx/vision_ep9307.c
View File

@ -23,7 +23,7 @@
#include <linux/mtd/partitions.h>
#include <linux/i2c.h>
#include <linux/i2c-gpio.h>
#include <linux/i2c/pca953x.h>
#include <linux/platform_data/pca953x.h>
#include <linux/spi/spi.h>
#include <linux/spi/flash.h>
#include <linux/spi/mmc_spi.h>

43
arch/arm/mach-exynos/common.h
View File

@ -17,7 +17,6 @@
void mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1);
void exynos_init_time(void);
extern unsigned long xxti_f, xusbxti_f;
struct map_desc;
void exynos_init_io(void);
@ -25,56 +24,14 @@ void exynos4_restart(enum reboot_mode mode, const char *cmd);
void exynos5_restart(enum reboot_mode mode, const char *cmd);
void exynos_init_late(void);
/* ToDo: remove these after migrating legacy exynos4 platforms to dt */
void exynos4_clk_init(struct device_node *np, int is_exynos4210, void __iomem *reg_base, unsigned long xom);
void exynos4_clk_register_fixed_ext(unsigned long, unsigned long);
void exynos_firmware_init(void);
void exynos_set_timer_source(u8 channels);
#ifdef CONFIG_PM_GENERIC_DOMAINS
int exynos_pm_late_initcall(void);
#else
static inline int exynos_pm_late_initcall(void) { return 0; }
#endif
#ifdef CONFIG_ARCH_EXYNOS4
void exynos4_register_clocks(void);
void exynos4_setup_clocks(void);
#else
#define exynos4_register_clocks()
#define exynos4_setup_clocks()
#endif
#ifdef CONFIG_ARCH_EXYNOS5
void exynos5_register_clocks(void);
void exynos5_setup_clocks(void);
#else
#define exynos5_register_clocks()
#define exynos5_setup_clocks()
#endif
#ifdef CONFIG_CPU_EXYNOS4210
void exynos4210_register_clocks(void);
#else
#define exynos4210_register_clocks()
#endif
#ifdef CONFIG_SOC_EXYNOS4212
void exynos4212_register_clocks(void);
#else
#define exynos4212_register_clocks()
#endif
struct device_node;
void combiner_init(void __iomem *combiner_base, struct device_node *np,
unsigned int max_nr, int irq_base);
extern struct smp_operations exynos_smp_ops;
extern void exynos_cpu_die(unsigned int cpu);

2
arch/arm/mach-highbank/Kconfig
View File

@ -12,7 +12,7 @@ config ARCH_HIGHBANK
select CPU_V7
select GENERIC_CLOCKEVENTS
select HAVE_ARM_SCU
select HAVE_ARM_TWD if LOCAL_TIMERS
select HAVE_ARM_TWD if SMP
select HAVE_SMP
select MAILBOX
select PL320_MBOX

2
arch/arm/mach-imx/Kconfig
View File

@ -793,7 +793,7 @@ config SOC_IMX6Q
select COMMON_CLK
select CPU_V7
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if LOCAL_TIMERS
select HAVE_ARM_TWD if SMP
select HAVE_IMX_ANATOP
select HAVE_IMX_GPC
select HAVE_IMX_MMDC

2
arch/arm/mach-imx/mach-imx27_visstrim_m10.c
View File

@ -26,7 +26,7 @@
#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
#include <linux/i2c.h>
#include <linux/i2c/pca953x.h>
#include <linux/platform_data/pca953x.h>
#include <linux/input.h>
#include <linux/gpio.h>
#include <linux/delay.h>

2
arch/arm/mach-imx/mach-mxt_td60.c
View File

@ -26,7 +26,7 @@
#include <asm/mach/time.h>
#include <asm/mach/map.h>
#include <linux/gpio.h>
#include <linux/i2c/pca953x.h>
#include <linux/platform_data/pca953x.h>
#include "common.h"
#include "devices-imx27.h"

2
arch/arm/mach-ks8695/board-acs5k.c
View File

@ -20,7 +20,7 @@
#include <linux/i2c.h>
#include <linux/i2c-algo-bit.h>
#include <linux/i2c-gpio.h>
#include <linux/i2c/pca953x.h>
#include <linux/platform_data/pca953x.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/map.h>

2
arch/arm/mach-mmp/ttc_dkb.c
View File

@ -15,7 +15,7 @@
#include <linux/mtd/partitions.h>
#include <linux/mtd/onenand.h>
#include <linux/interrupt.h>
#include <linux/i2c/pca953x.h>
#include <linux/platform_data/pca953x.h>
#include <linux/gpio.h>
#include <linux/gpio-pxa.h>
#include <linux/mfd/88pm860x.h>

9
arch/arm/mach-msm/Makefile
View File

@ -1,17 +1,16 @@
obj-y += io.o timer.o
obj-y += timer.o
obj-y += clock.o
obj-$(CONFIG_MSM_VIC) += irq-vic.o
obj-$(CONFIG_MSM_IOMMU) += devices-iommu.o
obj-$(CONFIG_ARCH_MSM7X00A) += irq.o
obj-$(CONFIG_ARCH_QSD8X50) += sirc.o
obj-$(CONFIG_MSM_PROC_COMM) += proc_comm.o clock-pcom.o vreg.o
obj-$(CONFIG_ARCH_MSM7X00A) += dma.o
obj-$(CONFIG_ARCH_MSM7X30) += dma.o
obj-$(CONFIG_ARCH_QSD8X50) += dma.o
obj-$(CONFIG_ARCH_MSM7X00A) += dma.o io.o
obj-$(CONFIG_ARCH_MSM7X30) += dma.o io.o
obj-$(CONFIG_ARCH_QSD8X50) += dma.o io.o
obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o
obj-$(CONFIG_MSM_SMD) += last_radio_log.o

4
arch/arm/mach-msm/board-dt-8660.c
View File

@ -15,8 +15,8 @@
#include <linux/of_platform.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/board.h>
#include "common.h"
static void __init msm8x60_init_late(void)
@ -42,9 +42,7 @@ static const char *msm8x60_fluid_match[] __initdata = {
DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)")
.smp = smp_ops(msm_smp_ops),
.map_io = msm_map_msm8x60_io,
.init_machine = msm8x60_dt_init,
.init_late = msm8x60_init_late,
.init_time = msm_dt_timer_init,
.dt_compat = msm8x60_fluid_match,
MACHINE_END

3
arch/arm/mach-msm/board-dt-8960.c
View File

@ -14,6 +14,7 @@
#include <linux/of_platform.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include "common.h"
@ -29,8 +30,6 @@ static const char * const msm8960_dt_match[] __initconst = {
DT_MACHINE_START(MSM8960_DT, "Qualcomm MSM (Flattened Device Tree)")
.smp = smp_ops(msm_smp_ops),
.map_io = msm_map_msm8960_io,
.init_time = msm_dt_timer_init,
.init_machine = msm_dt_init,
.dt_compat = msm8960_dt_match,
MACHINE_END

1
arch/arm/mach-msm/board-halibut.c
View File

@ -29,7 +29,6 @@
#include <asm/setup.h>
#include <mach/irqs.h>
#include <mach/board.h>
#include <mach/msm_iomap.h>
#include <linux/mtd/nand.h>

2
arch/arm/mach-msm/board-mahimahi.c
View File

@ -28,12 +28,12 @@
#include <asm/mach/map.h>
#include <asm/setup.h>
#include <mach/board.h>
#include <mach/hardware.h>
#include "board-mahimahi.h"
#include "devices.h"
#include "proc_comm.h"
#include "common.h"
static uint debug_uart;

1
arch/arm/mach-msm/board-msm7x30.c
View File

@ -30,7 +30,6 @@
#include <asm/memory.h>
#include <asm/setup.h>
#include <mach/board.h>
#include <mach/msm_iomap.h>
#include <mach/dma.h>

1
arch/arm/mach-msm/board-qsd8x50.c
View File

@ -28,7 +28,6 @@
#include <asm/io.h>
#include <asm/setup.h>
#include <mach/board.h>
#include <mach/irqs.h>
#include <mach/sirc.h>
#include <mach/vreg.h>

2
arch/arm/mach-msm/board-sapphire.c
View File

@ -28,7 +28,6 @@
#include <asm/mach/map.h>
#include <asm/mach/flash.h>
#include <mach/vreg.h>
#include <mach/board.h>
#include <asm/io.h>
#include <asm/delay.h>
@ -41,6 +40,7 @@
#include "board-sapphire.h"
#include "proc_comm.h"
#include "devices.h"
#include "common.h"
void msm_init_irq(void);
void msm_init_gpio(void);

1
arch/arm/mach-msm/board-trout.c
View File

@ -25,7 +25,6 @@
#include <asm/mach/map.h>
#include <asm/setup.h>
#include <mach/board.h>
#include <mach/hardware.h>
#include <mach/msm_iomap.h>

2
arch/arm/mach-msm/board-trout.h
View File

@ -4,7 +4,7 @@
#ifndef __ARCH_ARM_MACH_MSM_BOARD_TROUT_H
#define __ARCH_ARM_MACH_MSM_BOARD_TROUT_H
#include <mach/board.h>
#include "common.h"
#define MSM_SMI_BASE 0x00000000
#define MSM_SMI_SIZE 0x00800000

18
arch/arm/mach-msm/common.h
View File

@ -14,13 +14,10 @@
extern void msm7x01_timer_init(void);
extern void msm7x30_timer_init(void);
extern void msm_dt_timer_init(void);
extern void qsd8x50_timer_init(void);
extern void msm_map_common_io(void);
extern void msm_map_msm7x30_io(void);
extern void msm_map_msm8x60_io(void);
extern void msm_map_msm8960_io(void);
extern void msm_map_qsd8x50_io(void);
extern void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size,
@ -29,4 +26,19 @@ extern void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size,
extern struct smp_operations msm_smp_ops;
extern void msm_cpu_die(unsigned int cpu);
struct msm_mmc_platform_data;
extern void msm_add_devices(void);
extern void msm_init_irq(void);
extern void msm_init_gpio(void);
extern int msm_add_sdcc(unsigned int controller,
struct msm_mmc_platform_data *plat,
unsigned int stat_irq, unsigned long stat_irq_flags);
#if defined(CONFIG_MSM_SMD) && defined(CONFIG_DEBUG_FS)
extern int smd_debugfs_init(void);
#else
static inline int smd_debugfs_init(void) { return 0; }
#endif
#endif

912
arch/arm/mach-msm/devices-iommu.c
View File

@ -1,912 +0,0 @@
/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*/
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/bootmem.h>
#include <linux/module.h>
#include <mach/irqs.h>
#include <mach/iommu.h>
static struct resource msm_iommu_jpegd_resources[] = {
{
.start = 0x07300000,
.end = 0x07300000 + SZ_1M - 1,
.name = "physbase",
.flags = IORESOURCE_MEM,
},
{
.name = "nonsecure_irq",
.start = SMMU_JPEGD_CB_SC_NON_SECURE_IRQ,
.end = SMMU_JPEGD_CB_SC_NON_SECURE_IRQ,
.flags = IORESOURCE_IRQ,
},
{
.name = "secure_irq",
.start = SMMU_JPEGD_CB_SC_SECURE_IRQ,
.end = SMMU_JPEGD_CB_SC_SECURE_IRQ,
.flags = IORESOURCE_IRQ,
},
};
static struct resource msm_iommu_vpe_resources[] = {
{
.start = 0x07400000,
.end = 0x07400000 + SZ_1M - 1,
.name = "physbase",
.flags = IORESOURCE_MEM,
},
{
.name = "nonsecure_irq",
.start = SMMU_VPE_CB_SC_NON_SECURE_IRQ,
.end = SMMU_VPE_CB_SC_NON_SECURE_IRQ,
.flags = IORESOURCE_IRQ,
},
{
.name = "secure_irq",
.start = SMMU_VPE_CB_SC_SECURE_IRQ,
.end = SMMU_VPE_CB_SC_SECURE_IRQ,
.flags = IORESOURCE_IRQ,
},
};
static struct resource msm_iommu_mdp0_resources[] = {
{
.start = 0x07500000,
.end = 0x07500000 + SZ_1M - 1,
.name = "physbase",
.flags = IORESOURCE_MEM,
},
{
.name = "nonsecure_irq",
.start = SMMU_MDP0_CB_SC_NON_SECURE_IRQ,
.end = SMMU_MDP0_CB_SC_NON_SECURE_IRQ,
.flags = IORESOURCE_IRQ,
},
{
.name = "secure_irq",
.start = SMMU_MDP0_CB_SC_SECURE_IRQ,
.end = SMMU_MDP0_CB_SC_SECURE_IRQ,
.flags = IORESOURCE_IRQ,
},
};
static struct resource msm_iommu_mdp1_resources[] = {
{
.start = 0x07600000,
.end = 0x07600000 + SZ_1M - 1,
.name = "physbase",
.flags = IORESOURCE_MEM,
},
{
.name = "nonsecure_irq",
.start = SMMU_MDP1_CB_SC_NON_SECURE_IRQ,
.end = SMMU_MDP1_CB_SC_NON_SECURE_IRQ,
.flags = IORESOURCE_IRQ,
},
{
.name = "secure_irq",
.start = SMMU_MDP1_CB_SC_SECURE_IRQ,
.end = SMMU_MDP1_CB_SC_SECURE_IRQ,
.flags = IORESOURCE_IRQ,
},
};
static struct resource msm_iommu_rot_resources[] = {
{
.start = 0x07700000,
.end = 0x07700000 + SZ_1M - 1,
.name = "physbase",
.flags = IORESOURCE_MEM,
},
{
.name = "nonsecure_irq",
.start = SMMU_ROT_CB_SC_NON_SECURE_IRQ,
.end = SMMU_ROT_CB_SC_NON_SECURE_IRQ,
.flags = IORESOURCE_IRQ,
},
{
.name = "secure_irq",
.start = SMMU_ROT_CB_SC_SECURE_IRQ,
.end = SMMU_ROT_CB_SC_SECURE_IRQ,
.flags = IORESOURCE_IRQ,
},
};
static struct resource msm_iommu_ijpeg_resources[] = {
{
.start = 0x07800000,
.end = 0x07800000 + SZ_1M - 1,
.name = "physbase",
.flags = IORESOURCE_MEM,
},
{
.name = "nonsecure_irq",
.start = SMMU_IJPEG_CB_SC_NON_SECURE_IRQ,
.end = SMMU_IJPEG_CB_SC_NON_SECURE_IRQ,
.flags = IORESOURCE_IRQ,
},
{
.name = "secure_irq",
.start = SMMU_IJPEG_CB_SC_SECURE_IRQ,
.end = SMMU_IJPEG_CB_SC_SECURE_IRQ,
.flags = IORESOURCE_IRQ,
},
};
static struct resource msm_iommu_vfe_resources[] = {
{
.start = 0x07900000,
.end = 0x07900000 + SZ_1M - 1,
.name = "physbase",
.flags = IORESOURCE_MEM,
},
{
.name = "nonsecure_irq",
.start = SMMU_VFE_CB_SC_NON_SECURE_IRQ,
.end = SMMU_VFE_CB_SC_NON_SECURE_IRQ,
.flags = IORESOURCE_IRQ,
},
{
.name = "secure_irq",
.start = SMMU_VFE_CB_SC_SECURE_IRQ,
.end = SMMU_VFE_CB_SC_SECURE_IRQ,
.flags = IORESOURCE_IRQ,
},
};
static struct resource msm_iommu_vcodec_a_resources[] = {
{
.start = 0x07A00000,
.end = 0x07A00000 + SZ_1M - 1,
.name = "physbase",
.flags = IORESOURCE_MEM,
},
{
.name = "nonsecure_irq",
.start = SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ,
.end = SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ,
.flags = IORESOURCE_IRQ,
},
{
.name = "secure_irq",
.start = SMMU_VCODEC_A_CB_SC_SECURE_IRQ,
.end = SMMU_VCODEC_A_CB_SC_SECURE_IRQ,
.flags = IORESOURCE_IRQ,
},
};
static struct resource msm_iommu_vcodec_b_resources[] = {
{
.start = 0x07B00000,
.end = 0x07B00000 + SZ_1M - 1,
.name = "physbase",
.flags = IORESOURCE_MEM,
},
{
.name = "nonsecure_irq",
.start = SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ,
.end = SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ,
.flags = IORESOURCE_IRQ,
},
{
.name = "secure_irq",
.start = SMMU_VCODEC_B_CB_SC_SECURE_IRQ,
.end = SMMU_VCODEC_B_CB_SC_SECURE_IRQ,
.flags = IORESOURCE_IRQ,
},
};
static struct resource msm_iommu_gfx3d_resources[] = {
{
.start = 0x07C00000,
.end = 0x07C00000 + SZ_1M - 1,
.name = "physbase",
.flags = IORESOURCE_MEM,
},
{
.name = "nonsecure_irq",
.start = SMMU_GFX3D_CB_SC_NON_SECURE_IRQ,
.end = SMMU_GFX3D_CB_SC_NON_SECURE_IRQ,
.flags = IORESOURCE_IRQ,
},
{
.name = "secure_irq",
.start = SMMU_GFX3D_CB_SC_SECURE_IRQ,
.end = SMMU_GFX3D_CB_SC_SECURE_IRQ,
.flags = IORESOURCE_IRQ,
},
};
static struct resource msm_iommu_gfx2d0_resources[] = {
{
.start = 0x07D00000,
.end = 0x07D00000 + SZ_1M - 1,
.name = "physbase",
.flags = IORESOURCE_MEM,
},
{
.name = "nonsecure_irq",
.start = SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ,
.end = SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ,
.flags = IORESOURCE_IRQ,
},
{
.name = "secure_irq",
.start = SMMU_GFX2D0_CB_SC_SECURE_IRQ,
.end = SMMU_GFX2D0_CB_SC_SECURE_IRQ,
.flags = IORESOURCE_IRQ,
},
};
static struct resource msm_iommu_gfx2d1_resources[] = {
{
.start = 0x07E00000,
.end = 0x07E00000 + SZ_1M - 1,
.name = "physbase",
.flags = IORESOURCE_MEM,
},
{
.name = "nonsecure_irq",
.start = SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ,
.end = SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ,
.flags = IORESOURCE_IRQ,
},
{
.name = "secure_irq",
.start = SMMU_GFX2D1_CB_SC_SECURE_IRQ,
.end = SMMU_GFX2D1_CB_SC_SECURE_IRQ,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device msm_root_iommu_dev = {
.name = "msm_iommu",
.id = -1,
};
static struct msm_iommu_dev jpegd_iommu = {
.name = "jpegd",
.ncb = 2,
};
static struct msm_iommu_dev vpe_iommu = {
.name = "vpe",
.ncb = 2,
};
static struct msm_iommu_dev mdp0_iommu = {
.name = "mdp0",
.ncb = 2,
};
static struct msm_iommu_dev mdp1_iommu = {
.name = "mdp1",
.ncb = 2,
};
static struct msm_iommu_dev rot_iommu = {
.name = "rot",
.ncb = 2,
};
static struct msm_iommu_dev ijpeg_iommu = {
.name = "ijpeg",
.ncb = 2,
};
static struct msm_iommu_dev vfe_iommu = {
.name = "vfe",
.ncb = 2,
};
static struct msm_iommu_dev vcodec_a_iommu = {
.name = "vcodec_a",
.ncb = 2,
};
static struct msm_iommu_dev vcodec_b_iommu = {
.name = "vcodec_b",
.ncb = 2,
};
static struct msm_iommu_dev gfx3d_iommu = {
.name = "gfx3d",
.ncb = 3,
};
static struct msm_iommu_dev gfx2d0_iommu = {
.name = "gfx2d0",
.ncb = 2,
};
static struct msm_iommu_dev gfx2d1_iommu = {
.name = "gfx2d1",
.ncb = 2,
};
static struct platform_device msm_device_iommu_jpegd = {
.name = "msm_iommu",
.id = 0,
.dev = {
.parent = &msm_root_iommu_dev.dev,
},
.num_resources = ARRAY_SIZE(msm_iommu_jpegd_resources),
.resource = msm_iommu_jpegd_resources,
};
static struct platform_device msm_device_iommu_vpe = {
.name = "msm_iommu",
.id = 1,
.dev = {
.parent = &msm_root_iommu_dev.dev,
},
.num_resources = ARRAY_SIZE(msm_iommu_vpe_resources),
.resource = msm_iommu_vpe_resources,
};
static struct platform_device msm_device_iommu_mdp0 = {
.name = "msm_iommu",
.id = 2,
.dev = {
.parent = &msm_root_iommu_dev.dev,
},
.num_resources = ARRAY_SIZE(msm_iommu_mdp0_resources),
.resource = msm_iommu_mdp0_resources,
};
static struct platform_device msm_device_iommu_mdp1 = {
.name = "msm_iommu",
.id = 3,
.dev = {
.parent = &msm_root_iommu_dev.dev,
},
.num_resources = ARRAY_SIZE(msm_iommu_mdp1_resources),
.resource = msm_iommu_mdp1_resources,
};
static struct platform_device msm_device_iommu_rot = {
.name = "msm_iommu",
.id = 4,
.dev = {
.parent = &msm_root_iommu_dev.dev,
},
.num_resources = ARRAY_SIZE(msm_iommu_rot_resources),
.resource = msm_iommu_rot_resources,
};
static struct platform_device msm_device_iommu_ijpeg = {
.name = "msm_iommu",
.id = 5,
.dev = {
.parent = &msm_root_iommu_dev.dev,
},
.num_resources = ARRAY_SIZE(msm_iommu_ijpeg_resources),
.resource = msm_iommu_ijpeg_resources,
};
static struct platform_device msm_device_iommu_vfe = {
.name = "msm_iommu",
.id = 6,
.dev = {
.parent = &msm_root_iommu_dev.dev,
},
.num_resources = ARRAY_SIZE(msm_iommu_vfe_resources),
.resource = msm_iommu_vfe_resources,
};
static struct platform_device msm_device_iommu_vcodec_a = {
.name = "msm_iommu",
.id = 7,
.dev = {
.parent = &msm_root_iommu_dev.dev,
},
.num_resources = ARRAY_SIZE(msm_iommu_vcodec_a_resources),
.resource = msm_iommu_vcodec_a_resources,
};
static struct platform_device msm_device_iommu_vcodec_b = {
.name = "msm_iommu",
.id = 8,
.dev = {
.parent = &msm_root_iommu_dev.dev,
},
.num_resources = ARRAY_SIZE(msm_iommu_vcodec_b_resources),
.resource = msm_iommu_vcodec_b_resources,
};
static struct platform_device msm_device_iommu_gfx3d = {
.name = "msm_iommu",
.id = 9,
.dev = {
.parent = &msm_root_iommu_dev.dev,
},
.num_resources = ARRAY_SIZE(msm_iommu_gfx3d_resources),
.resource = msm_iommu_gfx3d_resources,
};
static struct platform_device msm_device_iommu_gfx2d0 = {
.name = "msm_iommu",
.id = 10,
.dev = {
.parent = &msm_root_iommu_dev.dev,
},
.num_resources = ARRAY_SIZE(msm_iommu_gfx2d0_resources),
.resource = msm_iommu_gfx2d0_resources,
};
struct platform_device msm_device_iommu_gfx2d1 = {
.name = "msm_iommu",
.id = 11,
.dev = {
.parent = &msm_root_iommu_dev.dev,
},
.num_resources = ARRAY_SIZE(msm_iommu_gfx2d1_resources),
.resource = msm_iommu_gfx2d1_resources,
};
static struct msm_iommu_ctx_dev jpegd_src_ctx = {
.name = "jpegd_src",
.num = 0,
.mids = {0, -1}
};
static struct msm_iommu_ctx_dev jpegd_dst_ctx = {
.name = "jpegd_dst",
.num = 1,
.mids = {1, -1}
};
static struct msm_iommu_ctx_dev vpe_src_ctx = {
.name = "vpe_src",
.num = 0,
.mids = {0, -1}
};
static struct msm_iommu_ctx_dev vpe_dst_ctx = {
.name = "vpe_dst",
.num = 1,
.mids = {1, -1}
};
static struct msm_iommu_ctx_dev mdp_vg1_ctx = {
.name = "mdp_vg1",
.num = 0,
.mids = {0, 2, -1}
};
static struct msm_iommu_ctx_dev mdp_rgb1_ctx = {
.name = "mdp_rgb1",
.num = 1,
.mids = {1, 3, 4, 5, 6, 7, 8, 9, 10, -1}
};
static struct msm_iommu_ctx_dev mdp_vg2_ctx = {
.name = "mdp_vg2",
.num = 0,
.mids = {0, 2, -1}
};
static struct msm_iommu_ctx_dev mdp_rgb2_ctx = {
.name = "mdp_rgb2",
.num = 1,
.mids = {1, 3, 4, 5, 6, 7, 8, 9, 10, -1}
};
static struct msm_iommu_ctx_dev rot_src_ctx = {
.name = "rot_src",
.num = 0,
.mids = {0, -1}
};
static struct msm_iommu_ctx_dev rot_dst_ctx = {
.name = "rot_dst",
.num = 1,
.mids = {1, -1}
};
static struct msm_iommu_ctx_dev ijpeg_src_ctx = {
.name = "ijpeg_src",
.num = 0,
.mids = {0, -1}
};
static struct msm_iommu_ctx_dev ijpeg_dst_ctx = {
.name = "ijpeg_dst",
.num = 1,
.mids = {1, -1}
};
static struct msm_iommu_ctx_dev vfe_imgwr_ctx = {
.name = "vfe_imgwr",
.num = 0,
.mids = {2, 3, 4, 5, 6, 7, 8, -1}
};
static struct msm_iommu_ctx_dev vfe_misc_ctx = {
.name = "vfe_misc",
.num = 1,
.mids = {0, 1, 9, -1}
};
static struct msm_iommu_ctx_dev vcodec_a_stream_ctx = {
.name = "vcodec_a_stream",
.num = 0,
.mids = {2, 5, -1}
};
static struct msm_iommu_ctx_dev vcodec_a_mm1_ctx = {
.name = "vcodec_a_mm1",
.num = 1,
.mids = {0, 1, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1}
};
static struct msm_iommu_ctx_dev vcodec_b_mm2_ctx = {
.name = "vcodec_b_mm2",
.num = 0,
.mids = {0, 1, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1}
};
static struct msm_iommu_ctx_dev gfx3d_user_ctx = {
.name = "gfx3d_user",
.num = 0,
.mids = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1}
};
static struct msm_iommu_ctx_dev gfx3d_priv_ctx = {
.name = "gfx3d_priv",
.num = 1,
.mids = {16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30,
31, -1}
};
static struct msm_iommu_ctx_dev gfx2d0_2d0_ctx = {
.name = "gfx2d0_2d0",
.num = 0,
.mids = {0, 1, 2, 3, 4, 5, 6, 7, -1}
};
static struct msm_iommu_ctx_dev gfx2d1_2d1_ctx = {
.name = "gfx2d1_2d1",
.num = 0,
.mids = {0, 1, 2, 3, 4, 5, 6, 7, -1}
};
static struct platform_device msm_device_jpegd_src_ctx = {
.name = "msm_iommu_ctx",
.id = 0,
.dev = {
.parent = &msm_device_iommu_jpegd.dev,
},
};
static struct platform_device msm_device_jpegd_dst_ctx = {
.name = "msm_iommu_ctx",
.id = 1,
.dev = {
.parent = &msm_device_iommu_jpegd.dev,
},
};
static struct platform_device msm_device_vpe_src_ctx = {
.name = "msm_iommu_ctx",
.id = 2,
.dev = {
.parent = &msm_device_iommu_vpe.dev,
},
};
static struct platform_device msm_device_vpe_dst_ctx = {
.name = "msm_iommu_ctx",
.id = 3,
.dev = {
.parent = &msm_device_iommu_vpe.dev,
},
};
static struct platform_device msm_device_mdp_vg1_ctx = {
.name = "msm_iommu_ctx",
.id = 4,
.dev = {
.parent = &msm_device_iommu_mdp0.dev,
},
};
static struct platform_device msm_device_mdp_rgb1_ctx = {
.name = "msm_iommu_ctx",
.id = 5,
.dev = {
.parent = &msm_device_iommu_mdp0.dev,
},
};
static struct platform_device msm_device_mdp_vg2_ctx = {
.name = "msm_iommu_ctx",
.id = 6,
.dev = {
.parent = &msm_device_iommu_mdp1.dev,
},
};
static struct platform_device msm_device_mdp_rgb2_ctx = {
.name = "msm_iommu_ctx",
.id = 7,
.dev = {
.parent = &msm_device_iommu_mdp1.dev,
},
};
static struct platform_device msm_device_rot_src_ctx = {
.name = "msm_iommu_ctx",
.id = 8,
.dev = {
.parent = &msm_device_iommu_rot.dev,
},
};
static struct platform_device msm_device_rot_dst_ctx = {
.name = "msm_iommu_ctx",
.id = 9,
.dev = {
.parent = &msm_device_iommu_rot.dev,
},
};
static struct platform_device msm_device_ijpeg_src_ctx = {
.name = "msm_iommu_ctx",
.id = 10,
.dev = {
.parent = &msm_device_iommu_ijpeg.dev,
},
};
static struct platform_device msm_device_ijpeg_dst_ctx = {
.name = "msm_iommu_ctx",
.id = 11,
.dev = {
.parent = &msm_device_iommu_ijpeg.dev,
},
};
static struct platform_device msm_device_vfe_imgwr_ctx = {
.name = "msm_iommu_ctx",
.id = 12,
.dev = {
.parent = &msm_device_iommu_vfe.dev,
},
};
static struct platform_device msm_device_vfe_misc_ctx = {
.name = "msm_iommu_ctx",
.id = 13,
.dev = {
.parent = &msm_device_iommu_vfe.dev,
},
};
static struct platform_device msm_device_vcodec_a_stream_ctx = {
.name = "msm_iommu_ctx",
.id = 14,
.dev = {
.parent = &msm_device_iommu_vcodec_a.dev,
},
};
static struct platform_device msm_device_vcodec_a_mm1_ctx = {
.name = "msm_iommu_ctx",
.id = 15,
.dev = {
.parent = &msm_device_iommu_vcodec_a.dev,
},
};
static struct platform_device msm_device_vcodec_b_mm2_ctx = {
.name = "msm_iommu_ctx",
.id = 16,
.dev = {
.parent = &msm_device_iommu_vcodec_b.dev,
},
};
static struct platform_device msm_device_gfx3d_user_ctx = {
.name = "msm_iommu_ctx",
.id = 17,
.dev = {
.parent = &msm_device_iommu_gfx3d.dev,
},
};
static struct platform_device msm_device_gfx3d_priv_ctx = {
.name = "msm_iommu_ctx",
.id = 18,
.dev = {
.parent = &msm_device_iommu_gfx3d.dev,
},
};
static struct platform_device msm_device_gfx2d0_2d0_ctx = {
.name = "msm_iommu_ctx",
.id = 19,
.dev = {
.parent = &msm_device_iommu_gfx2d0.dev,
},
};
static struct platform_device msm_device_gfx2d1_2d1_ctx = {
.name = "msm_iommu_ctx",
.id = 20,
.dev = {
.parent = &msm_device_iommu_gfx2d1.dev,
},
};
static struct platform_device *msm_iommu_devs[] = {
&msm_device_iommu_jpegd,
&msm_device_iommu_vpe,
&msm_device_iommu_mdp0,
&msm_device_iommu_mdp1,
&msm_device_iommu_rot,
&msm_device_iommu_ijpeg,
&msm_device_iommu_vfe,
&msm_device_iommu_vcodec_a,
&msm_device_iommu_vcodec_b,
&msm_device_iommu_gfx3d,
&msm_device_iommu_gfx2d0,
&msm_device_iommu_gfx2d1,
};
static struct msm_iommu_dev *msm_iommu_data[] = {
&jpegd_iommu,
&vpe_iommu,
&mdp0_iommu,
&mdp1_iommu,
&rot_iommu,
&ijpeg_iommu,
&vfe_iommu,
&vcodec_a_iommu,
&vcodec_b_iommu,
&gfx3d_iommu,
&gfx2d0_iommu,
&gfx2d1_iommu,
};
static struct platform_device *msm_iommu_ctx_devs[] = {
&msm_device_jpegd_src_ctx,
&msm_device_jpegd_dst_ctx,
&msm_device_vpe_src_ctx,
&msm_device_vpe_dst_ctx,
&msm_device_mdp_vg1_ctx,
&msm_device_mdp_rgb1_ctx,
&msm_device_mdp_vg2_ctx,
&msm_device_mdp_rgb2_ctx,
&msm_device_rot_src_ctx,
&msm_device_rot_dst_ctx,
&msm_device_ijpeg_src_ctx,
&msm_device_ijpeg_dst_ctx,
&msm_device_vfe_imgwr_ctx,
&msm_device_vfe_misc_ctx,
&msm_device_vcodec_a_stream_ctx,
&msm_device_vcodec_a_mm1_ctx,
&msm_device_vcodec_b_mm2_ctx,
&msm_device_gfx3d_user_ctx,
&msm_device_gfx3d_priv_ctx,
&msm_device_gfx2d0_2d0_ctx,
&msm_device_gfx2d1_2d1_ctx,
};
static struct msm_iommu_ctx_dev *msm_iommu_ctx_data[] = {
&jpegd_src_ctx,
&jpegd_dst_ctx,
&vpe_src_ctx,
&vpe_dst_ctx,
&mdp_vg1_ctx,
&mdp_rgb1_ctx,
&mdp_vg2_ctx,
&mdp_rgb2_ctx,
&rot_src_ctx,
&rot_dst_ctx,
&ijpeg_src_ctx,
&ijpeg_dst_ctx,
&vfe_imgwr_ctx,
&vfe_misc_ctx,
&vcodec_a_stream_ctx,
&vcodec_a_mm1_ctx,
&vcodec_b_mm2_ctx,
&gfx3d_user_ctx,
&gfx3d_priv_ctx,
&gfx2d0_2d0_ctx,
&gfx2d1_2d1_ctx,
};
static int __init msm8x60_iommu_init(void)
{
int ret, i;
ret = platform_device_register(&msm_root_iommu_dev);
if (ret != 0) {
pr_err("Failed to register root IOMMU device!\n");
goto failure;
}
for (i = 0; i < ARRAY_SIZE(msm_iommu_devs); i++) {
ret = platform_device_add_data(msm_iommu_devs[i],
msm_iommu_data[i],
sizeof(struct msm_iommu_dev));
if (ret != 0) {
pr_err("platform_device_add_data failed, "
"i = %d\n", i);
goto failure_unwind;
}
ret = platform_device_register(msm_iommu_devs[i]);
if (ret != 0) {
pr_err("platform_device_register iommu failed, "
"i = %d\n", i);
goto failure_unwind;
}
}
for (i = 0; i < ARRAY_SIZE(msm_iommu_ctx_devs); i++) {
ret = platform_device_add_data(msm_iommu_ctx_devs[i],
msm_iommu_ctx_data[i],
sizeof(*msm_iommu_ctx_devs[i]));
if (ret != 0) {
pr_err("platform_device_add_data iommu failed, "
"i = %d\n", i);
goto failure_unwind2;
}
ret = platform_device_register(msm_iommu_ctx_devs[i]);
if (ret != 0) {
pr_err("platform_device_register ctx failed, "
"i = %d\n", i);
goto failure_unwind2;
}
}
return 0;
failure_unwind2:
while (--i >= 0)
platform_device_unregister(msm_iommu_ctx_devs[i]);
failure_unwind:
while (--i >= 0)
platform_device_unregister(msm_iommu_devs[i]);
platform_device_unregister(&msm_root_iommu_dev);
failure:
return ret;
}
static void __exit msm8x60_iommu_exit(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(msm_iommu_ctx_devs); i++)
platform_device_unregister(msm_iommu_ctx_devs[i]);
for (i = 0; i < ARRAY_SIZE(msm_iommu_devs); ++i)
platform_device_unregister(msm_iommu_devs[i]);
platform_device_unregister(&msm_root_iommu_dev);
}
subsys_initcall(msm8x60_iommu_init);
module_exit(msm8x60_iommu_exit);
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Stepan Moskovchenko <stepanm@codeaurora.org>");

2
arch/arm/mach-msm/devices-msm7x30.c
View File

@ -21,10 +21,10 @@
#include <mach/irqs.h>
#include <mach/msm_iomap.h>
#include <mach/dma.h>
#include <mach/board.h>
#include "devices.h"
#include "smd_private.h"
#include "common.h"
#include <asm/mach/flash.h>

2
arch/arm/mach-msm/devices-qsd8x50.c
View File

@ -21,9 +21,9 @@
#include <mach/irqs.h>
#include <mach/msm_iomap.h>
#include <mach/dma.h>
#include <mach/board.h>
#include "devices.h"
#include "common.h"
#include <asm/mach/flash.h>

38
arch/arm/mach-msm/include/mach/board.h
View File

@ -1,38 +0,0 @@
/* arch/arm/mach-msm/include/mach/board.h
*
* Copyright (C) 2007 Google, Inc.
* Author: Brian Swetland <swetland@google.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __ASM_ARCH_MSM_BOARD_H
#define __ASM_ARCH_MSM_BOARD_H
#include <linux/types.h>
#include <linux/platform_data/mmc-msm_sdcc.h>
/* common init routines for use by arch/arm/mach-msm/board-*.c */
void __init msm_add_devices(void);
void __init msm_init_irq(void);
void __init msm_init_gpio(void);
int __init msm_add_sdcc(unsigned int controller,
struct msm_mmc_platform_data *plat,
unsigned int stat_irq, unsigned long stat_irq_flags);
#if defined(CONFIG_MSM_SMD) && defined(CONFIG_DEBUG_FS)
int smd_debugfs_init(void);
#else
static inline int smd_debugfs_init(void) { return 0; }
#endif
#endif

46
arch/arm/mach-msm/include/mach/msm_iomap-8960.h
View File

@ -1,46 +0,0 @@
/*
* Copyright (C) 2007 Google, Inc.
* Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
* Author: Brian Swetland <swetland@google.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
* The MSM peripherals are spread all over across 768MB of physical
* space, which makes just having a simple IO_ADDRESS macro to slide
* them into the right virtual location rough. Instead, we will
* provide a master phys->virt mapping for peripherals here.
*
*/
#ifndef __ASM_ARCH_MSM_IOMAP_8960_H
#define __ASM_ARCH_MSM_IOMAP_8960_H
/* Physical base address and size of peripherals.
* Ordered by the virtual base addresses they will be mapped at.
*
* If you add or remove entries here, you'll want to edit the
* msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
* changes.
*
*/
#define MSM8960_TMR_PHYS 0x0200A000
#define MSM8960_TMR_SIZE SZ_4K
#define MSM8960_TMR0_PHYS 0x0208A000
#define MSM8960_TMR0_SIZE SZ_4K
#ifdef CONFIG_DEBUG_MSM8960_UART
#define MSM_DEBUG_UART_BASE 0xF0040000
#define MSM_DEBUG_UART_PHYS 0x16440000
#endif
#endif

53
arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
View File

@ -1,53 +0,0 @@
/*
* Copyright (C) 2007 Google, Inc.
* Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
* Author: Brian Swetland <swetland@google.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
* The MSM peripherals are spread all over across 768MB of physical
* space, which makes just having a simple IO_ADDRESS macro to slide
* them into the right virtual location rough. Instead, we will
* provide a master phys->virt mapping for peripherals here.
*
*/
#ifndef __ASM_ARCH_MSM_IOMAP_8X60_H
#define __ASM_ARCH_MSM_IOMAP_8X60_H
/* Physical base address and size of peripherals.
* Ordered by the virtual base addresses they will be mapped at.
*
* MSM_VIC_BASE must be an value that can be loaded via a "mov"
* instruction, otherwise entry-macro.S will not compile.
*
* If you add or remove entries here, you'll want to edit the
* msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
* changes.
*
*/
#define MSM_TLMM_BASE IOMEM(0xF0004000)
#define MSM_TLMM_PHYS 0x00800000
#define MSM_TLMM_SIZE SZ_16K
#define MSM8X60_TMR_PHYS 0x02000000
#define MSM8X60_TMR_SIZE SZ_4K
#define MSM8X60_TMR0_PHYS 0x02040000
#define MSM8X60_TMR0_SIZE SZ_4K
#ifdef CONFIG_DEBUG_MSM8660_UART
#define MSM_DEBUG_UART_BASE 0xF0040000
#define MSM_DEBUG_UART_PHYS 0x19C40000
#endif
#endif

17
arch/arm/mach-msm/include/mach/msm_iomap.h
View File

@ -45,25 +45,8 @@
#include "msm_iomap-7x00.h"
#endif
#include "msm_iomap-8x60.h"
#include "msm_iomap-8960.h"
#define MSM_DEBUG_UART_SIZE SZ_4K
#if defined(CONFIG_DEBUG_MSM_UART1)
#define MSM_DEBUG_UART_BASE 0xE1000000
#define MSM_DEBUG_UART_PHYS MSM_UART1_PHYS
#elif defined(CONFIG_DEBUG_MSM_UART2)
#define MSM_DEBUG_UART_BASE 0xE1000000
#define MSM_DEBUG_UART_PHYS MSM_UART2_PHYS
#elif defined(CONFIG_DEBUG_MSM_UART3)
#define MSM_DEBUG_UART_BASE 0xE1000000
#define MSM_DEBUG_UART_PHYS MSM_UART3_PHYS
#endif
/* Virtual addresses shared across all MSM targets. */
#define MSM_CSR_BASE IOMEM(0xE0001000)
#define MSM_TMR_BASE IOMEM(0xF0200000)
#define MSM_TMR0_BASE IOMEM(0xF0201000)
#define MSM_GPIO1_BASE IOMEM(0xE0003000)
#define MSM_GPIO2_BASE IOMEM(0xE0004000)

63
arch/arm/mach-msm/include/mach/uncompress.h
View File

@ -1,63 +0,0 @@
/*
* Copyright (C) 2007 Google, Inc.
* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __ASM_ARCH_MSM_UNCOMPRESS_H
#define __ASM_ARCH_MSM_UNCOMPRESS_H
#include <asm/barrier.h>
#include <asm/processor.h>
#include <mach/msm_iomap.h>
#define UART_CSR (*(volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x08))
#define UART_TF (*(volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x0c))
#define UART_DM_SR (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x08)))
#define UART_DM_CR (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x10)))
#define UART_DM_ISR (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x14)))
#define UART_DM_NCHAR (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x40)))
#define UART_DM_TF (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x70)))
static void putc(int c)
{
#if defined(MSM_DEBUG_UART_PHYS)
#ifdef CONFIG_MSM_HAS_DEBUG_UART_HS
/*
* Wait for TX_READY to be set; but skip it if we have a
* TX underrun.
*/
if (!(UART_DM_SR & 0x08))
while (!(UART_DM_ISR & 0x80))
cpu_relax();
UART_DM_CR = 0x300;
UART_DM_NCHAR = 0x1;
UART_DM_TF = c;
#else
while (!(UART_CSR & 0x04))
cpu_relax();
UART_TF = c;
#endif
#endif
}
static inline void flush(void)
{
}
static inline void arch_decomp_setup(void)
{
}
#endif

67
arch/arm/mach-msm/io.c
View File

@ -18,6 +18,7 @@
*/
#include <linux/kernel.h>
#include <linux/bug.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/export.h>
@ -27,8 +28,6 @@
#include <mach/msm_iomap.h>
#include <asm/mach/map.h>
#include <mach/board.h>
#include "common.h"
#define MSM_CHIP_DEVICE_TYPE(name, chip, mem_type) { \
@ -52,26 +51,38 @@ static struct map_desc msm_io_desc[] __initdata = {
MSM_CHIP_DEVICE_TYPE(GPIO1, MSM7X00, MT_DEVICE_NONSHARED),
MSM_CHIP_DEVICE_TYPE(GPIO2, MSM7X00, MT_DEVICE_NONSHARED),
MSM_DEVICE_TYPE(CLK_CTL, MT_DEVICE_NONSHARED),
#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
defined(CONFIG_DEBUG_MSM_UART3)
MSM_DEVICE_TYPE(DEBUG_UART, MT_DEVICE_NONSHARED),
#endif
{
.virtual = (unsigned long) MSM_SHARED_RAM_BASE,
.pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS),
.length = MSM_SHARED_RAM_SIZE,
.type = MT_DEVICE,
},
#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
defined(CONFIG_DEBUG_MSM_UART3)
{
/* Must be last: virtual and pfn filled in by debug_ll_addr() */
.length = SZ_4K,
.type = MT_DEVICE_NONSHARED,
}
#endif
};
void __init msm_map_common_io(void)
{
size_t size = ARRAY_SIZE(msm_io_desc);
/* Make sure the peripheral register window is closed, since
* we will use PTE flags (TEX[1]=1,B=0,C=1) to determine which
* pages are peripheral interface or not.
*/
asm("mcr p15, 0, %0, c15, c2, 4" : : "r" (0));
iotable_init(msm_io_desc, ARRAY_SIZE(msm_io_desc));
#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
defined(CONFIG_DEBUG_MSM_UART3)
debug_ll_addr(&msm_io_desc[size - 1].pfn,
&msm_io_desc[size - 1].virtual);
msm_io_desc[size - 1].pfn = __phys_to_pfn(msm_io_desc[size - 1].pfn);
#endif
iotable_init(msm_io_desc, size);
}
#endif
@ -87,10 +98,6 @@ static struct map_desc qsd8x50_io_desc[] __initdata = {
MSM_DEVICE(SCPLL),
MSM_DEVICE(AD5),
MSM_DEVICE(MDC),
#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
defined(CONFIG_DEBUG_MSM_UART3)
MSM_DEVICE(DEBUG_UART),
#endif
{
.virtual = (unsigned long) MSM_SHARED_RAM_BASE,
.pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS),
@ -101,40 +108,11 @@ static struct map_desc qsd8x50_io_desc[] __initdata = {
void __init msm_map_qsd8x50_io(void)
{
debug_ll_io_init();
iotable_init(qsd8x50_io_desc, ARRAY_SIZE(qsd8x50_io_desc));
}
#endif /* CONFIG_ARCH_QSD8X50 */
#ifdef CONFIG_ARCH_MSM8X60
static struct map_desc msm8x60_io_desc[] __initdata = {
MSM_CHIP_DEVICE(TMR, MSM8X60),
MSM_CHIP_DEVICE(TMR0, MSM8X60),
#ifdef CONFIG_DEBUG_MSM8660_UART
MSM_DEVICE(DEBUG_UART),
#endif
};
void __init msm_map_msm8x60_io(void)
{
iotable_init(msm8x60_io_desc, ARRAY_SIZE(msm8x60_io_desc));
}
#endif /* CONFIG_ARCH_MSM8X60 */
#ifdef CONFIG_ARCH_MSM8960
static struct map_desc msm8960_io_desc[] __initdata = {
MSM_CHIP_DEVICE(TMR, MSM8960),
MSM_CHIP_DEVICE(TMR0, MSM8960),
#ifdef CONFIG_DEBUG_MSM8960_UART
MSM_DEVICE(DEBUG_UART),
#endif
};
void __init msm_map_msm8960_io(void)
{
iotable_init(msm8960_io_desc, ARRAY_SIZE(msm8960_io_desc));
}
#endif /* CONFIG_ARCH_MSM8960 */
#ifdef CONFIG_ARCH_MSM7X30
static struct map_desc msm7x30_io_desc[] __initdata = {
MSM_DEVICE(VIC),
@ -150,10 +128,6 @@ static struct map_desc msm7x30_io_desc[] __initdata = {
MSM_DEVICE(SAW),
MSM_DEVICE(GCC),
MSM_DEVICE(TCSR),
#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
defined(CONFIG_DEBUG_MSM_UART3)
MSM_DEVICE(DEBUG_UART),
#endif
{
.virtual = (unsigned long) MSM_SHARED_RAM_BASE,
.pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS),
@ -164,10 +138,12 @@ static struct map_desc msm7x30_io_desc[] __initdata = {
void __init msm_map_msm7x30_io(void)
{
debug_ll_io_init();
iotable_init(msm7x30_io_desc, ARRAY_SIZE(msm7x30_io_desc));
}
#endif /* CONFIG_ARCH_MSM7X30 */
#ifdef CONFIG_ARCH_MSM7X00A
void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size,
unsigned int mtype, void *caller)
{
@ -182,3 +158,4 @@ void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size,
return __arm_ioremap_caller(phys_addr, size, mtype, caller);
}
#endif

143
arch/arm/mach-msm/timer.c
View File

@ -16,6 +16,7 @@
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/cpu.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
@ -26,7 +27,6 @@
#include <linux/sched_clock.h>
#include <asm/mach/time.h>
#include <asm/localtimer.h>
#include "common.h"
@ -49,7 +49,7 @@ static void __iomem *sts_base;
static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
{
struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
struct clock_event_device *evt = dev_id;
/* Stop the timer tick */
if (evt->mode == CLOCK_EVT_MODE_ONESHOT) {
u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
@ -101,18 +101,7 @@ static void msm_timer_set_mode(enum clock_event_mode mode,
writel_relaxed(ctrl, event_base + TIMER_ENABLE);
}
static struct clock_event_device msm_clockevent = {
.name = "gp_timer",
.features = CLOCK_EVT_FEAT_ONESHOT,
.rating = 200,
.set_next_event = msm_timer_set_next_event,
.set_mode = msm_timer_set_mode,
};
static union {
struct clock_event_device *evt;
struct clock_event_device * __percpu *percpu_evt;
} msm_evt;
static struct clock_event_device __percpu *msm_evt;
static void __iomem *source_base;
@ -138,23 +127,34 @@ static struct clocksource msm_clocksource = {
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
#ifdef CONFIG_LOCAL_TIMERS
static int msm_timer_irq;
static int msm_timer_has_ppi;
static int msm_local_timer_setup(struct clock_event_device *evt)
{
/* Use existing clock_event for cpu 0 */
if (!smp_processor_id())
return 0;
int cpu = smp_processor_id();
int err;
evt->irq = msm_clockevent.irq;
evt->name = "local_timer";
evt->features = msm_clockevent.features;
evt->rating = msm_clockevent.rating;
evt->irq = msm_timer_irq;
evt->name = "msm_timer";
evt->features = CLOCK_EVT_FEAT_ONESHOT;
evt->rating = 200;
evt->set_mode = msm_timer_set_mode;
evt->set_next_event = msm_timer_set_next_event;
evt->cpumask = cpumask_of(cpu);
clockevents_config_and_register(evt, GPT_HZ, 4, 0xffffffff);
if (msm_timer_has_ppi) {
enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
} else {
err = request_irq(evt->irq, msm_timer_interrupt,
IRQF_TIMER | IRQF_NOBALANCING |
IRQF_TRIGGER_RISING, "gp_timer", evt);
if (err)
pr_err("request_irq failed\n");
}
*__this_cpu_ptr(msm_evt.percpu_evt) = evt;
clockevents_config_and_register(evt, GPT_HZ, 4, 0xf0000000);
enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
return 0;
}
@ -164,11 +164,28 @@ static void msm_local_timer_stop(struct clock_event_device *evt)
disable_percpu_irq(evt->irq);
}
static struct local_timer_ops msm_local_timer_ops = {
.setup = msm_local_timer_setup,
.stop = msm_local_timer_stop,
static int msm_timer_cpu_notify(struct notifier_block *self,
unsigned long action, void *hcpu)
{
/*
* Grab cpu pointer in each case to avoid spurious
* preemptible warnings
*/
switch (action & ~CPU_TASKS_FROZEN) {
case CPU_STARTING:
msm_local_timer_setup(this_cpu_ptr(msm_evt));
break;
case CPU_DYING:
msm_local_timer_stop(this_cpu_ptr(msm_evt));
break;
}
return NOTIFY_OK;
}
static struct notifier_block msm_timer_cpu_nb = {
.notifier_call = msm_timer_cpu_notify,
};
#endif /* CONFIG_LOCAL_TIMERS */
static notrace u32 msm_sched_clock_read(void)
{
@ -178,38 +195,35 @@ static notrace u32 msm_sched_clock_read(void)
static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
bool percpu)
{
struct clock_event_device *ce = &msm_clockevent;
struct clocksource *cs = &msm_clocksource;
int res;
int res = 0;
ce->cpumask = cpumask_of(0);
ce->irq = irq;
msm_timer_irq = irq;
msm_timer_has_ppi = percpu;
clockevents_config_and_register(ce, GPT_HZ, 4, 0xffffffff);
if (percpu) {
msm_evt.percpu_evt = alloc_percpu(struct clock_event_device *);
if (!msm_evt.percpu_evt) {
pr_err("memory allocation failed for %s\n", ce->name);
goto err;
}
*__this_cpu_ptr(msm_evt.percpu_evt) = ce;
res = request_percpu_irq(ce->irq, msm_timer_interrupt,
ce->name, msm_evt.percpu_evt);
if (!res) {
enable_percpu_irq(ce->irq, IRQ_TYPE_EDGE_RISING);
#ifdef CONFIG_LOCAL_TIMERS
local_timer_register(&msm_local_timer_ops);
#endif
}
} else {
msm_evt.evt = ce;
res = request_irq(ce->irq, msm_timer_interrupt,
IRQF_TIMER | IRQF_NOBALANCING |
IRQF_TRIGGER_RISING, ce->name, &msm_evt.evt);
msm_evt = alloc_percpu(struct clock_event_device);
if (!msm_evt) {
pr_err("memory allocation failed for clockevents\n");
goto err;
}
if (percpu)
res = request_percpu_irq(irq, msm_timer_interrupt,
"gp_timer", msm_evt);
if (res) {
pr_err("request_percpu_irq failed\n");
} else {
res = register_cpu_notifier(&msm_timer_cpu_nb);
if (res) {
free_percpu_irq(irq, msm_evt);
goto err;
}
/* Immediately configure the timer on the boot CPU */
msm_local_timer_setup(__this_cpu_ptr(msm_evt));
}
if (res)
pr_err("request_irq failed for %s\n", ce->name);
err:
writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
res = clocksource_register_hz(cs, dgt_hz);
@ -219,15 +233,8 @@ err:
}
#ifdef CONFIG_OF
static const struct of_device_id msm_timer_match[] __initconst = {
{ .compatible = "qcom,kpss-timer" },
{ .compatible = "qcom,scss-timer" },
{ },
};
void __init msm_dt_timer_init(void)
static void __init msm_dt_timer_init(struct device_node *np)
{
struct device_node *np;
u32 freq;
int irq;
struct resource res;
@ -235,12 +242,6 @@ void __init msm_dt_timer_init(void)
void __iomem *base;
void __iomem *cpu0_base;
np = of_find_matching_node(NULL, msm_timer_match);
if (!np) {
pr_err("Can't find msm timer DT node\n");
return;
}
base = of_iomap(np, 0);
if (!base) {
pr_err("Failed to map event base\n");
@ -283,6 +284,8 @@ void __init msm_dt_timer_init(void)
msm_timer_init(freq, 32, irq, !!percpu_offset);
}
CLOCKSOURCE_OF_DECLARE(kpss_timer, "qcom,kpss-timer", msm_dt_timer_init);
CLOCKSOURCE_OF_DECLARE(scss_timer, "qcom,scss-timer", msm_dt_timer_init);
#endif
static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source,

19
arch/arm/mach-mvebu/platsmp.c
View File

@ -82,28 +82,11 @@ static int armada_xp_boot_secondary(unsigned int cpu, struct task_struct *idle)
static void __init armada_xp_smp_init_cpus(void)
{
struct device_node *np;
unsigned int i, ncores;
unsigned int ncores = num_possible_cpus();
np = of_find_node_by_name(NULL, "cpus");
if (!np)
panic("No 'cpus' node found\n");
ncores = of_get_child_count(np);
if (ncores == 0 || ncores > ARMADA_XP_MAX_CPUS)
panic("Invalid number of CPUs in DT\n");
/* Limit possible CPUs to defconfig */
if (ncores > nr_cpu_ids) {
pr_warn("SMP: %d CPUs physically present. Only %d configured.",
ncores, nr_cpu_ids);
pr_warn("Clipping CPU count to %d\n", nr_cpu_ids);
ncores = nr_cpu_ids;
}
for (i = 0; i < ncores; i++)
set_cpu_possible(i, true);
set_smp_cross_call(armada_mpic_send_doorbell);
}

3
arch/arm/mach-omap2/Kconfig
View File

@ -37,9 +37,8 @@ config ARCH_OMAP4
select CACHE_L2X0
select CPU_V7
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if LOCAL_TIMERS
select HAVE_ARM_TWD if SMP
select HAVE_SMP
select LOCAL_TIMERS if SMP
select OMAP_INTERCONNECT
select PL310_ERRATA_588369
select PL310_ERRATA_727915

2
arch/arm/mach-omap2/board-am3517evm.c
View File

@ -21,7 +21,7 @@
#include <linux/clk.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/i2c/pca953x.h>
#include <linux/platform_data/pca953x.h>
#include <linux/can/platform/ti_hecc.h>
#include <linux/davinci_emac.h>
#include <linux/mmc/host.h>

318
arch/arm/mach-omap2/cm-regbits-24xx.h
View File

@ -14,439 +14,121 @@
* published by the Free Software Foundation.
*/
/* Bits shared between registers */
/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
#define OMAP24XX_EN_CAM_SHIFT 31
#define OMAP24XX_EN_CAM_MASK (1 << 31)
#define OMAP24XX_EN_WDT4_SHIFT 29
#define OMAP24XX_EN_WDT4_MASK (1 << 29)
#define OMAP2420_EN_WDT3_SHIFT 28
#define OMAP2420_EN_WDT3_MASK (1 << 28)
#define OMAP24XX_EN_MSPRO_SHIFT 27
#define OMAP24XX_EN_MSPRO_MASK (1 << 27)
#define OMAP24XX_EN_FAC_SHIFT 25
#define OMAP24XX_EN_FAC_MASK (1 << 25)
#define OMAP2420_EN_EAC_SHIFT 24
#define OMAP2420_EN_EAC_MASK (1 << 24)
#define OMAP24XX_EN_HDQ_SHIFT 23
#define OMAP24XX_EN_HDQ_MASK (1 << 23)
#define OMAP2420_EN_I2C2_SHIFT 20
#define OMAP2420_EN_I2C2_MASK (1 << 20)
#define OMAP2420_EN_I2C1_SHIFT 19
#define OMAP2420_EN_I2C1_MASK (1 << 19)
/* CM_FCLKEN2_CORE and CM_ICLKEN2_CORE shared bits */
#define OMAP2430_EN_MCBSP5_SHIFT 5
#define OMAP2430_EN_MCBSP5_MASK (1 << 5)
#define OMAP2430_EN_MCBSP4_SHIFT 4
#define OMAP2430_EN_MCBSP4_MASK (1 << 4)
#define OMAP2430_EN_MCBSP3_SHIFT 3
#define OMAP2430_EN_MCBSP3_MASK (1 << 3)
#define OMAP24XX_EN_SSI_SHIFT 1
#define OMAP24XX_EN_SSI_MASK (1 << 1)
/* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */
#define OMAP24XX_EN_MPU_WDT_SHIFT 3
#define OMAP24XX_EN_MPU_WDT_MASK (1 << 3)
/* Bits specific to each register */
/* CM_IDLEST_MPU */
/* 2430 only */
#define OMAP2430_ST_MPU_MASK (1 << 0)
/* CM_CLKSEL_MPU */
#define OMAP24XX_CLKSEL_MPU_SHIFT 0
#define OMAP24XX_CLKSEL_MPU_MASK (0x1f << 0)
#define OMAP24XX_CLKSEL_MPU_WIDTH 5
/* CM_CLKSTCTRL_MPU */
#define OMAP24XX_AUTOSTATE_MPU_SHIFT 0
#define OMAP24XX_AUTOSTATE_MPU_MASK (1 << 0)
/* CM_FCLKEN1_CORE specific bits*/
#define OMAP24XX_EN_TV_SHIFT 2
#define OMAP24XX_EN_TV_MASK (1 << 2)
#define OMAP24XX_EN_DSS2_SHIFT 1
#define OMAP24XX_EN_DSS2_MASK (1 << 1)
#define OMAP24XX_EN_DSS1_SHIFT 0
#define OMAP24XX_EN_DSS1_MASK (1 << 0)
/* CM_FCLKEN2_CORE specific bits */
#define OMAP2430_EN_I2CHS2_SHIFT 20
#define OMAP2430_EN_I2CHS2_MASK (1 << 20)
#define OMAP2430_EN_I2CHS1_SHIFT 19
#define OMAP2430_EN_I2CHS1_MASK (1 << 19)
#define OMAP2430_EN_MMCHSDB2_SHIFT 17
#define OMAP2430_EN_MMCHSDB2_MASK (1 << 17)
#define OMAP2430_EN_MMCHSDB1_SHIFT 16
#define OMAP2430_EN_MMCHSDB1_MASK (1 << 16)
/* CM_ICLKEN1_CORE specific bits */
#define OMAP24XX_EN_MAILBOXES_SHIFT 30
#define OMAP24XX_EN_MAILBOXES_MASK (1 << 30)
#define OMAP24XX_EN_DSS_SHIFT 0
#define OMAP24XX_EN_DSS_MASK (1 << 0)
/* CM_ICLKEN2_CORE specific bits */
/* CM_ICLKEN3_CORE */
/* 2430 only */
#define OMAP2430_EN_SDRC_SHIFT 2
#define OMAP2430_EN_SDRC_MASK (1 << 2)
/* CM_ICLKEN4_CORE */
#define OMAP24XX_EN_PKA_SHIFT 4
#define OMAP24XX_EN_PKA_MASK (1 << 4)
#define OMAP24XX_EN_AES_SHIFT 3
#define OMAP24XX_EN_AES_MASK (1 << 3)
#define OMAP24XX_EN_RNG_SHIFT 2
#define OMAP24XX_EN_RNG_MASK (1 << 2)
#define OMAP24XX_EN_SHA_SHIFT 1
#define OMAP24XX_EN_SHA_MASK (1 << 1)
#define OMAP24XX_EN_DES_SHIFT 0
#define OMAP24XX_EN_DES_MASK (1 << 0)
/* CM_IDLEST1_CORE specific bits */
#define OMAP24XX_ST_MAILBOXES_SHIFT 30
#define OMAP24XX_ST_MAILBOXES_MASK (1 << 30)
#define OMAP24XX_ST_WDT4_SHIFT 29
#define OMAP24XX_ST_WDT4_MASK (1 << 29)
#define OMAP2420_ST_WDT3_SHIFT 28
#define OMAP2420_ST_WDT3_MASK (1 << 28)
#define OMAP24XX_ST_MSPRO_SHIFT 27
#define OMAP24XX_ST_MSPRO_MASK (1 << 27)
#define OMAP24XX_ST_FAC_SHIFT 25
#define OMAP24XX_ST_FAC_MASK (1 << 25)
#define OMAP2420_ST_EAC_SHIFT 24
#define OMAP2420_ST_EAC_MASK (1 << 24)
#define OMAP24XX_ST_HDQ_SHIFT 23
#define OMAP24XX_ST_HDQ_MASK (1 << 23)
#define OMAP2420_ST_I2C2_SHIFT 20
#define OMAP2420_ST_I2C2_MASK (1 << 20)
#define OMAP2430_ST_I2CHS1_SHIFT 19
#define OMAP2430_ST_I2CHS1_MASK (1 << 19)
#define OMAP2420_ST_I2C1_SHIFT 19
#define OMAP2420_ST_I2C1_MASK (1 << 19)
#define OMAP2430_ST_I2CHS2_SHIFT 20
#define OMAP2430_ST_I2CHS2_MASK (1 << 20)
#define OMAP24XX_ST_MCBSP2_SHIFT 16
#define OMAP24XX_ST_MCBSP2_MASK (1 << 16)
#define OMAP24XX_ST_MCBSP1_SHIFT 15
#define OMAP24XX_ST_MCBSP1_MASK (1 << 15)
#define OMAP24XX_ST_DSS_SHIFT 0
#define OMAP24XX_ST_DSS_MASK (1 << 0)
/* CM_IDLEST2_CORE */
#define OMAP2430_ST_MCBSP5_SHIFT 5
#define OMAP2430_ST_MCBSP5_MASK (1 << 5)
#define OMAP2430_ST_MCBSP4_SHIFT 4
#define OMAP2430_ST_MCBSP4_MASK (1 << 4)
#define OMAP2430_ST_MCBSP3_SHIFT 3
#define OMAP2430_ST_MCBSP3_MASK (1 << 3)
#define OMAP24XX_ST_SSI_SHIFT 1
#define OMAP24XX_ST_SSI_MASK (1 << 1)
/* CM_IDLEST3_CORE */
/* 2430 only */
#define OMAP2430_ST_SDRC_MASK (1 << 2)
/* CM_IDLEST4_CORE */
#define OMAP24XX_ST_PKA_SHIFT 4
#define OMAP24XX_ST_PKA_MASK (1 << 4)
#define OMAP24XX_ST_AES_SHIFT 3
#define OMAP24XX_ST_AES_MASK (1 << 3)
#define OMAP24XX_ST_RNG_SHIFT 2
#define OMAP24XX_ST_RNG_MASK (1 << 2)
#define OMAP24XX_ST_SHA_SHIFT 1
#define OMAP24XX_ST_SHA_MASK (1 << 1)
#define OMAP24XX_ST_DES_SHIFT 0
#define OMAP24XX_ST_DES_MASK (1 << 0)
/* CM_AUTOIDLE1_CORE */
#define OMAP24XX_AUTO_CAM_MASK (1 << 31)
#define OMAP24XX_AUTO_MAILBOXES_MASK (1 << 30)
#define OMAP24XX_AUTO_WDT4_MASK (1 << 29)
#define OMAP2420_AUTO_WDT3_MASK (1 << 28)
#define OMAP24XX_AUTO_MSPRO_MASK (1 << 27)
#define OMAP2420_AUTO_MMC_MASK (1 << 26)
#define OMAP24XX_AUTO_FAC_MASK (1 << 25)
#define OMAP2420_AUTO_EAC_MASK (1 << 24)
#define OMAP24XX_AUTO_HDQ_MASK (1 << 23)
#define OMAP24XX_AUTO_UART2_MASK (1 << 22)
#define OMAP24XX_AUTO_UART1_MASK (1 << 21)
#define OMAP24XX_AUTO_I2C2_MASK (1 << 20)
#define OMAP24XX_AUTO_I2C1_MASK (1 << 19)
#define OMAP24XX_AUTO_MCSPI2_MASK (1 << 18)
#define OMAP24XX_AUTO_MCSPI1_MASK (1 << 17)
#define OMAP24XX_AUTO_MCBSP2_MASK (1 << 16)
#define OMAP24XX_AUTO_MCBSP1_MASK (1 << 15)
#define OMAP24XX_AUTO_GPT12_MASK (1 << 14)
#define OMAP24XX_AUTO_GPT11_MASK (1 << 13)
#define OMAP24XX_AUTO_GPT10_MASK (1 << 12)
#define OMAP24XX_AUTO_GPT9_MASK (1 << 11)
#define OMAP24XX_AUTO_GPT8_MASK (1 << 10)
#define OMAP24XX_AUTO_GPT7_MASK (1 << 9)
#define OMAP24XX_AUTO_GPT6_MASK (1 << 8)
#define OMAP24XX_AUTO_GPT5_MASK (1 << 7)
#define OMAP24XX_AUTO_GPT4_MASK (1 << 6)
#define OMAP24XX_AUTO_GPT3_MASK (1 << 5)
#define OMAP24XX_AUTO_GPT2_MASK (1 << 4)
#define OMAP2420_AUTO_VLYNQ_MASK (1 << 3)
#define OMAP24XX_AUTO_DSS_MASK (1 << 0)
/* CM_AUTOIDLE2_CORE */
#define OMAP2430_AUTO_MDM_INTC_MASK (1 << 11)
#define OMAP2430_AUTO_GPIO5_MASK (1 << 10)
#define OMAP2430_AUTO_MCSPI3_MASK (1 << 9)
#define OMAP2430_AUTO_MMCHS2_MASK (1 << 8)
#define OMAP2430_AUTO_MMCHS1_MASK (1 << 7)
#define OMAP2430_AUTO_USBHS_MASK (1 << 6)
#define OMAP2430_AUTO_MCBSP5_MASK (1 << 5)
#define OMAP2430_AUTO_MCBSP4_MASK (1 << 4)
#define OMAP2430_AUTO_MCBSP3_MASK (1 << 3)
#define OMAP24XX_AUTO_UART3_MASK (1 << 2)
#define OMAP24XX_AUTO_SSI_MASK (1 << 1)
#define OMAP24XX_AUTO_USB_MASK (1 << 0)
/* CM_AUTOIDLE3_CORE */
#define OMAP24XX_AUTO_SDRC_SHIFT 2
#define OMAP24XX_AUTO_SDRC_MASK (1 << 2)
#define OMAP24XX_AUTO_GPMC_SHIFT 1
#define OMAP24XX_AUTO_GPMC_MASK (1 << 1)
#define OMAP24XX_AUTO_SDMA_SHIFT 0
#define OMAP24XX_AUTO_SDMA_MASK (1 << 0)
/* CM_AUTOIDLE4_CORE */
#define OMAP24XX_AUTO_PKA_MASK (1 << 4)
#define OMAP24XX_AUTO_AES_MASK (1 << 3)
#define OMAP24XX_AUTO_RNG_MASK (1 << 2)
#define OMAP24XX_AUTO_SHA_MASK (1 << 1)
#define OMAP24XX_AUTO_DES_MASK (1 << 0)
/* CM_CLKSEL1_CORE */
#define OMAP24XX_CLKSEL_USB_SHIFT 25
#define OMAP24XX_CLKSEL_USB_MASK (0x7 << 25)
#define OMAP24XX_CLKSEL_SSI_SHIFT 20
#define OMAP24XX_CLKSEL_SSI_MASK (0x1f << 20)
#define OMAP2420_CLKSEL_VLYNQ_SHIFT 15
#define OMAP2420_CLKSEL_VLYNQ_MASK (0x1f << 15)
#define OMAP24XX_CLKSEL_DSS2_SHIFT 13
#define OMAP24XX_CLKSEL_DSS2_MASK (0x1 << 13)
#define OMAP24XX_CLKSEL_DSS1_SHIFT 8
#define OMAP24XX_CLKSEL_DSS1_MASK (0x1f << 8)
#define OMAP24XX_CLKSEL_L4_SHIFT 5
#define OMAP24XX_CLKSEL_L4_MASK (0x3 << 5)
#define OMAP24XX_CLKSEL_L4_WIDTH 2
#define OMAP24XX_CLKSEL_L3_SHIFT 0
#define OMAP24XX_CLKSEL_L3_MASK (0x1f << 0)
#define OMAP24XX_CLKSEL_L3_WIDTH 5
/* CM_CLKSEL2_CORE */
#define OMAP24XX_CLKSEL_GPT12_SHIFT 22
#define OMAP24XX_CLKSEL_GPT12_MASK (0x3 << 22)
#define OMAP24XX_CLKSEL_GPT11_SHIFT 20
#define OMAP24XX_CLKSEL_GPT11_MASK (0x3 << 20)
#define OMAP24XX_CLKSEL_GPT10_SHIFT 18
#define OMAP24XX_CLKSEL_GPT10_MASK (0x3 << 18)
#define OMAP24XX_CLKSEL_GPT9_SHIFT 16
#define OMAP24XX_CLKSEL_GPT9_MASK (0x3 << 16)
#define OMAP24XX_CLKSEL_GPT8_SHIFT 14
#define OMAP24XX_CLKSEL_GPT8_MASK (0x3 << 14)
#define OMAP24XX_CLKSEL_GPT7_SHIFT 12
#define OMAP24XX_CLKSEL_GPT7_MASK (0x3 << 12)
#define OMAP24XX_CLKSEL_GPT6_SHIFT 10
#define OMAP24XX_CLKSEL_GPT6_MASK (0x3 << 10)
#define OMAP24XX_CLKSEL_GPT5_SHIFT 8
#define OMAP24XX_CLKSEL_GPT5_MASK (0x3 << 8)
#define OMAP24XX_CLKSEL_GPT4_SHIFT 6
#define OMAP24XX_CLKSEL_GPT4_MASK (0x3 << 6)
#define OMAP24XX_CLKSEL_GPT3_SHIFT 4
#define OMAP24XX_CLKSEL_GPT3_MASK (0x3 << 4)
#define OMAP24XX_CLKSEL_GPT2_SHIFT 2
#define OMAP24XX_CLKSEL_GPT2_MASK (0x3 << 2)
/* CM_CLKSTCTRL_CORE */
#define OMAP24XX_AUTOSTATE_DSS_SHIFT 2
#define OMAP24XX_AUTOSTATE_DSS_MASK (1 << 2)
#define OMAP24XX_AUTOSTATE_L4_SHIFT 1
#define OMAP24XX_AUTOSTATE_L4_MASK (1 << 1)
#define OMAP24XX_AUTOSTATE_L3_SHIFT 0
#define OMAP24XX_AUTOSTATE_L3_MASK (1 << 0)
/* CM_FCLKEN_GFX */
#define OMAP24XX_EN_3D_SHIFT 2
#define OMAP24XX_EN_3D_MASK (1 << 2)
#define OMAP24XX_EN_2D_SHIFT 1
#define OMAP24XX_EN_2D_MASK (1 << 1)
/* CM_ICLKEN_GFX specific bits */
/* CM_IDLEST_GFX specific bits */
/* CM_CLKSEL_GFX specific bits */
/* CM_CLKSTCTRL_GFX */
#define OMAP24XX_AUTOSTATE_GFX_SHIFT 0
#define OMAP24XX_AUTOSTATE_GFX_MASK (1 << 0)
/* CM_FCLKEN_WKUP specific bits */
/* CM_ICLKEN_WKUP specific bits */
#define OMAP2430_EN_ICR_SHIFT 6
#define OMAP2430_EN_ICR_MASK (1 << 6)
#define OMAP24XX_EN_OMAPCTRL_SHIFT 5
#define OMAP24XX_EN_OMAPCTRL_MASK (1 << 5)
#define OMAP24XX_EN_WDT1_SHIFT 4
#define OMAP24XX_EN_WDT1_MASK (1 << 4)
#define OMAP24XX_EN_32KSYNC_SHIFT 1
#define OMAP24XX_EN_32KSYNC_MASK (1 << 1)
/* CM_IDLEST_WKUP specific bits */
#define OMAP2430_ST_ICR_SHIFT 6
#define OMAP2430_ST_ICR_MASK (1 << 6)
#define OMAP24XX_ST_OMAPCTRL_SHIFT 5
#define OMAP24XX_ST_OMAPCTRL_MASK (1 << 5)
#define OMAP24XX_ST_WDT1_SHIFT 4
#define OMAP24XX_ST_WDT1_MASK (1 << 4)
#define OMAP24XX_ST_MPU_WDT_SHIFT 3
#define OMAP24XX_ST_MPU_WDT_MASK (1 << 3)
#define OMAP24XX_ST_32KSYNC_SHIFT 1
#define OMAP24XX_ST_32KSYNC_MASK (1 << 1)
/* CM_AUTOIDLE_WKUP */
#define OMAP24XX_AUTO_OMAPCTRL_MASK (1 << 5)
#define OMAP24XX_AUTO_WDT1_MASK (1 << 4)
#define OMAP24XX_AUTO_MPU_WDT_MASK (1 << 3)
#define OMAP24XX_AUTO_GPIOS_MASK (1 << 2)
#define OMAP24XX_AUTO_32KSYNC_MASK (1 << 1)
#define OMAP24XX_AUTO_GPT1_MASK (1 << 0)
/* CM_CLKSEL_WKUP */
#define OMAP24XX_CLKSEL_GPT1_SHIFT 0
#define OMAP24XX_CLKSEL_GPT1_MASK (0x3 << 0)
/* CM_CLKEN_PLL */
#define OMAP24XX_EN_54M_PLL_SHIFT 6
#define OMAP24XX_EN_54M_PLL_MASK (0x3 << 6)
#define OMAP24XX_EN_96M_PLL_SHIFT 2
#define OMAP24XX_EN_96M_PLL_MASK (0x3 << 2)
#define OMAP24XX_EN_DPLL_SHIFT 0
#define OMAP24XX_EN_DPLL_MASK (0x3 << 0)
/* CM_IDLEST_CKGEN */
#define OMAP24XX_ST_54M_APLL_SHIFT 9
#define OMAP24XX_ST_54M_APLL_MASK (1 << 9)
#define OMAP24XX_ST_96M_APLL_SHIFT 8
#define OMAP24XX_ST_96M_APLL_MASK (1 << 8)
#define OMAP24XX_ST_54M_CLK_MASK (1 << 6)
#define OMAP24XX_ST_12M_CLK_MASK (1 << 5)
#define OMAP24XX_ST_48M_CLK_MASK (1 << 4)
#define OMAP24XX_ST_96M_CLK_MASK (1 << 2)
#define OMAP24XX_ST_CORE_CLK_SHIFT 0
#define OMAP24XX_ST_CORE_CLK_MASK (0x3 << 0)
/* CM_AUTOIDLE_PLL */
#define OMAP24XX_AUTO_54M_SHIFT 6
#define OMAP24XX_AUTO_54M_MASK (0x3 << 6)
#define OMAP24XX_AUTO_96M_SHIFT 2
#define OMAP24XX_AUTO_96M_MASK (0x3 << 2)
#define OMAP24XX_AUTO_DPLL_SHIFT 0
#define OMAP24XX_AUTO_DPLL_MASK (0x3 << 0)
/* CM_CLKSEL1_PLL */
#define OMAP2430_MAXDPLLFASTLOCK_SHIFT 28
#define OMAP2430_MAXDPLLFASTLOCK_MASK (0x7 << 28)
#define OMAP24XX_APLLS_CLKIN_SHIFT 23
#define OMAP24XX_APLLS_CLKIN_MASK (0x7 << 23)
#define OMAP24XX_DPLL_MULT_SHIFT 12
#define OMAP24XX_DPLL_MULT_MASK (0x3ff << 12)
#define OMAP24XX_DPLL_DIV_SHIFT 8
#define OMAP24XX_DPLL_DIV_MASK (0xf << 8)
#define OMAP24XX_54M_SOURCE_SHIFT 5
#define OMAP24XX_54M_SOURCE_MASK (1 << 5)
#define OMAP24XX_54M_SOURCE_WIDTH 1
#define OMAP2430_96M_SOURCE_SHIFT 4
#define OMAP2430_96M_SOURCE_MASK (1 << 4)
#define OMAP2430_96M_SOURCE_WIDTH 1
#define OMAP24XX_48M_SOURCE_SHIFT 3
#define OMAP24XX_48M_SOURCE_MASK (1 << 3)
#define OMAP2430_ALTCLK_SOURCE_SHIFT 0
#define OMAP2430_ALTCLK_SOURCE_MASK (0x7 << 0)
/* CM_CLKSEL2_PLL */
#define OMAP24XX_CORE_CLK_SRC_SHIFT 0
#define OMAP24XX_CORE_CLK_SRC_MASK (0x3 << 0)
/* CM_FCLKEN_DSP */
#define OMAP2420_EN_IVA_COP_SHIFT 10
#define OMAP2420_EN_IVA_COP_MASK (1 << 10)
#define OMAP2420_EN_IVA_MPU_SHIFT 8
#define OMAP2420_EN_IVA_MPU_MASK (1 << 8)
#define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT 0
#define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_MASK (1 << 0)
/* CM_ICLKEN_DSP */
#define OMAP2420_EN_DSP_IPI_SHIFT 1
#define OMAP2420_EN_DSP_IPI_MASK (1 << 1)
/* CM_IDLEST_DSP */
#define OMAP2420_ST_IVA_MASK (1 << 8)
#define OMAP2420_ST_IPI_MASK (1 << 1)
#define OMAP24XX_ST_DSP_MASK (1 << 0)
/* CM_AUTOIDLE_DSP */
#define OMAP2420_AUTO_DSP_IPI_MASK (1 << 1)
/* CM_CLKSEL_DSP */
#define OMAP2420_SYNC_IVA_MASK (1 << 13)
#define OMAP2420_CLKSEL_IVA_SHIFT 8
#define OMAP2420_CLKSEL_IVA_MASK (0x1f << 8)
#define OMAP24XX_SYNC_DSP_MASK (1 << 7)
#define OMAP24XX_CLKSEL_DSP_IF_SHIFT 5
#define OMAP24XX_CLKSEL_DSP_IF_MASK (0x3 << 5)
#define OMAP24XX_CLKSEL_DSP_SHIFT 0
#define OMAP24XX_CLKSEL_DSP_MASK (0x1f << 0)
/* CM_CLKSTCTRL_DSP */
#define OMAP2420_AUTOSTATE_IVA_SHIFT 8
#define OMAP2420_AUTOSTATE_IVA_MASK (1 << 8)
#define OMAP24XX_AUTOSTATE_DSP_SHIFT 0
#define OMAP24XX_AUTOSTATE_DSP_MASK (1 << 0)
/* CM_FCLKEN_MDM */
/* 2430 only */
#define OMAP2430_EN_OSC_SHIFT 1
#define OMAP2430_EN_OSC_MASK (1 << 1)
/* CM_ICLKEN_MDM */
/* 2430 only */
#define OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT 0
#define OMAP2430_CM_ICLKEN_MDM_EN_MDM_MASK (1 << 0)
/* CM_IDLEST_MDM specific bits */
/* 2430 only */
/* CM_AUTOIDLE_MDM */
/* 2430 only */
#define OMAP2430_AUTO_OSC_MASK (1 << 1)
#define OMAP2430_AUTO_MDM_MASK (1 << 0)
/* CM_CLKSEL_MDM */
/* 2430 only */
#define OMAP2430_SYNC_MDM_MASK (1 << 4)
#define OMAP2430_CLKSEL_MDM_SHIFT 0
#define OMAP2430_CLKSEL_MDM_MASK (0xf << 0)
/* CM_CLKSTCTRL_MDM */
/* 2430 only */
#define OMAP2430_AUTOSTATE_MDM_SHIFT 0
#define OMAP2430_AUTOSTATE_MDM_MASK (1 << 0)
/* OMAP24XX CM_CLKSTCTRL_*.AUTOSTATE_* register bit values */
#define OMAP24XX_CLKSTCTRL_DISABLE_AUTO 0x0
#define OMAP24XX_CLKSTCTRL_ENABLE_AUTO 0x1
#endif

749
arch/arm/mach-omap2/cm-regbits-33xx.h
View File

@ -20,798 +20,49 @@
#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H
#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H
/*
* Used by CM_AUTOIDLE_DPLL_CORE, CM_AUTOIDLE_DPLL_DDR, CM_AUTOIDLE_DPLL_DISP,
* CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER
*/
#define AM33XX_AUTO_DPLL_MODE_SHIFT 0
#define AM33XX_AUTO_DPLL_MODE_WIDTH 3
#define AM33XX_AUTO_DPLL_MODE_MASK (0x7 << 0)
/* Used by CM_WKUP_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_ADC_FCLK_SHIFT 14
#define AM33XX_CLKACTIVITY_ADC_FCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_ADC_FCLK_MASK (1 << 16)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_CAN_CLK_SHIFT 11
#define AM33XX_CLKACTIVITY_CAN_CLK_WIDTH 1
#define AM33XX_CLKACTIVITY_CAN_CLK_MASK (1 << 11)
/* Used by CM_PER_CLK_24MHZ_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_SHIFT 4
#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_MASK (1 << 4)
/* Used by CM_PER_CPSW_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_SHIFT 4
#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_MASK (1 << 4)
/* Used by CM_PER_L4HS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_SHIFT 4
#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_MASK (1 << 4)
/* Used by CM_PER_L4HS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_SHIFT 5
#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_MASK (1 << 5)
/* Used by CM_PER_L4HS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_SHIFT 6
#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_MASK (1 << 6)
/* Used by CM_PER_L3_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_SHIFT 6
#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_MASK (1 << 6)
/* Used by CM_CEFUSE_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9
#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_WIDTH 1
#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9)
/* Used by CM_L3_AON_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_DBGSYSCLK_SHIFT 2
#define AM33XX_CLKACTIVITY_DBGSYSCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_DBGSYSCLK_MASK (1 << 2)
/* Used by CM_L3_AON_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_DEBUG_CLKA_SHIFT 4
#define AM33XX_CLKACTIVITY_DEBUG_CLKA_WIDTH 1
#define AM33XX_CLKACTIVITY_DEBUG_CLKA_MASK (1 << 4)
/* Used by CM_PER_L3_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_EMIF_GCLK_SHIFT 2
#define AM33XX_CLKACTIVITY_EMIF_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_EMIF_GCLK_MASK (1 << 2)
/* Used by CM_GFX_L3_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_GFX_FCLK_SHIFT 9
#define AM33XX_CLKACTIVITY_GFX_FCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_GFX_FCLK_MASK (1 << 9)
/* Used by CM_GFX_L3_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_SHIFT 8
#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_MASK (1 << 8)
/* Used by CM_WKUP_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_SHIFT 8
#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_MASK (1 << 8)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_SHIFT 19
#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_MASK (1 << 19)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_SHIFT 20
#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_MASK (1 << 20)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_SHIFT 21
#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_MASK (1 << 21)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_SHIFT 22
#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_MASK (1 << 22)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_SHIFT 26
#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_MASK (1 << 26)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_SHIFT 18
#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_MASK (1 << 18)
/* Used by CM_WKUP_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_I2C0_GFCLK_SHIFT 11
#define AM33XX_CLKACTIVITY_I2C0_GFCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_I2C0_GFCLK_MASK (1 << 11)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_I2C_FCLK_SHIFT 24
#define AM33XX_CLKACTIVITY_I2C_FCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_I2C_FCLK_MASK (1 << 24)
/* Used by CM_PER_PRUSS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_SHIFT 5
#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_MASK (1 << 5)
/* Used by CM_PER_PRUSS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_SHIFT 4
#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_MASK (1 << 4)
/* Used by CM_PER_PRUSS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_SHIFT 6
#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_MASK (1 << 6)
/* Used by CM_PER_L3S_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_L3S_GCLK_SHIFT 3
#define AM33XX_CLKACTIVITY_L3S_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_L3S_GCLK_MASK (1 << 3)
/* Used by CM_L3_AON_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_L3_AON_GCLK_SHIFT 3
#define AM33XX_CLKACTIVITY_L3_AON_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_L3_AON_GCLK_MASK (1 << 3)
/* Used by CM_PER_L3_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_L3_GCLK_SHIFT 4
#define AM33XX_CLKACTIVITY_L3_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_L3_GCLK_MASK (1 << 4)
/* Used by CM_PER_L4FW_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_L4FW_GCLK_SHIFT 8
#define AM33XX_CLKACTIVITY_L4FW_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_L4FW_GCLK_MASK (1 << 8)
/* Used by CM_PER_L4HS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_L4HS_GCLK_SHIFT 3
#define AM33XX_CLKACTIVITY_L4HS_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_L4HS_GCLK_MASK (1 << 3)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_L4LS_GCLK_SHIFT 8
#define AM33XX_CLKACTIVITY_L4LS_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_L4LS_GCLK_MASK (1 << 8)
/* Used by CM_GFX_L4LS_GFX_CLKSTCTRL__1 */
#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_SHIFT 8
#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_MASK (1 << 8)
/* Used by CM_CEFUSE_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8
#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_WIDTH 1
#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8)
/* Used by CM_RTC_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_SHIFT 8
#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_MASK (1 << 8)
/* Used by CM_L4_WKUP_AON_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_SHIFT 2
#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_MASK (1 << 2)
/* Used by CM_WKUP_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_SHIFT 2
#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_MASK (1 << 2)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_LCDC_GCLK_SHIFT 17
#define AM33XX_CLKACTIVITY_LCDC_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_LCDC_GCLK_MASK (1 << 17)
/* Used by CM_PER_LCDC_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_SHIFT 4
#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_MASK (1 << 4)
/* Used by CM_PER_LCDC_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_SHIFT 5
#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_MASK (1 << 5)
/* Used by CM_PER_L3_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_MCASP_GCLK_SHIFT 7
#define AM33XX_CLKACTIVITY_MCASP_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_MCASP_GCLK_MASK (1 << 7)
/* Used by CM_PER_L3_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_MMC_FCLK_SHIFT 3
#define AM33XX_CLKACTIVITY_MMC_FCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_MMC_FCLK_MASK (1 << 3)
/* Used by CM_MPU_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_MPU_CLK_SHIFT 2
#define AM33XX_CLKACTIVITY_MPU_CLK_WIDTH 1
#define AM33XX_CLKACTIVITY_MPU_CLK_MASK (1 << 2)
/* Used by CM_PER_OCPWP_L3_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_SHIFT 4
#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_MASK (1 << 4)
/* Used by CM_PER_OCPWP_L3_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_SHIFT 5
#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_MASK (1 << 5)
/* Used by CM_RTC_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_RTC_32KCLK_SHIFT 9
#define AM33XX_CLKACTIVITY_RTC_32KCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_RTC_32KCLK_MASK (1 << 9)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_SPI_GCLK_SHIFT 25
#define AM33XX_CLKACTIVITY_SPI_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_SPI_GCLK_MASK (1 << 25)
/* Used by CM_WKUP_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_SR_SYSCLK_SHIFT 3
#define AM33XX_CLKACTIVITY_SR_SYSCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_SR_SYSCLK_MASK (1 << 3)
/* Used by CM_WKUP_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_TIMER0_GCLK_SHIFT 10
#define AM33XX_CLKACTIVITY_TIMER0_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_TIMER0_GCLK_MASK (1 << 10)
/* Used by CM_WKUP_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_TIMER1_GCLK_SHIFT 13
#define AM33XX_CLKACTIVITY_TIMER1_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_TIMER1_GCLK_MASK (1 << 13)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_TIMER2_GCLK_SHIFT 14
#define AM33XX_CLKACTIVITY_TIMER2_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_TIMER2_GCLK_MASK (1 << 14)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_TIMER3_GCLK_SHIFT 15
#define AM33XX_CLKACTIVITY_TIMER3_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_TIMER3_GCLK_MASK (1 << 15)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_TIMER4_GCLK_SHIFT 16
#define AM33XX_CLKACTIVITY_TIMER4_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_TIMER4_GCLK_MASK (1 << 16)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_TIMER5_GCLK_SHIFT 27
#define AM33XX_CLKACTIVITY_TIMER5_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_TIMER5_GCLK_MASK (1 << 27)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_TIMER6_GCLK_SHIFT 28
#define AM33XX_CLKACTIVITY_TIMER6_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_TIMER6_GCLK_MASK (1 << 28)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_TIMER7_GCLK_SHIFT 13
#define AM33XX_CLKACTIVITY_TIMER7_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_TIMER7_GCLK_MASK (1 << 13)
/* Used by CM_WKUP_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_UART0_GFCLK_SHIFT 12
#define AM33XX_CLKACTIVITY_UART0_GFCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_UART0_GFCLK_MASK (1 << 12)
/* Used by CM_PER_L4LS_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_UART_GFCLK_SHIFT 10
#define AM33XX_CLKACTIVITY_UART_GFCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_UART_GFCLK_MASK (1 << 10)
/* Used by CM_WKUP_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_WDT0_GCLK_SHIFT 9
#define AM33XX_CLKACTIVITY_WDT0_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_WDT0_GCLK_MASK (1 << 9)
/* Used by CM_WKUP_CLKSTCTRL */
#define AM33XX_CLKACTIVITY_WDT1_GCLK_SHIFT 4
#define AM33XX_CLKACTIVITY_WDT1_GCLK_WIDTH 1
#define AM33XX_CLKACTIVITY_WDT1_GCLK_MASK (1 << 4)
/* Used by CLKSEL_GFX_FCLK */
#define AM33XX_CLKDIV_SEL_GFX_FCLK_SHIFT 0
#define AM33XX_CLKDIV_SEL_GFX_FCLK_WIDTH 1
#define AM33XX_CLKDIV_SEL_GFX_FCLK_MASK (1 << 0)
/* Used by CM_CLKOUT_CTRL */
#define AM33XX_CLKOUT2DIV_SHIFT 3
#define AM33XX_CLKOUT2DIV_WIDTH 3
#define AM33XX_CLKOUT2DIV_MASK (0x7 << 3)
/* Used by CM_CLKOUT_CTRL */
#define AM33XX_CLKOUT2EN_SHIFT 7
#define AM33XX_CLKOUT2EN_WIDTH 1
#define AM33XX_CLKOUT2EN_MASK (1 << 7)
/* Used by CM_CLKOUT_CTRL */
#define AM33XX_CLKOUT2SOURCE_SHIFT 0
#define AM33XX_CLKOUT2SOURCE_WIDTH 3
#define AM33XX_CLKOUT2SOURCE_MASK (0x7 << 0)
/*
* Used by CLKSEL_GPIO0_DBCLK, CLKSEL_LCDC_PIXEL_CLK, CLKSEL_TIMER2_CLK,
* CLKSEL_TIMER3_CLK, CLKSEL_TIMER4_CLK, CLKSEL_TIMER5_CLK, CLKSEL_TIMER6_CLK,
* CLKSEL_TIMER7_CLK
*/
#define AM33XX_CLKSEL_SHIFT 0
#define AM33XX_CLKSEL_WIDTH 1
#define AM33XX_CLKSEL_MASK (0x01 << 0)
/*
* Renamed from CLKSEL Used by CLKSEL_PRUSS_OCP_CLK, CLKSEL_WDT1_CLK,
* CM_CPTS_RFT_CLKSEL
*/
#define AM33XX_CLKSEL_0_0_SHIFT 0
#define AM33XX_CLKSEL_0_0_WIDTH 1
#define AM33XX_CLKSEL_0_0_MASK (1 << 0)
#define AM33XX_CLKSEL_0_1_SHIFT 0
#define AM33XX_CLKSEL_0_1_WIDTH 2
#define AM33XX_CLKSEL_0_1_MASK (3 << 0)
/* Renamed from CLKSEL Used by CLKSEL_TIMER1MS_CLK */
#define AM33XX_CLKSEL_0_2_SHIFT 0
#define AM33XX_CLKSEL_0_2_WIDTH 3
#define AM33XX_CLKSEL_0_2_MASK (7 << 0)
/* Used by CLKSEL_GFX_FCLK */
#define AM33XX_CLKSEL_GFX_FCLK_SHIFT 1
#define AM33XX_CLKSEL_GFX_FCLK_WIDTH 1
#define AM33XX_CLKSEL_GFX_FCLK_MASK (1 << 1)
/*
* Used by CM_MPU_CLKSTCTRL, CM_RTC_CLKSTCTRL, CM_PER_CLK_24MHZ_CLKSTCTRL,
* CM_PER_CPSW_CLKSTCTRL, CM_PER_PRUSS_CLKSTCTRL, CM_PER_L3S_CLKSTCTRL,
* CM_PER_L3_CLKSTCTRL, CM_PER_L4FW_CLKSTCTRL, CM_PER_L4HS_CLKSTCTRL,
* CM_PER_L4LS_CLKSTCTRL, CM_PER_LCDC_CLKSTCTRL, CM_PER_OCPWP_L3_CLKSTCTRL,
* CM_L3_AON_CLKSTCTRL, CM_L4_WKUP_AON_CLKSTCTRL, CM_WKUP_CLKSTCTRL,
* CM_GFX_L3_CLKSTCTRL, CM_GFX_L4LS_GFX_CLKSTCTRL__1, CM_CEFUSE_CLKSTCTRL
*/
#define AM33XX_CLKTRCTRL_SHIFT 0
#define AM33XX_CLKTRCTRL_WIDTH 2
#define AM33XX_CLKTRCTRL_MASK (0x3 << 0)
/*
* Used by CM_SSC_DELTAMSTEP_DPLL_CORE, CM_SSC_DELTAMSTEP_DPLL_DDR,
* CM_SSC_DELTAMSTEP_DPLL_DISP, CM_SSC_DELTAMSTEP_DPLL_MPU,
* CM_SSC_DELTAMSTEP_DPLL_PER
*/
#define AM33XX_DELTAMSTEP_SHIFT 0
#define AM33XX_DELTAMSTEP_WIDTH 20
#define AM33XX_DELTAMSTEP_MASK (0xfffff << 0)
/* Used by CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, CM_CLKSEL_DPLL_MPU */
#define AM33XX_DPLL_BYP_CLKSEL_SHIFT 23
#define AM33XX_DPLL_BYP_CLKSEL_WIDTH 1
#define AM33XX_DPLL_BYP_CLKSEL_MASK (1 << 23)
/* Used by CM_CLKDCOLDO_DPLL_PER */
#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8
#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_WIDTH 1
#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8)
/* Used by CM_CLKDCOLDO_DPLL_PER */
#define AM33XX_DPLL_CLKDCOLDO_PWDN_SHIFT 12
#define AM33XX_DPLL_CLKDCOLDO_PWDN_WIDTH 1
#define AM33XX_DPLL_CLKDCOLDO_PWDN_MASK (1 << 12)
/* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */
#define AM33XX_DPLL_CLKOUT_DIV_SHIFT 0
#define AM33XX_DPLL_CLKOUT_DIV_WIDTH 5
#define AM33XX_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
/* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_PER */
#define AM33XX_DPLL_CLKOUT_DIV_0_6_SHIFT 0
#define AM33XX_DPLL_CLKOUT_DIV_0_6_WIDTH 7
#define AM33XX_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0)
/* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */
#define AM33XX_DPLL_CLKOUT_DIVCHACK_SHIFT 5
#define AM33XX_DPLL_CLKOUT_DIVCHACK_WIDTH 1
#define AM33XX_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5)
/* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_PER */
#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_SHIFT 7
#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_WIDTH 1
#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_MASK (1 << 7)
/*
* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU,
* CM_DIV_M2_DPLL_PER
*/
#define AM33XX_DPLL_CLKOUT_GATE_CTRL_SHIFT 8
#define AM33XX_DPLL_CLKOUT_GATE_CTRL_WIDTH 1
#define AM33XX_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8)
/*
* Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP,
* CM_CLKSEL_DPLL_MPU
*/
#define AM33XX_DPLL_DIV_SHIFT 0
#define AM33XX_DPLL_DIV_WIDTH 7
#define AM33XX_DPLL_DIV_MASK (0x7f << 0)
#define AM33XX_DPLL_PER_DIV_MASK (0xff << 0)
/* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_PERIPH */
#define AM33XX_DPLL_DIV_0_7_SHIFT 0
#define AM33XX_DPLL_DIV_0_7_WIDTH 8
#define AM33XX_DPLL_DIV_0_7_MASK (0xff << 0)
/*
* Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
* CM_CLKMODE_DPLL_MPU
*/
#define AM33XX_DPLL_DRIFTGUARD_EN_SHIFT 8
#define AM33XX_DPLL_DRIFTGUARD_EN_WIDTH 1
#define AM33XX_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
/*
* Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
*/
#define AM33XX_DPLL_EN_SHIFT 0
#define AM33XX_DPLL_EN_WIDTH 3
#define AM33XX_DPLL_EN_MASK (0x7 << 0)
/*
* Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
* CM_CLKMODE_DPLL_MPU
*/
#define AM33XX_DPLL_LPMODE_EN_SHIFT 10
#define AM33XX_DPLL_LPMODE_EN_WIDTH 1
#define AM33XX_DPLL_LPMODE_EN_MASK (1 << 10)
/*
* Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP,
* CM_CLKSEL_DPLL_MPU
*/
#define AM33XX_DPLL_MULT_SHIFT 8
#define AM33XX_DPLL_MULT_WIDTH 11
#define AM33XX_DPLL_MULT_MASK (0x7ff << 8)
/* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_PERIPH */
#define AM33XX_DPLL_MULT_PERIPH_SHIFT 8
#define AM33XX_DPLL_MULT_PERIPH_WIDTH 12
#define AM33XX_DPLL_MULT_PERIPH_MASK (0xfff << 8)
/*
* Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
* CM_CLKMODE_DPLL_MPU
*/
#define AM33XX_DPLL_REGM4XEN_SHIFT 11
#define AM33XX_DPLL_REGM4XEN_WIDTH 1
#define AM33XX_DPLL_REGM4XEN_MASK (1 << 11)
/* Used by CM_CLKSEL_DPLL_PERIPH */
#define AM33XX_DPLL_SD_DIV_SHIFT 24
#define AM33XX_DPLL_SD_DIV_WIDTH 8
#define AM33XX_DPLL_SD_DIV_MASK (0xff << 24)
/*
* Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
*/
#define AM33XX_DPLL_SSC_ACK_SHIFT 13
#define AM33XX_DPLL_SSC_ACK_WIDTH 1
#define AM33XX_DPLL_SSC_ACK_MASK (1 << 13)
/*
* Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
*/
#define AM33XX_DPLL_SSC_DOWNSPREAD_SHIFT 14
#define AM33XX_DPLL_SSC_DOWNSPREAD_WIDTH 1
#define AM33XX_DPLL_SSC_DOWNSPREAD_MASK (1 << 14)
/*
* Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
* CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
*/
#define AM33XX_DPLL_SSC_EN_SHIFT 12
#define AM33XX_DPLL_SSC_EN_WIDTH 1
#define AM33XX_DPLL_SSC_EN_MASK (1 << 12)
/* Used by CM_DIV_M4_DPLL_CORE */
#define AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT 0
#define AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH 5
#define AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0)
/* Used by CM_DIV_M4_DPLL_CORE */
#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5
#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_WIDTH 1
#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5)
/* Used by CM_DIV_M4_DPLL_CORE */
#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8
#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_WIDTH 1
#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8)
/* Used by CM_DIV_M4_DPLL_CORE */
#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12
#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_WIDTH 1
#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12)
/* Used by CM_DIV_M5_DPLL_CORE */
#define AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT 0
#define AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH 5
#define AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0)
/* Used by CM_DIV_M5_DPLL_CORE */
#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5
#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_WIDTH 1
#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5)
/* Used by CM_DIV_M5_DPLL_CORE */
#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8
#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_WIDTH 1
#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8)
/* Used by CM_DIV_M5_DPLL_CORE */
#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12
#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_WIDTH 1
#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12)
/* Used by CM_DIV_M6_DPLL_CORE */
#define AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT 0
#define AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH 5
#define AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0)
/* Used by CM_DIV_M6_DPLL_CORE */
#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5
#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_WIDTH 1
#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5)
/* Used by CM_DIV_M6_DPLL_CORE */
#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8
#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_WIDTH 1
#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8)
/* Used by CM_DIV_M6_DPLL_CORE */
#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12
#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_WIDTH 1
#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12)
/*
* Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL,
* CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL,
* CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL,
* CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL,
* CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL,
* CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL,
* CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL,
* CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL,
* CM_PER_PRUSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL,
* CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL,
* CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL,
* CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL,
* CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL,
* CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL,
* CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
* CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL,
* CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL,
* CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL,
* CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL,
* CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL,
* CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL,
* CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
* CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL,
* CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL,
* CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL,
* CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL,
* CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL,
* CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL,
* CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL,
* CM_WKUP_WDT1_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL,
* CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL
*/
#define AM33XX_IDLEST_SHIFT 16
#define AM33XX_IDLEST_WIDTH 2
#define AM33XX_IDLEST_MASK (0x3 << 16)
/* Used by CM_MAC_CLKSEL */
#define AM33XX_MII_CLK_SEL_SHIFT 2
#define AM33XX_MII_CLK_SEL_WIDTH 1
#define AM33XX_MII_CLK_SEL_MASK (1 << 2)
/*
* Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR,
* CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU,
* CM_SSC_MODFREQDIV_DPLL_PER
*/
#define AM33XX_MODFREQDIV_EXPONENT_SHIFT 8
#define AM33XX_MODFREQDIV_EXPONENT_WIDTH 3
#define AM33XX_MODFREQDIV_EXPONENT_MASK (0x7 << 8)
/*
* Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR,
* CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU,
* CM_SSC_MODFREQDIV_DPLL_PER
*/
#define AM33XX_MODFREQDIV_MANTISSA_SHIFT 0
#define AM33XX_MODFREQDIV_MANTISSA_WIDTH 7
#define AM33XX_MODFREQDIV_MANTISSA_MASK (0x7f << 0)
/*
* Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL,
* CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL,
* CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL,
* CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL,
* CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL,
* CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL,
* CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL,
* CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL,
* CM_PER_PRUSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL,
* CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL,
* CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL,
* CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL,
* CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL,
* CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL,
* CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
* CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL,
* CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL,
* CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL,
* CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL,
* CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL,
* CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL,
* CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
* CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL,
* CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL,
* CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL,
* CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL,
* CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL,
* CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL,
* CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL,
* CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL,
* CM_GFX_GFX_CLKCTRL, CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL,
* CM_CEFUSE_CEFUSE_CLKCTRL
*/
#define AM33XX_MODULEMODE_SHIFT 0
#define AM33XX_MODULEMODE_WIDTH 2
#define AM33XX_MODULEMODE_MASK (0x3 << 0)
/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
#define AM33XX_OPTCLK_DEBUG_CLKA_SHIFT 30
#define AM33XX_OPTCLK_DEBUG_CLKA_WIDTH 1
#define AM33XX_OPTCLK_DEBUG_CLKA_MASK (1 << 30)
/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
#define AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT 19
#define AM33XX_OPTFCLKEN_DBGSYSCLK_WIDTH 1
#define AM33XX_OPTFCLKEN_DBGSYSCLK_MASK (1 << 19)
/* Used by CM_WKUP_GPIO0_CLKCTRL */
#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT 18
#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_WIDTH 1
#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_MASK (1 << 18)
/* Used by CM_PER_GPIO1_CLKCTRL */
#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT 18
#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_WIDTH 1
#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_MASK (1 << 18)
/* Used by CM_PER_GPIO2_CLKCTRL */
#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT 18
#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_WIDTH 1
#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_MASK (1 << 18)
/* Used by CM_PER_GPIO3_CLKCTRL */
#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT 18
#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_WIDTH 1
#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_MASK (1 << 18)
/* Used by CM_PER_GPIO4_CLKCTRL */
#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_SHIFT 18
#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_WIDTH 1
#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_MASK (1 << 18)
/* Used by CM_PER_GPIO5_CLKCTRL */
#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_SHIFT 18
#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_WIDTH 1
#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_MASK (1 << 18)
/* Used by CM_PER_GPIO6_CLKCTRL */
#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_SHIFT 18
#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_WIDTH 1
#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_MASK (1 << 18)
/*
* Used by CM_MPU_MPU_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL, CM_PER_PRUSS_CLKCTRL,
* CM_PER_IEEE5000_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MLB_CLKCTRL,
* CM_PER_MSTR_EXPS_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
* CM_PER_SPARE_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
* CM_PER_TPTC2_CLKCTRL, CM_PER_USB0_CLKCTRL, CM_WKUP_DEBUGSS_CLKCTRL,
* CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL
*/
#define AM33XX_STBYST_SHIFT 18
#define AM33XX_STBYST_WIDTH 1
#define AM33XX_STBYST_MASK (1 << 18)
/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
#define AM33XX_STM_PMD_CLKDIVSEL_SHIFT 27
#define AM33XX_STM_PMD_CLKDIVSEL_WIDTH 3
#define AM33XX_STM_PMD_CLKDIVSEL_MASK (0x7 << 27)
/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
#define AM33XX_STM_PMD_CLKSEL_SHIFT 22
#define AM33XX_STM_PMD_CLKSEL_WIDTH 2
#define AM33XX_STM_PMD_CLKSEL_MASK (0x3 << 22)
/*
* Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP,
* CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER
*/
#define AM33XX_ST_DPLL_CLK_SHIFT 0
#define AM33XX_ST_DPLL_CLK_WIDTH 1
#define AM33XX_ST_DPLL_CLK_MASK (1 << 0)
/* Used by CM_CLKDCOLDO_DPLL_PER */
#define AM33XX_ST_DPLL_CLKDCOLDO_SHIFT 8
#define AM33XX_ST_DPLL_CLKDCOLDO_WIDTH 1
#define AM33XX_ST_DPLL_CLKDCOLDO_MASK (1 << 8)
/*
* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU,
* CM_DIV_M2_DPLL_PER
*/
#define AM33XX_ST_DPLL_CLKOUT_SHIFT 9
#define AM33XX_ST_DPLL_CLKOUT_WIDTH 1
#define AM33XX_ST_DPLL_CLKOUT_MASK (1 << 9)
/* Used by CM_DIV_M4_DPLL_CORE */
#define AM33XX_ST_HSDIVIDER_CLKOUT1_SHIFT 9
#define AM33XX_ST_HSDIVIDER_CLKOUT1_WIDTH 1
#define AM33XX_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9)
/* Used by CM_DIV_M5_DPLL_CORE */
#define AM33XX_ST_HSDIVIDER_CLKOUT2_SHIFT 9
#define AM33XX_ST_HSDIVIDER_CLKOUT2_WIDTH 1
#define AM33XX_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9)
/* Used by CM_DIV_M6_DPLL_CORE */
#define AM33XX_ST_HSDIVIDER_CLKOUT3_SHIFT 9
#define AM33XX_ST_HSDIVIDER_CLKOUT3_WIDTH 1
#define AM33XX_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9)
/*
* Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP,
* CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER
*/
#define AM33XX_ST_MN_BYPASS_SHIFT 8
#define AM33XX_ST_MN_BYPASS_WIDTH 1
#define AM33XX_ST_MN_BYPASS_MASK (1 << 8)
/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
#define AM33XX_TRC_PMD_CLKDIVSEL_SHIFT 24
#define AM33XX_TRC_PMD_CLKDIVSEL_WIDTH 3
#define AM33XX_TRC_PMD_CLKDIVSEL_MASK (0x7 << 24)
/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
#define AM33XX_TRC_PMD_CLKSEL_SHIFT 20
#define AM33XX_TRC_PMD_CLKSEL_WIDTH 2
#define AM33XX_TRC_PMD_CLKSEL_MASK (0x3 << 20)
/* Used by CONTROL_SEC_CLK_CTRL */
#define AM33XX_TIMER0_CLKSEL_WIDTH 2
#define AM33XX_TIMER0_CLKSEL_MASK (0x3 << 4)
#endif

632
arch/arm/mach-omap2/cm-regbits-34xx.h
View File

@ -14,833 +14,201 @@
* published by the Free Software Foundation.
*/
/* Bits shared between registers */
/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
#define OMAP3430ES2_EN_MMC3_MASK (1 << 30)
#define OMAP3430ES2_EN_MMC3_SHIFT 30
#define OMAP3430_EN_MSPRO_MASK (1 << 23)
#define OMAP3430_EN_MSPRO_SHIFT 23
#define OMAP3430_EN_HDQ_MASK (1 << 22)
#define OMAP3430_EN_HDQ_SHIFT 22
#define OMAP3430ES1_EN_FSHOSTUSB_MASK (1 << 5)
#define OMAP3430ES1_EN_FSHOSTUSB_SHIFT 5
#define OMAP3430ES1_EN_D2D_MASK (1 << 3)
#define OMAP3430ES1_EN_D2D_SHIFT 3
#define OMAP3430_EN_SSI_MASK (1 << 0)
#define OMAP3430_EN_SSI_SHIFT 0
/* CM_FCLKEN3_CORE and CM_ICLKEN3_CORE shared bits */
#define OMAP3430ES2_EN_USBTLL_SHIFT 2
#define OMAP3430ES2_EN_USBTLL_MASK (1 << 2)
/* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */
#define OMAP3430_EN_WDT2_MASK (1 << 5)
#define OMAP3430_EN_WDT2_SHIFT 5
/* CM_ICLKEN_CAM, CM_FCLKEN_CAM shared bits */
#define OMAP3430_EN_CAM_MASK (1 << 0)
#define OMAP3430_EN_CAM_SHIFT 0
/* CM_FCLKEN_PER, CM_ICLKEN_PER shared bits */
#define OMAP3430_EN_WDT3_MASK (1 << 12)
#define OMAP3430_EN_WDT3_SHIFT 12
/* CM_CLKSEL2_EMU, CM_CLKSEL3_EMU shared bits */
#define OMAP3430_OVERRIDE_ENABLE_MASK (1 << 19)
/* Bits specific to each register */
/* CM_FCLKEN_IVA2 */
#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK (1 << 0)
#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT 0
/* CM_CLKEN_PLL_IVA2 */
#define OMAP3430_IVA2_DPLL_RAMPTIME_SHIFT 8
#define OMAP3430_IVA2_DPLL_RAMPTIME_MASK (0x3 << 8)
#define OMAP3430_IVA2_DPLL_FREQSEL_SHIFT 4
#define OMAP3430_IVA2_DPLL_FREQSEL_MASK (0xf << 4)
#define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT 3
#define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_MASK (1 << 3)
#define OMAP3430_EN_IVA2_DPLL_SHIFT 0
#define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0)
/* CM_IDLEST_IVA2 */
#define OMAP3430_ST_IVA2_SHIFT 0
#define OMAP3430_ST_IVA2_MASK (1 << 0)
/* CM_IDLEST_PLL_IVA2 */
#define OMAP3430_ST_IVA2_CLK_SHIFT 0
#define OMAP3430_ST_IVA2_CLK_MASK (1 << 0)
/* CM_AUTOIDLE_PLL_IVA2 */
#define OMAP3430_AUTO_IVA2_DPLL_SHIFT 0
#define OMAP3430_AUTO_IVA2_DPLL_MASK (0x7 << 0)
/* CM_CLKSEL1_PLL_IVA2 */
#define OMAP3430_IVA2_CLK_SRC_SHIFT 19
#define OMAP3430_IVA2_CLK_SRC_MASK (0x7 << 19)
#define OMAP3430_IVA2_CLK_SRC_WIDTH 3
#define OMAP3430_IVA2_DPLL_MULT_SHIFT 8
#define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8)
#define OMAP3430_IVA2_DPLL_DIV_SHIFT 0
#define OMAP3430_IVA2_DPLL_DIV_MASK (0x7f << 0)
/* CM_CLKSEL2_PLL_IVA2 */
#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT 0
#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_WIDTH 5
/* CM_CLKSTCTRL_IVA2 */
#define OMAP3430_CLKTRCTRL_IVA2_SHIFT 0
#define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0)
/* CM_CLKSTST_IVA2 */
#define OMAP3430_CLKACTIVITY_IVA2_SHIFT 0
#define OMAP3430_CLKACTIVITY_IVA2_MASK (1 << 0)
/* CM_REVISION specific bits */
/* CM_SYSCONFIG specific bits */
/* CM_CLKEN_PLL_MPU */
#define OMAP3430_MPU_DPLL_RAMPTIME_SHIFT 8
#define OMAP3430_MPU_DPLL_RAMPTIME_MASK (0x3 << 8)
#define OMAP3430_MPU_DPLL_FREQSEL_SHIFT 4
#define OMAP3430_MPU_DPLL_FREQSEL_MASK (0xf << 4)
#define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT 3
#define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_MASK (1 << 3)
#define OMAP3430_EN_MPU_DPLL_SHIFT 0
#define OMAP3430_EN_MPU_DPLL_MASK (0x7 << 0)
/* CM_IDLEST_MPU */
#define OMAP3430_ST_MPU_MASK (1 << 0)
/* CM_IDLEST_PLL_MPU */
#define OMAP3430_ST_MPU_CLK_SHIFT 0
#define OMAP3430_ST_MPU_CLK_MASK (1 << 0)
#define OMAP3430_ST_MPU_CLK_WIDTH 1
/* CM_AUTOIDLE_PLL_MPU */
#define OMAP3430_AUTO_MPU_DPLL_SHIFT 0
#define OMAP3430_AUTO_MPU_DPLL_MASK (0x7 << 0)
/* CM_CLKSEL1_PLL_MPU */
#define OMAP3430_MPU_CLK_SRC_SHIFT 19
#define OMAP3430_MPU_CLK_SRC_MASK (0x7 << 19)
#define OMAP3430_MPU_CLK_SRC_WIDTH 3
#define OMAP3430_MPU_DPLL_MULT_SHIFT 8
#define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8)
#define OMAP3430_MPU_DPLL_DIV_SHIFT 0
#define OMAP3430_MPU_DPLL_DIV_MASK (0x7f << 0)
/* CM_CLKSEL2_PLL_MPU */
#define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT 0
#define OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
#define OMAP3430_MPU_DPLL_CLKOUT_DIV_WIDTH 5
/* CM_CLKSTCTRL_MPU */
#define OMAP3430_CLKTRCTRL_MPU_SHIFT 0
#define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0)
/* CM_CLKSTST_MPU */
#define OMAP3430_CLKACTIVITY_MPU_SHIFT 0
#define OMAP3430_CLKACTIVITY_MPU_MASK (1 << 0)
/* CM_FCLKEN1_CORE specific bits */
#define OMAP3430_EN_MODEM_MASK (1 << 31)
#define OMAP3430_EN_MODEM_SHIFT 31
/* CM_ICLKEN1_CORE specific bits */
#define OMAP3430_EN_ICR_MASK (1 << 29)
#define OMAP3430_EN_ICR_SHIFT 29
#define OMAP3430_EN_AES2_MASK (1 << 28)
#define OMAP3430_EN_AES2_SHIFT 28
#define OMAP3430_EN_SHA12_MASK (1 << 27)
#define OMAP3430_EN_SHA12_SHIFT 27
#define OMAP3430_EN_DES2_MASK (1 << 26)
#define OMAP3430_EN_DES2_SHIFT 26
#define OMAP3430ES1_EN_FAC_MASK (1 << 8)
#define OMAP3430ES1_EN_FAC_SHIFT 8
#define OMAP3430_EN_MAILBOXES_MASK (1 << 7)
#define OMAP3430_EN_MAILBOXES_SHIFT 7
#define OMAP3430_EN_OMAPCTRL_MASK (1 << 6)
#define OMAP3430_EN_OMAPCTRL_SHIFT 6
#define OMAP3430_EN_SAD2D_MASK (1 << 3)
#define OMAP3430_EN_SAD2D_SHIFT 3
#define OMAP3430_EN_SDRC_MASK (1 << 1)
#define OMAP3430_EN_SDRC_SHIFT 1
/* AM35XX specific CM_ICLKEN1_CORE bits */
#define AM35XX_EN_IPSS_MASK (1 << 4)
#define AM35XX_EN_IPSS_SHIFT 4
/* CM_ICLKEN2_CORE */
#define OMAP3430_EN_PKA_MASK (1 << 4)
#define OMAP3430_EN_PKA_SHIFT 4
#define OMAP3430_EN_AES1_MASK (1 << 3)
#define OMAP3430_EN_AES1_SHIFT 3
#define OMAP3430_EN_RNG_MASK (1 << 2)
#define OMAP3430_EN_RNG_SHIFT 2
#define OMAP3430_EN_SHA11_MASK (1 << 1)
#define OMAP3430_EN_SHA11_SHIFT 1
#define OMAP3430_EN_DES1_MASK (1 << 0)
#define OMAP3430_EN_DES1_SHIFT 0
/* CM_ICLKEN3_CORE */
#define OMAP3430_EN_MAD2D_SHIFT 3
#define OMAP3430_EN_MAD2D_MASK (1 << 3)
/* CM_FCLKEN3_CORE specific bits */
#define OMAP3430ES2_EN_TS_SHIFT 1
#define OMAP3430ES2_EN_TS_MASK (1 << 1)
#define OMAP3430ES2_EN_CPEFUSE_SHIFT 0
#define OMAP3430ES2_EN_CPEFUSE_MASK (1 << 0)
/* CM_IDLEST1_CORE specific bits */
#define OMAP3430ES2_ST_MMC3_SHIFT 30
#define OMAP3430ES2_ST_MMC3_MASK (1 << 30)
#define OMAP3430_ST_ICR_SHIFT 29
#define OMAP3430_ST_ICR_MASK (1 << 29)
#define OMAP3430_ST_AES2_SHIFT 28
#define OMAP3430_ST_AES2_MASK (1 << 28)
#define OMAP3430_ST_SHA12_SHIFT 27
#define OMAP3430_ST_SHA12_MASK (1 << 27)
#define OMAP3430_ST_DES2_SHIFT 26
#define OMAP3430_ST_DES2_MASK (1 << 26)
#define OMAP3430_ST_MSPRO_SHIFT 23
#define OMAP3430_ST_MSPRO_MASK (1 << 23)
#define AM35XX_ST_UART4_SHIFT 23
#define AM35XX_ST_UART4_MASK (1 << 23)
#define OMAP3430_ST_HDQ_SHIFT 22
#define OMAP3430_ST_HDQ_MASK (1 << 22)
#define OMAP3430ES1_ST_FAC_SHIFT 8
#define OMAP3430ES1_ST_FAC_MASK (1 << 8)
#define OMAP3430ES2_ST_SSI_IDLE_SHIFT 8
#define OMAP3430ES2_ST_SSI_IDLE_MASK (1 << 8)
#define OMAP3430_ST_MAILBOXES_SHIFT 7
#define OMAP3430_ST_MAILBOXES_MASK (1 << 7)
#define OMAP3430_ST_OMAPCTRL_SHIFT 6
#define OMAP3430_ST_OMAPCTRL_MASK (1 << 6)
#define OMAP3430_ST_SAD2D_SHIFT 3
#define OMAP3430_ST_SAD2D_MASK (1 << 3)
#define OMAP3430_ST_SDMA_SHIFT 2
#define OMAP3430_ST_SDMA_MASK (1 << 2)
#define OMAP3430_ST_SDRC_SHIFT 1
#define OMAP3430_ST_SDRC_MASK (1 << 1)
#define OMAP3430_ST_SSI_STDBY_SHIFT 0
#define OMAP3430_ST_SSI_STDBY_MASK (1 << 0)
/* AM35xx specific CM_IDLEST1_CORE bits */
#define AM35XX_ST_IPSS_SHIFT 5
#define AM35XX_ST_IPSS_MASK (1 << 5)
/* CM_IDLEST2_CORE */
#define OMAP3430_ST_PKA_SHIFT 4
#define OMAP3430_ST_PKA_MASK (1 << 4)
#define OMAP3430_ST_AES1_SHIFT 3
#define OMAP3430_ST_AES1_MASK (1 << 3)
#define OMAP3430_ST_RNG_SHIFT 2
#define OMAP3430_ST_RNG_MASK (1 << 2)
#define OMAP3430_ST_SHA11_SHIFT 1
#define OMAP3430_ST_SHA11_MASK (1 << 1)
#define OMAP3430_ST_DES1_SHIFT 0
#define OMAP3430_ST_DES1_MASK (1 << 0)
/* CM_IDLEST3_CORE */
#define OMAP3430ES2_ST_USBTLL_SHIFT 2
#define OMAP3430ES2_ST_USBTLL_MASK (1 << 2)
#define OMAP3430ES2_ST_CPEFUSE_SHIFT 0
#define OMAP3430ES2_ST_CPEFUSE_MASK (1 << 0)
/* CM_AUTOIDLE1_CORE */
#define OMAP3430_AUTO_MODEM_MASK (1 << 31)
#define OMAP3430_AUTO_MODEM_SHIFT 31
#define OMAP3430ES2_AUTO_MMC3_MASK (1 << 30)
#define OMAP3430ES2_AUTO_MMC3_SHIFT 30
#define OMAP3430ES2_AUTO_ICR_MASK (1 << 29)
#define OMAP3430ES2_AUTO_ICR_SHIFT 29
#define OMAP3430_AUTO_AES2_MASK (1 << 28)
#define OMAP3430_AUTO_AES2_SHIFT 28
#define OMAP3430_AUTO_SHA12_MASK (1 << 27)
#define OMAP3430_AUTO_SHA12_SHIFT 27
#define OMAP3430_AUTO_DES2_MASK (1 << 26)
#define OMAP3430_AUTO_DES2_SHIFT 26
#define OMAP3430_AUTO_MMC2_MASK (1 << 25)
#define OMAP3430_AUTO_MMC2_SHIFT 25
#define OMAP3430_AUTO_MMC1_MASK (1 << 24)
#define OMAP3430_AUTO_MMC1_SHIFT 24
#define OMAP3430_AUTO_MSPRO_MASK (1 << 23)
#define OMAP3430_AUTO_MSPRO_SHIFT 23
#define OMAP3430_AUTO_HDQ_MASK (1 << 22)
#define OMAP3430_AUTO_HDQ_SHIFT 22
#define OMAP3430_AUTO_MCSPI4_MASK (1 << 21)
#define OMAP3430_AUTO_MCSPI4_SHIFT 21
#define OMAP3430_AUTO_MCSPI3_MASK (1 << 20)
#define OMAP3430_AUTO_MCSPI3_SHIFT 20
#define OMAP3430_AUTO_MCSPI2_MASK (1 << 19)
#define OMAP3430_AUTO_MCSPI2_SHIFT 19
#define OMAP3430_AUTO_MCSPI1_MASK (1 << 18)
#define OMAP3430_AUTO_MCSPI1_SHIFT 18
#define OMAP3430_AUTO_I2C3_MASK (1 << 17)
#define OMAP3430_AUTO_I2C3_SHIFT 17
#define OMAP3430_AUTO_I2C2_MASK (1 << 16)
#define OMAP3430_AUTO_I2C2_SHIFT 16
#define OMAP3430_AUTO_I2C1_MASK (1 << 15)
#define OMAP3430_AUTO_I2C1_SHIFT 15
#define OMAP3430_AUTO_UART2_MASK (1 << 14)
#define OMAP3430_AUTO_UART2_SHIFT 14
#define OMAP3430_AUTO_UART1_MASK (1 << 13)
#define OMAP3430_AUTO_UART1_SHIFT 13
#define OMAP3430_AUTO_GPT11_MASK (1 << 12)
#define OMAP3430_AUTO_GPT11_SHIFT 12
#define OMAP3430_AUTO_GPT10_MASK (1 << 11)
#define OMAP3430_AUTO_GPT10_SHIFT 11
#define OMAP3430_AUTO_MCBSP5_MASK (1 << 10)
#define OMAP3430_AUTO_MCBSP5_SHIFT 10
#define OMAP3430_AUTO_MCBSP1_MASK (1 << 9)
#define OMAP3430_AUTO_MCBSP1_SHIFT 9
#define OMAP3430ES1_AUTO_FAC_MASK (1 << 8)
#define OMAP3430ES1_AUTO_FAC_SHIFT 8
#define OMAP3430_AUTO_MAILBOXES_MASK (1 << 7)
#define OMAP3430_AUTO_MAILBOXES_SHIFT 7
#define OMAP3430_AUTO_OMAPCTRL_MASK (1 << 6)
#define OMAP3430_AUTO_OMAPCTRL_SHIFT 6
#define OMAP3430ES1_AUTO_FSHOSTUSB_MASK (1 << 5)
#define OMAP3430ES1_AUTO_FSHOSTUSB_SHIFT 5
#define OMAP3430_AUTO_HSOTGUSB_MASK (1 << 4)
#define OMAP3430_AUTO_HSOTGUSB_SHIFT 4
#define OMAP3430ES1_AUTO_D2D_MASK (1 << 3)
#define OMAP3430ES1_AUTO_D2D_SHIFT 3
#define OMAP3430_AUTO_SAD2D_MASK (1 << 3)
#define OMAP3430_AUTO_SAD2D_SHIFT 3
#define OMAP3430_AUTO_SSI_MASK (1 << 0)
#define OMAP3430_AUTO_SSI_SHIFT 0
/* CM_AUTOIDLE2_CORE */
#define OMAP3430_AUTO_PKA_MASK (1 << 4)
#define OMAP3430_AUTO_PKA_SHIFT 4
#define OMAP3430_AUTO_AES1_MASK (1 << 3)
#define OMAP3430_AUTO_AES1_SHIFT 3
#define OMAP3430_AUTO_RNG_MASK (1 << 2)
#define OMAP3430_AUTO_RNG_SHIFT 2
#define OMAP3430_AUTO_SHA11_MASK (1 << 1)
#define OMAP3430_AUTO_SHA11_SHIFT 1
#define OMAP3430_AUTO_DES1_MASK (1 << 0)
#define OMAP3430_AUTO_DES1_SHIFT 0
/* CM_AUTOIDLE3_CORE */
#define OMAP3430ES2_AUTO_USBHOST (1 << 0)
#define OMAP3430ES2_AUTO_USBHOST_SHIFT 0
#define OMAP3430ES2_AUTO_USBTLL (1 << 2)
#define OMAP3430ES2_AUTO_USBTLL_SHIFT 2
#define OMAP3430ES2_AUTO_USBTLL_MASK (1 << 2)
#define OMAP3430_AUTO_MAD2D_SHIFT 3
#define OMAP3430_AUTO_MAD2D_MASK (1 << 3)
/* CM_CLKSEL_CORE */
#define OMAP3430_CLKSEL_SSI_SHIFT 8
#define OMAP3430_CLKSEL_SSI_MASK (0xf << 8)
#define OMAP3430_CLKSEL_GPT11_MASK (1 << 7)
#define OMAP3430_CLKSEL_GPT11_SHIFT 7
#define OMAP3430_CLKSEL_GPT10_MASK (1 << 6)
#define OMAP3430_CLKSEL_GPT10_SHIFT 6
#define OMAP3430ES1_CLKSEL_FSHOSTUSB_SHIFT 4
#define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK (0x3 << 4)
#define OMAP3430_CLKSEL_L4_SHIFT 2
#define OMAP3430_CLKSEL_L4_MASK (0x3 << 2)
#define OMAP3430_CLKSEL_L4_WIDTH 2
#define OMAP3430_CLKSEL_L3_SHIFT 0
#define OMAP3430_CLKSEL_L3_MASK (0x3 << 0)
#define OMAP3430_CLKSEL_L3_WIDTH 2
#define OMAP3630_CLKSEL_96M_SHIFT 12
#define OMAP3630_CLKSEL_96M_MASK (0x3 << 12)
#define OMAP3630_CLKSEL_96M_WIDTH 2
/* CM_CLKSTCTRL_CORE */
#define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT 4
#define OMAP3430ES1_CLKTRCTRL_D2D_MASK (0x3 << 4)
#define OMAP3430_CLKTRCTRL_L4_SHIFT 2
#define OMAP3430_CLKTRCTRL_L4_MASK (0x3 << 2)
#define OMAP3430_CLKTRCTRL_L3_SHIFT 0
#define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0)
/* CM_CLKSTST_CORE */
#define OMAP3430ES1_CLKACTIVITY_D2D_SHIFT 2
#define OMAP3430ES1_CLKACTIVITY_D2D_MASK (1 << 2)
#define OMAP3430_CLKACTIVITY_L4_SHIFT 1
#define OMAP3430_CLKACTIVITY_L4_MASK (1 << 1)
#define OMAP3430_CLKACTIVITY_L3_SHIFT 0
#define OMAP3430_CLKACTIVITY_L3_MASK (1 << 0)
/* CM_FCLKEN_GFX */
#define OMAP3430ES1_EN_3D_MASK (1 << 2)
#define OMAP3430ES1_EN_3D_SHIFT 2
#define OMAP3430ES1_EN_2D_MASK (1 << 1)
#define OMAP3430ES1_EN_2D_SHIFT 1
/* CM_ICLKEN_GFX specific bits */
/* CM_IDLEST_GFX specific bits */
/* CM_CLKSEL_GFX specific bits */
/* CM_SLEEPDEP_GFX specific bits */
/* CM_CLKSTCTRL_GFX */
#define OMAP3430ES1_CLKTRCTRL_GFX_SHIFT 0
#define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0)
/* CM_CLKSTST_GFX */
#define OMAP3430ES1_CLKACTIVITY_GFX_SHIFT 0
#define OMAP3430ES1_CLKACTIVITY_GFX_MASK (1 << 0)
/* CM_FCLKEN_SGX */
#define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT 1
#define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_MASK (1 << 1)
/* CM_IDLEST_SGX */
#define OMAP3430ES2_ST_SGX_SHIFT 1
#define OMAP3430ES2_ST_SGX_MASK (1 << 1)
/* CM_ICLKEN_SGX */
#define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT 0
#define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_MASK (1 << 0)
/* CM_CLKSEL_SGX */
#define OMAP3430ES2_CLKSEL_SGX_SHIFT 0
#define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0)
/* CM_CLKSTCTRL_SGX */
#define OMAP3430ES2_CLKTRCTRL_SGX_SHIFT 0
#define OMAP3430ES2_CLKTRCTRL_SGX_MASK (0x3 << 0)
/* CM_CLKSTST_SGX */
#define OMAP3430ES2_CLKACTIVITY_SGX_SHIFT 0
#define OMAP3430ES2_CLKACTIVITY_SGX_MASK (1 << 0)
/* CM_FCLKEN_WKUP specific bits */
#define OMAP3430ES2_EN_USIMOCP_SHIFT 9
#define OMAP3430ES2_EN_USIMOCP_MASK (1 << 9)
/* CM_ICLKEN_WKUP specific bits */
#define OMAP3430_EN_WDT1_MASK (1 << 4)
#define OMAP3430_EN_WDT1_SHIFT 4
#define OMAP3430_EN_32KSYNC_MASK (1 << 2)
#define OMAP3430_EN_32KSYNC_SHIFT 2
/* CM_IDLEST_WKUP specific bits */
#define OMAP3430ES2_ST_USIMOCP_SHIFT 9
#define OMAP3430ES2_ST_USIMOCP_MASK (1 << 9)
#define OMAP3430_ST_WDT2_SHIFT 5
#define OMAP3430_ST_WDT2_MASK (1 << 5)
#define OMAP3430_ST_WDT1_SHIFT 4
#define OMAP3430_ST_WDT1_MASK (1 << 4)
#define OMAP3430_ST_32KSYNC_SHIFT 2
#define OMAP3430_ST_32KSYNC_MASK (1 << 2)
/* CM_AUTOIDLE_WKUP */
#define OMAP3430ES2_AUTO_USIMOCP_MASK (1 << 9)
#define OMAP3430ES2_AUTO_USIMOCP_SHIFT 9
#define OMAP3430_AUTO_WDT2_MASK (1 << 5)
#define OMAP3430_AUTO_WDT2_SHIFT 5
#define OMAP3430_AUTO_WDT1_MASK (1 << 4)
#define OMAP3430_AUTO_WDT1_SHIFT 4
#define OMAP3430_AUTO_GPIO1_MASK (1 << 3)
#define OMAP3430_AUTO_GPIO1_SHIFT 3
#define OMAP3430_AUTO_32KSYNC_MASK (1 << 2)
#define OMAP3430_AUTO_32KSYNC_SHIFT 2
#define OMAP3430_AUTO_GPT12_MASK (1 << 1)
#define OMAP3430_AUTO_GPT12_SHIFT 1
#define OMAP3430_AUTO_GPT1_MASK (1 << 0)
#define OMAP3430_AUTO_GPT1_SHIFT 0
/* CM_CLKSEL_WKUP */
#define OMAP3430ES2_CLKSEL_USIMOCP_MASK (0xf << 3)
#define OMAP3430_CLKSEL_RM_SHIFT 1
#define OMAP3430_CLKSEL_RM_MASK (0x3 << 1)
#define OMAP3430_CLKSEL_RM_WIDTH 2
#define OMAP3430_CLKSEL_GPT1_SHIFT 0
#define OMAP3430_CLKSEL_GPT1_MASK (1 << 0)
/* CM_CLKEN_PLL */
#define OMAP3430_PWRDN_EMU_PERIPH_SHIFT 31
#define OMAP3430_PWRDN_CAM_SHIFT 30
#define OMAP3430_PWRDN_DSS1_SHIFT 29
#define OMAP3430_PWRDN_TV_SHIFT 28
#define OMAP3430_PWRDN_96M_SHIFT 27
#define OMAP3430_PERIPH_DPLL_RAMPTIME_SHIFT 24
#define OMAP3430_PERIPH_DPLL_RAMPTIME_MASK (0x3 << 24)
#define OMAP3430_PERIPH_DPLL_FREQSEL_SHIFT 20
#define OMAP3430_PERIPH_DPLL_FREQSEL_MASK (0xf << 20)
#define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT 19
#define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_MASK (1 << 19)
#define OMAP3430_EN_PERIPH_DPLL_SHIFT 16
#define OMAP3430_EN_PERIPH_DPLL_MASK (0x7 << 16)
#define OMAP3430_PWRDN_EMU_CORE_SHIFT 12
#define OMAP3430_CORE_DPLL_RAMPTIME_SHIFT 8
#define OMAP3430_CORE_DPLL_RAMPTIME_MASK (0x3 << 8)
#define OMAP3430_CORE_DPLL_FREQSEL_SHIFT 4
#define OMAP3430_CORE_DPLL_FREQSEL_MASK (0xf << 4)
#define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT 3
#define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_MASK (1 << 3)
#define OMAP3430_EN_CORE_DPLL_SHIFT 0
#define OMAP3430_EN_CORE_DPLL_MASK (0x7 << 0)
/* CM_CLKEN2_PLL */
#define OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT 10
#define OMAP3430ES2_PERIPH2_DPLL_RAMPTIME_MASK (0x3 << 8)
#define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT 4
#define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK (0xf << 4)
#define OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT 3
#define OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT 0
#define OMAP3430ES2_EN_PERIPH2_DPLL_MASK (0x7 << 0)
/* CM_IDLEST_CKGEN */
#define OMAP3430_ST_54M_CLK_MASK (1 << 5)
#define OMAP3430_ST_12M_CLK_MASK (1 << 4)
#define OMAP3430_ST_48M_CLK_MASK (1 << 3)
#define OMAP3430_ST_96M_CLK_MASK (1 << 2)
#define OMAP3430_ST_PERIPH_CLK_SHIFT 1
#define OMAP3430_ST_PERIPH_CLK_MASK (1 << 1)
#define OMAP3430_ST_CORE_CLK_SHIFT 0
#define OMAP3430_ST_CORE_CLK_MASK (1 << 0)
/* CM_IDLEST2_CKGEN */
#define OMAP3430ES2_ST_USIM_CLK_SHIFT 2
#define OMAP3430ES2_ST_USIM_CLK_MASK (1 << 2)
#define OMAP3430ES2_ST_120M_CLK_SHIFT 1
#define OMAP3430ES2_ST_120M_CLK_MASK (1 << 1)
#define OMAP3430ES2_ST_PERIPH2_CLK_SHIFT 0
#define OMAP3430ES2_ST_PERIPH2_CLK_MASK (1 << 0)
/* CM_AUTOIDLE_PLL */
#define OMAP3430_AUTO_PERIPH_DPLL_SHIFT 3
#define OMAP3430_AUTO_PERIPH_DPLL_MASK (0x7 << 3)
#define OMAP3430_AUTO_CORE_DPLL_SHIFT 0
#define OMAP3430_AUTO_CORE_DPLL_MASK (0x7 << 0)
/* CM_AUTOIDLE2_PLL */
#define OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT 0
#define OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK (0x7 << 0)
/* CM_CLKSEL1_PLL */
/* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */
#define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT 27
#define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK (0x1f << 27)
#define OMAP3430_CORE_DPLL_CLKOUT_DIV_WIDTH 5
#define OMAP3430_CORE_DPLL_MULT_SHIFT 16
#define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16)
#define OMAP3430_CORE_DPLL_DIV_SHIFT 8
#define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8)
#define OMAP3430_SOURCE_96M_SHIFT 6
#define OMAP3430_SOURCE_96M_MASK (1 << 6)
#define OMAP3430_SOURCE_96M_WIDTH 1
#define OMAP3430_SOURCE_54M_SHIFT 5
#define OMAP3430_SOURCE_54M_MASK (1 << 5)
#define OMAP3430_SOURCE_54M_WIDTH 1
#define OMAP3430_SOURCE_48M_SHIFT 3
#define OMAP3430_SOURCE_48M_MASK (1 << 3)
/* CM_CLKSEL2_PLL */
#define OMAP3430_PERIPH_DPLL_MULT_SHIFT 8
#define OMAP3430_PERIPH_DPLL_MULT_MASK (0x7ff << 8)
#define OMAP3630_PERIPH_DPLL_MULT_MASK (0xfff << 8)
#define OMAP3430_PERIPH_DPLL_DIV_SHIFT 0
#define OMAP3430_PERIPH_DPLL_DIV_MASK (0x7f << 0)
#define OMAP3630_PERIPH_DPLL_DCO_SEL_SHIFT 21
#define OMAP3630_PERIPH_DPLL_DCO_SEL_MASK (0x7 << 21)
#define OMAP3630_PERIPH_DPLL_SD_DIV_SHIFT 24
#define OMAP3630_PERIPH_DPLL_SD_DIV_MASK (0xff << 24)
/* CM_CLKSEL3_PLL */
#define OMAP3430_DIV_96M_SHIFT 0
#define OMAP3430_DIV_96M_MASK (0x1f << 0)
#define OMAP3430_DIV_96M_WIDTH 5
#define OMAP3630_DIV_96M_MASK (0x3f << 0)
#define OMAP3630_DIV_96M_WIDTH 6
/* CM_CLKSEL4_PLL */
#define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT 8
#define OMAP3430ES2_PERIPH2_DPLL_MULT_MASK (0x7ff << 8)
#define OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT 0
#define OMAP3430ES2_PERIPH2_DPLL_DIV_MASK (0x7f << 0)
/* CM_CLKSEL5_PLL */
#define OMAP3430ES2_DIV_120M_SHIFT 0
#define OMAP3430ES2_DIV_120M_MASK (0x1f << 0)
#define OMAP3430ES2_DIV_120M_WIDTH 5
/* CM_CLKOUT_CTRL */
#define OMAP3430_CLKOUT2_EN_SHIFT 7
#define OMAP3430_CLKOUT2_EN_MASK (1 << 7)
#define OMAP3430_CLKOUT2_DIV_SHIFT 3
#define OMAP3430_CLKOUT2_DIV_MASK (0x7 << 3)
#define OMAP3430_CLKOUT2_DIV_WIDTH 3
#define OMAP3430_CLKOUT2SOURCE_SHIFT 0
#define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0)
/* CM_FCLKEN_DSS */
#define OMAP3430_EN_TV_MASK (1 << 2)
#define OMAP3430_EN_TV_SHIFT 2
#define OMAP3430_EN_DSS2_MASK (1 << 1)
#define OMAP3430_EN_DSS2_SHIFT 1
#define OMAP3430_EN_DSS1_MASK (1 << 0)
#define OMAP3430_EN_DSS1_SHIFT 0
/* CM_ICLKEN_DSS */
#define OMAP3430_CM_ICLKEN_DSS_EN_DSS_MASK (1 << 0)
#define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0
/* CM_IDLEST_DSS */
#define OMAP3430ES2_ST_DSS_IDLE_SHIFT 1
#define OMAP3430ES2_ST_DSS_IDLE_MASK (1 << 1)
#define OMAP3430ES2_ST_DSS_STDBY_SHIFT 0
#define OMAP3430ES2_ST_DSS_STDBY_MASK (1 << 0)
#define OMAP3430ES1_ST_DSS_SHIFT 0
#define OMAP3430ES1_ST_DSS_MASK (1 << 0)
/* CM_AUTOIDLE_DSS */
#define OMAP3430_AUTO_DSS_MASK (1 << 0)
#define OMAP3430_AUTO_DSS_SHIFT 0
/* CM_CLKSEL_DSS */
#define OMAP3430_CLKSEL_TV_SHIFT 8
#define OMAP3430_CLKSEL_TV_MASK (0x1f << 8)
#define OMAP3430_CLKSEL_TV_WIDTH 5
#define OMAP3630_CLKSEL_TV_MASK (0x3f << 8)
#define OMAP3630_CLKSEL_TV_WIDTH 6
#define OMAP3430_CLKSEL_DSS1_SHIFT 0
#define OMAP3430_CLKSEL_DSS1_MASK (0x1f << 0)
#define OMAP3430_CLKSEL_DSS1_WIDTH 5
#define OMAP3630_CLKSEL_DSS1_MASK (0x3f << 0)
#define OMAP3630_CLKSEL_DSS1_WIDTH 6
/* CM_SLEEPDEP_DSS specific bits */
/* CM_CLKSTCTRL_DSS */
#define OMAP3430_CLKTRCTRL_DSS_SHIFT 0
#define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0)
/* CM_CLKSTST_DSS */
#define OMAP3430_CLKACTIVITY_DSS_SHIFT 0
#define OMAP3430_CLKACTIVITY_DSS_MASK (1 << 0)
/* CM_FCLKEN_CAM specific bits */
#define OMAP3430_EN_CSI2_MASK (1 << 1)
#define OMAP3430_EN_CSI2_SHIFT 1
/* CM_ICLKEN_CAM specific bits */
/* CM_IDLEST_CAM */
#define OMAP3430_ST_CAM_MASK (1 << 0)
/* CM_AUTOIDLE_CAM */
#define OMAP3430_AUTO_CAM_MASK (1 << 0)
#define OMAP3430_AUTO_CAM_SHIFT 0
/* CM_CLKSEL_CAM */
#define OMAP3430_CLKSEL_CAM_SHIFT 0
#define OMAP3430_CLKSEL_CAM_MASK (0x1f << 0)
#define OMAP3430_CLKSEL_CAM_WIDTH 5
#define OMAP3630_CLKSEL_CAM_MASK (0x3f << 0)
#define OMAP3630_CLKSEL_CAM_WIDTH 6
/* CM_SLEEPDEP_CAM specific bits */
/* CM_CLKSTCTRL_CAM */
#define OMAP3430_CLKTRCTRL_CAM_SHIFT 0
#define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0)
/* CM_CLKSTST_CAM */
#define OMAP3430_CLKACTIVITY_CAM_SHIFT 0
#define OMAP3430_CLKACTIVITY_CAM_MASK (1 << 0)
/* CM_FCLKEN_PER specific bits */
/* CM_ICLKEN_PER specific bits */
/* CM_IDLEST_PER */
#define OMAP3430_ST_WDT3_SHIFT 12
#define OMAP3430_ST_WDT3_MASK (1 << 12)
#define OMAP3430_ST_MCBSP4_SHIFT 2
#define OMAP3430_ST_MCBSP4_MASK (1 << 2)
#define OMAP3430_ST_MCBSP3_SHIFT 1
#define OMAP3430_ST_MCBSP3_MASK (1 << 1)
#define OMAP3430_ST_MCBSP2_SHIFT 0
#define OMAP3430_ST_MCBSP2_MASK (1 << 0)
/* CM_AUTOIDLE_PER */
#define OMAP3630_AUTO_UART4_MASK (1 << 18)
#define OMAP3630_AUTO_UART4_SHIFT 18
#define OMAP3430_AUTO_GPIO6_MASK (1 << 17)
#define OMAP3430_AUTO_GPIO6_SHIFT 17
#define OMAP3430_AUTO_GPIO5_MASK (1 << 16)
#define OMAP3430_AUTO_GPIO5_SHIFT 16
#define OMAP3430_AUTO_GPIO4_MASK (1 << 15)
#define OMAP3430_AUTO_GPIO4_SHIFT 15
#define OMAP3430_AUTO_GPIO3_MASK (1 << 14)
#define OMAP3430_AUTO_GPIO3_SHIFT 14
#define OMAP3430_AUTO_GPIO2_MASK (1 << 13)
#define OMAP3430_AUTO_GPIO2_SHIFT 13
#define OMAP3430_AUTO_WDT3_MASK (1 << 12)
#define OMAP3430_AUTO_WDT3_SHIFT 12
#define OMAP3430_AUTO_UART3_MASK (1 << 11)
#define OMAP3430_AUTO_UART3_SHIFT 11
#define OMAP3430_AUTO_GPT9_MASK (1 << 10)
#define OMAP3430_AUTO_GPT9_SHIFT 10
#define OMAP3430_AUTO_GPT8_MASK (1 << 9)
#define OMAP3430_AUTO_GPT8_SHIFT 9
#define OMAP3430_AUTO_GPT7_MASK (1 << 8)
#define OMAP3430_AUTO_GPT7_SHIFT 8
#define OMAP3430_AUTO_GPT6_MASK (1 << 7)
#define OMAP3430_AUTO_GPT6_SHIFT 7
#define OMAP3430_AUTO_GPT5_MASK (1 << 6)
#define OMAP3430_AUTO_GPT5_SHIFT 6
#define OMAP3430_AUTO_GPT4_MASK (1 << 5)
#define OMAP3430_AUTO_GPT4_SHIFT 5
#define OMAP3430_AUTO_GPT3_MASK (1 << 4)
#define OMAP3430_AUTO_GPT3_SHIFT 4
#define OMAP3430_AUTO_GPT2_MASK (1 << 3)
#define OMAP3430_AUTO_GPT2_SHIFT 3
#define OMAP3430_AUTO_MCBSP4_MASK (1 << 2)
#define OMAP3430_AUTO_MCBSP4_SHIFT 2
#define OMAP3430_AUTO_MCBSP3_MASK (1 << 1)
#define OMAP3430_AUTO_MCBSP3_SHIFT 1
#define OMAP3430_AUTO_MCBSP2_MASK (1 << 0)
#define OMAP3430_AUTO_MCBSP2_SHIFT 0
/* CM_CLKSEL_PER */
#define OMAP3430_CLKSEL_GPT9_MASK (1 << 7)
#define OMAP3430_CLKSEL_GPT9_SHIFT 7
#define OMAP3430_CLKSEL_GPT8_MASK (1 << 6)
#define OMAP3430_CLKSEL_GPT8_SHIFT 6
#define OMAP3430_CLKSEL_GPT7_MASK (1 << 5)
#define OMAP3430_CLKSEL_GPT7_SHIFT 5
#define OMAP3430_CLKSEL_GPT6_MASK (1 << 4)
#define OMAP3430_CLKSEL_GPT6_SHIFT 4
#define OMAP3430_CLKSEL_GPT5_MASK (1 << 3)
#define OMAP3430_CLKSEL_GPT5_SHIFT 3
#define OMAP3430_CLKSEL_GPT4_MASK (1 << 2)
#define OMAP3430_CLKSEL_GPT4_SHIFT 2
#define OMAP3430_CLKSEL_GPT3_MASK (1 << 1)
#define OMAP3430_CLKSEL_GPT3_SHIFT 1
#define OMAP3430_CLKSEL_GPT2_MASK (1 << 0)
#define OMAP3430_CLKSEL_GPT2_SHIFT 0
/* CM_SLEEPDEP_PER specific bits */
#define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2_MASK (1 << 2)
/* CM_CLKSTCTRL_PER */
#define OMAP3430_CLKTRCTRL_PER_SHIFT 0
#define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0)
/* CM_CLKSTST_PER */
#define OMAP3430_CLKACTIVITY_PER_SHIFT 0
#define OMAP3430_CLKACTIVITY_PER_MASK (1 << 0)
/* CM_CLKSEL1_EMU */
#define OMAP3430_DIV_DPLL4_SHIFT 24
#define OMAP3430_DIV_DPLL4_MASK (0x1f << 24)
#define OMAP3430_DIV_DPLL4_WIDTH 5
#define OMAP3630_DIV_DPLL4_MASK (0x3f << 24)
#define OMAP3630_DIV_DPLL4_WIDTH 6
#define OMAP3430_DIV_DPLL3_SHIFT 16
#define OMAP3430_DIV_DPLL3_MASK (0x1f << 16)
#define OMAP3430_DIV_DPLL3_WIDTH 5
#define OMAP3430_CLKSEL_TRACECLK_SHIFT 11
#define OMAP3430_CLKSEL_TRACECLK_MASK (0x7 << 11)
#define OMAP3430_CLKSEL_TRACECLK_WIDTH 3
#define OMAP3430_CLKSEL_PCLK_SHIFT 8
#define OMAP3430_CLKSEL_PCLK_MASK (0x7 << 8)
#define OMAP3430_CLKSEL_PCLK_WIDTH 3
#define OMAP3430_CLKSEL_PCLKX2_SHIFT 6
#define OMAP3430_CLKSEL_PCLKX2_MASK (0x3 << 6)
#define OMAP3430_CLKSEL_PCLKX2_WIDTH 2
#define OMAP3430_CLKSEL_ATCLK_SHIFT 4
#define OMAP3430_CLKSEL_ATCLK_MASK (0x3 << 4)
#define OMAP3430_CLKSEL_ATCLK_WIDTH 2
#define OMAP3430_TRACE_MUX_CTRL_SHIFT 2
#define OMAP3430_TRACE_MUX_CTRL_MASK (0x3 << 2)
#define OMAP3430_TRACE_MUX_CTRL_WIDTH 2
#define OMAP3430_MUX_CTRL_SHIFT 0
#define OMAP3430_MUX_CTRL_MASK (0x3 << 0)
#define OMAP3430_MUX_CTRL_WIDTH 2
/* CM_CLKSTCTRL_EMU */
#define OMAP3430_CLKTRCTRL_EMU_SHIFT 0
#define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0)
/* CM_CLKSTST_EMU */
#define OMAP3430_CLKACTIVITY_EMU_SHIFT 0
#define OMAP3430_CLKACTIVITY_EMU_MASK (1 << 0)
/* CM_CLKSEL2_EMU specific bits */
#define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT 8
#define OMAP3430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8)
#define OMAP3430_CORE_DPLL_EMU_DIV_SHIFT 0
#define OMAP3430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0)
/* CM_CLKSEL3_EMU specific bits */
#define OMAP3430_PERIPH_DPLL_EMU_MULT_SHIFT 8
#define OMAP3430_PERIPH_DPLL_EMU_MULT_MASK (0x7ff << 8)
#define OMAP3430_PERIPH_DPLL_EMU_DIV_SHIFT 0
#define OMAP3430_PERIPH_DPLL_EMU_DIV_MASK (0x7f << 0)
/* CM_POLCTRL */
#define OMAP3430_CLKOUT2_POL_MASK (1 << 0)
/* CM_IDLEST_NEON */
#define OMAP3430_ST_NEON_MASK (1 << 0)
/* CM_CLKSTCTRL_NEON */
#define OMAP3430_CLKTRCTRL_NEON_SHIFT 0
#define OMAP3430_CLKTRCTRL_NEON_MASK (0x3 << 0)
/* CM_FCLKEN_USBHOST */
#define OMAP3430ES2_EN_USBHOST2_SHIFT 1
#define OMAP3430ES2_EN_USBHOST2_MASK (1 << 1)
#define OMAP3430ES2_EN_USBHOST1_SHIFT 0
#define OMAP3430ES2_EN_USBHOST1_MASK (1 << 0)
/* CM_ICLKEN_USBHOST */
#define OMAP3430ES2_EN_USBHOST_SHIFT 0
#define OMAP3430ES2_EN_USBHOST_MASK (1 << 0)
/* CM_IDLEST_USBHOST */
#define OMAP3430ES2_ST_USBHOST_IDLE_SHIFT 1
#define OMAP3430ES2_ST_USBHOST_IDLE_MASK (1 << 1)
#define OMAP3430ES2_ST_USBHOST_STDBY_SHIFT 0
#define OMAP3430ES2_ST_USBHOST_STDBY_MASK (1 << 0)
/* CM_AUTOIDLE_USBHOST */
#define OMAP3430ES2_AUTO_USBHOST_SHIFT 0
#define OMAP3430ES2_AUTO_USBHOST_MASK (1 << 0)
/* CM_SLEEPDEP_USBHOST */
#define OMAP3430ES2_EN_MPU_SHIFT 1
#define OMAP3430ES2_EN_MPU_MASK (1 << 1)
#define OMAP3430ES2_EN_IVA2_SHIFT 2
#define OMAP3430ES2_EN_IVA2_MASK (1 << 2)
/* CM_CLKSTCTRL_USBHOST */
#define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT 0
#define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0)
/* CM_CLKSTST_USBHOST */
#define OMAP3430ES2_CLKACTIVITY_USBHOST_SHIFT 0
#define OMAP3430ES2_CLKACTIVITY_USBHOST_MASK (1 << 0)
/*
*
*/
/* OMAP3XXX CM_CLKSTCTRL_*.CLKTRCTRL_* register bit values */
#define OMAP34XX_CLKSTCTRL_DISABLE_AUTO 0x0
#define OMAP34XX_CLKSTCTRL_FORCE_SLEEP 0x1
#define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP 0x2
#define OMAP34XX_CLKSTCTRL_ENABLE_AUTO 0x3
#endif

1558
arch/arm/mach-omap2/cm-regbits-44xx.h
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1633
arch/arm/mach-omap2/cm-regbits-54xx.h
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File diff suppressed because it is too large Load Diff

1
arch/arm/mach-omap2/omap_hwmod_54xx_data.c
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@ -32,7 +32,6 @@
#include "cm1_54xx.h"
#include "cm2_54xx.h"
#include "prm54xx.h"
#include "prm-regbits-54xx.h"
#include "i2c.h"
#include "mmc.h"
#include "wd_timer.h"

1
arch/arm/mach-omap2/powerdomains54xx_data.c
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@ -25,7 +25,6 @@
#include "prcm-common.h"
#include "prcm44xx.h"
#include "prm-regbits-54xx.h"
#include "prm54xx.h"
#include "prcm_mpu54xx.h"

247
arch/arm/mach-omap2/prm-regbits-24xx.h
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@ -16,274 +16,27 @@
#include "prm2xxx.h"
/* Bits shared between registers */
/* PRCM_IRQSTATUS_MPU, PM_IRQSTATUS_DSP, PRCM_IRQSTATUS_IVA shared bits */
#define OMAP24XX_VOLTTRANS_ST_MASK (1 << 2)
#define OMAP24XX_WKUP2_ST_MASK (1 << 1)
#define OMAP24XX_WKUP1_ST_MASK (1 << 0)
/* PRCM_IRQENABLE_MPU, PM_IRQENABLE_DSP, PRCM_IRQENABLE_IVA shared bits */
#define OMAP24XX_VOLTTRANS_EN_MASK (1 << 2)
#define OMAP24XX_WKUP2_EN_MASK (1 << 1)
#define OMAP24XX_WKUP1_EN_MASK (1 << 0)
/* PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_DSP, PM_WKDEP_MDM shared bits */
#define OMAP24XX_EN_MPU_SHIFT 1
#define OMAP24XX_EN_MPU_MASK (1 << 1)
#define OMAP24XX_EN_CORE_SHIFT 0
#define OMAP24XX_EN_CORE_MASK (1 << 0)
/*
* PM_PWSTCTRL_MPU, PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM
* shared bits
*/
#define OMAP24XX_MEMONSTATE_SHIFT 10
#define OMAP24XX_MEMONSTATE_MASK (0x3 << 10)
#define OMAP24XX_MEMRETSTATE_MASK (1 << 3)
/* PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM shared bits */
#define OMAP24XX_FORCESTATE_MASK (1 << 18)
/*
* PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP,
* PM_PWSTST_MDM shared bits
*/
#define OMAP24XX_CLKACTIVITY_MASK (1 << 19)
/* PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_DSP shared bits */
#define OMAP24XX_LASTSTATEENTERED_SHIFT 4
#define OMAP24XX_LASTSTATEENTERED_MASK (0x3 << 4)
/* PM_PWSTST_MPU and PM_PWSTST_DSP shared bits */
#define OMAP2430_MEMSTATEST_SHIFT 10
#define OMAP2430_MEMSTATEST_MASK (0x3 << 10)
/* PM_PWSTST_GFX, PM_PWSTST_DSP, PM_PWSTST_MDM shared bits */
#define OMAP24XX_POWERSTATEST_SHIFT 0
#define OMAP24XX_POWERSTATEST_MASK (0x3 << 0)
/* Bits specific to each register */
/* PRCM_REVISION */
#define OMAP24XX_REV_SHIFT 0
#define OMAP24XX_REV_MASK (0xff << 0)
/* PRCM_SYSCONFIG */
#define OMAP24XX_AUTOIDLE_MASK (1 << 0)
/* PRCM_IRQSTATUS_MPU specific bits */
#define OMAP2430_DPLL_RECAL_ST_MASK (1 << 6)
#define OMAP24XX_TRANSITION_ST_MASK (1 << 5)
#define OMAP24XX_EVGENOFF_ST_MASK (1 << 4)
#define OMAP24XX_EVGENON_ST_MASK (1 << 3)
/* PRCM_IRQENABLE_MPU specific bits */
#define OMAP2430_DPLL_RECAL_EN_MASK (1 << 6)
#define OMAP24XX_TRANSITION_EN_MASK (1 << 5)
#define OMAP24XX_EVGENOFF_EN_MASK (1 << 4)
#define OMAP24XX_EVGENON_EN_MASK (1 << 3)
/* PRCM_VOLTCTRL */
#define OMAP24XX_AUTO_EXTVOLT_MASK (1 << 15)
#define OMAP24XX_FORCE_EXTVOLT_MASK (1 << 14)
#define OMAP24XX_SETOFF_LEVEL_SHIFT 12
#define OMAP24XX_SETOFF_LEVEL_MASK (0x3 << 12)
#define OMAP24XX_MEMRETCTRL_MASK (1 << 8)
#define OMAP24XX_SETRET_LEVEL_SHIFT 6
#define OMAP24XX_SETRET_LEVEL_MASK (0x3 << 6)
#define OMAP24XX_VOLT_LEVEL_SHIFT 0
#define OMAP24XX_VOLT_LEVEL_MASK (0x3 << 0)
/* PRCM_VOLTST */
#define OMAP24XX_ST_VOLTLEVEL_SHIFT 0
#define OMAP24XX_ST_VOLTLEVEL_MASK (0x3 << 0)
/* PRCM_CLKSRC_CTRL specific bits */
/* PRCM_CLKOUT_CTRL */
#define OMAP2420_CLKOUT2_EN_SHIFT 15
#define OMAP2420_CLKOUT2_EN_MASK (1 << 15)
#define OMAP2420_CLKOUT2_DIV_SHIFT 11
#define OMAP2420_CLKOUT2_DIV_MASK (0x7 << 11)
#define OMAP2420_CLKOUT2_DIV_WIDTH 3
#define OMAP2420_CLKOUT2_SOURCE_SHIFT 8
#define OMAP2420_CLKOUT2_SOURCE_MASK (0x3 << 8)
#define OMAP24XX_CLKOUT_EN_SHIFT 7
#define OMAP24XX_CLKOUT_EN_MASK (1 << 7)
#define OMAP24XX_CLKOUT_DIV_SHIFT 3
#define OMAP24XX_CLKOUT_DIV_MASK (0x7 << 3)
#define OMAP24XX_CLKOUT_DIV_WIDTH 3
#define OMAP24XX_CLKOUT_SOURCE_SHIFT 0
#define OMAP24XX_CLKOUT_SOURCE_MASK (0x3 << 0)
/* PRCM_CLKEMUL_CTRL */
#define OMAP24XX_EMULATION_EN_SHIFT 0
#define OMAP24XX_EMULATION_EN_MASK (1 << 0)
/* PRCM_CLKCFG_CTRL */
#define OMAP24XX_VALID_CONFIG_MASK (1 << 0)
/* PRCM_CLKCFG_STATUS */
#define OMAP24XX_CONFIG_STATUS_MASK (1 << 0)
/* PRCM_VOLTSETUP specific bits */
/* PRCM_CLKSSETUP specific bits */
/* PRCM_POLCTRL */
#define OMAP2420_CLKOUT2_POL_MASK (1 << 10)
#define OMAP24XX_CLKOUT_POL_MASK (1 << 9)
#define OMAP24XX_CLKREQ_POL_MASK (1 << 8)
#define OMAP2430_USE_POWEROK_MASK (1 << 2)
#define OMAP2430_POWEROK_POL_MASK (1 << 1)
#define OMAP24XX_EXTVOL_POL_MASK (1 << 0)
/* RM_RSTST_MPU specific bits */
/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" instead */
/* PM_WKDEP_MPU specific bits */
#define OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT 5
#define OMAP2430_PM_WKDEP_MPU_EN_MDM_MASK (1 << 5)
#define OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT 2
#define OMAP24XX_PM_WKDEP_MPU_EN_DSP_MASK (1 << 2)
/* PM_EVGENCTRL_MPU specific bits */
/* PM_EVEGENONTIM_MPU specific bits */
/* PM_EVEGENOFFTIM_MPU specific bits */
/* PM_PWSTCTRL_MPU specific bits */
#define OMAP2430_FORCESTATE_MASK (1 << 18)
/* PM_PWSTST_MPU specific bits */
/* INTRANSITION, CLKACTIVITY, POWERSTATE, MEMSTATEST are 2430 only */
/* PM_WKEN1_CORE specific bits */
/* PM_WKEN2_CORE specific bits */
/* PM_WKST1_CORE specific bits*/
/* PM_WKST2_CORE specific bits */
/* PM_WKDEP_CORE specific bits*/
#define OMAP2430_PM_WKDEP_CORE_EN_MDM_MASK (1 << 5)
#define OMAP24XX_PM_WKDEP_CORE_EN_GFX_MASK (1 << 3)
#define OMAP24XX_PM_WKDEP_CORE_EN_DSP_MASK (1 << 2)
/* PM_PWSTCTRL_CORE specific bits */
#define OMAP24XX_MEMORYCHANGE_MASK (1 << 20)
#define OMAP24XX_MEM3ONSTATE_SHIFT 14
#define OMAP24XX_MEM3ONSTATE_MASK (0x3 << 14)
#define OMAP24XX_MEM2ONSTATE_SHIFT 12
#define OMAP24XX_MEM2ONSTATE_MASK (0x3 << 12)
#define OMAP24XX_MEM1ONSTATE_SHIFT 10
#define OMAP24XX_MEM1ONSTATE_MASK (0x3 << 10)
#define OMAP24XX_MEM3RETSTATE_MASK (1 << 5)
#define OMAP24XX_MEM2RETSTATE_MASK (1 << 4)
#define OMAP24XX_MEM1RETSTATE_MASK (1 << 3)
/* PM_PWSTST_CORE specific bits */
#define OMAP24XX_MEM3STATEST_SHIFT 14
#define OMAP24XX_MEM3STATEST_MASK (0x3 << 14)
#define OMAP24XX_MEM2STATEST_SHIFT 12
#define OMAP24XX_MEM2STATEST_MASK (0x3 << 12)
#define OMAP24XX_MEM1STATEST_SHIFT 10
#define OMAP24XX_MEM1STATEST_MASK (0x3 << 10)
/* RM_RSTCTRL_GFX */
#define OMAP24XX_GFX_RST_MASK (1 << 0)
/* RM_RSTST_GFX specific bits */
#define OMAP24XX_GFX_SW_RST_MASK (1 << 4)
/* PM_PWSTCTRL_GFX specific bits */
/* PM_WKDEP_GFX specific bits */
/* 2430 often calls EN_WAKEUP "EN_WKUP" */
/* RM_RSTCTRL_WKUP specific bits */
/* RM_RSTTIME_WKUP specific bits */
/* RM_RSTST_WKUP specific bits */
/* 2430 calls EXTWMPU_RST "EXTWARM_RST" and GLOBALWMPU_RST "GLOBALWARM_RST" */
#define OMAP24XX_EXTWMPU_RST_SHIFT 6
#define OMAP24XX_EXTWMPU_RST_MASK (1 << 6)
#define OMAP24XX_SECU_WD_RST_SHIFT 5
#define OMAP24XX_SECU_WD_RST_MASK (1 << 5)
#define OMAP24XX_MPU_WD_RST_SHIFT 4
#define OMAP24XX_MPU_WD_RST_MASK (1 << 4)
#define OMAP24XX_SECU_VIOL_RST_SHIFT 3
#define OMAP24XX_SECU_VIOL_RST_MASK (1 << 3)
/* PM_WKEN_WKUP specific bits */
/* PM_WKST_WKUP specific bits */
/* RM_RSTCTRL_DSP */
#define OMAP2420_RST_IVA_MASK (1 << 8)
#define OMAP24XX_RST2_DSP_MASK (1 << 1)
#define OMAP24XX_RST1_DSP_MASK (1 << 0)
/* RM_RSTST_DSP specific bits */
/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" */
#define OMAP2420_IVA_SW_RST_MASK (1 << 8)
#define OMAP24XX_DSP_SW_RST2_MASK (1 << 5)
#define OMAP24XX_DSP_SW_RST1_MASK (1 << 4)
/* PM_WKDEP_DSP specific bits */
/* PM_PWSTCTRL_DSP specific bits */
/* 2430 only: MEMONSTATE, MEMRETSTATE */
#define OMAP2420_MEMIONSTATE_SHIFT 12
#define OMAP2420_MEMIONSTATE_MASK (0x3 << 12)
#define OMAP2420_MEMIRETSTATE_MASK (1 << 4)
/* PM_PWSTST_DSP specific bits */
/* MEMSTATEST is 2430 only */
#define OMAP2420_MEMISTATEST_SHIFT 12
#define OMAP2420_MEMISTATEST_MASK (0x3 << 12)
/* PRCM_IRQSTATUS_DSP specific bits */
/* PRCM_IRQENABLE_DSP specific bits */
/* RM_RSTCTRL_MDM */
/* 2430 only */
#define OMAP2430_PWRON1_MDM_MASK (1 << 1)
#define OMAP2430_RST1_MDM_MASK (1 << 0)
/* RM_RSTST_MDM specific bits */
/* 2430 only */
#define OMAP2430_MDM_SECU_VIOL_MASK (1 << 6)
#define OMAP2430_MDM_SW_PWRON1_MASK (1 << 5)
#define OMAP2430_MDM_SW_RST1_MASK (1 << 4)
/* PM_WKEN_MDM */
/* 2430 only */
#define OMAP2430_PM_WKEN_MDM_EN_MDM_MASK (1 << 0)
/* PM_WKST_MDM specific bits */
/* 2430 only */
/* PM_WKDEP_MDM specific bits */
/* 2430 only */
/* PM_PWSTCTRL_MDM specific bits */
/* 2430 only */
#define OMAP2430_KILLDOMAINWKUP_MASK (1 << 19)
/* PM_PWSTST_MDM specific bits */
/* 2430 only */
/* PRCM_IRQSTATUS_IVA */
/* 2420 only */
/* PRCM_IRQENABLE_IVA */
/* 2420 only */
#endif

307
arch/arm/mach-omap2/prm-regbits-33xx.h
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@ -18,340 +18,35 @@
#include "prm.h"
/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
#define AM33XX_ABBOFF_ACT_EXPORT_SHIFT 1
#define AM33XX_ABBOFF_ACT_EXPORT_MASK (1 << 1)
/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
#define AM33XX_ABBOFF_SLEEP_EXPORT_SHIFT 2
#define AM33XX_ABBOFF_SLEEP_EXPORT_MASK (1 << 2)
/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
#define AM33XX_AIPOFF_SHIFT 8
#define AM33XX_AIPOFF_MASK (1 << 8)
/* Used by PM_WKUP_PWRSTST */
#define AM33XX_DEBUGSS_MEM_STATEST_SHIFT 17
#define AM33XX_DEBUGSS_MEM_STATEST_MASK (0x3 << 17)
/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
#define AM33XX_DISABLE_RTA_EXPORT_SHIFT 0
#define AM33XX_DISABLE_RTA_EXPORT_MASK (1 << 0)
/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
#define AM33XX_DPLL_CORE_RECAL_EN_SHIFT 12
#define AM33XX_DPLL_CORE_RECAL_EN_MASK (1 << 12)
/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
#define AM33XX_DPLL_CORE_RECAL_ST_SHIFT 12
#define AM33XX_DPLL_CORE_RECAL_ST_MASK (1 << 12)
/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
#define AM33XX_DPLL_DDR_RECAL_EN_SHIFT 14
#define AM33XX_DPLL_DDR_RECAL_EN_MASK (1 << 14)
/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
#define AM33XX_DPLL_DDR_RECAL_ST_SHIFT 14
#define AM33XX_DPLL_DDR_RECAL_ST_MASK (1 << 14)
/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
#define AM33XX_DPLL_DISP_RECAL_EN_SHIFT 15
#define AM33XX_DPLL_DISP_RECAL_EN_MASK (1 << 15)
/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
#define AM33XX_DPLL_DISP_RECAL_ST_SHIFT 13
#define AM33XX_DPLL_DISP_RECAL_ST_MASK (1 << 13)
/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
#define AM33XX_DPLL_MPU_RECAL_EN_SHIFT 11
#define AM33XX_DPLL_MPU_RECAL_EN_MASK (1 << 11)
/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
#define AM33XX_DPLL_MPU_RECAL_ST_SHIFT 11
#define AM33XX_DPLL_MPU_RECAL_ST_MASK (1 << 11)
/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
#define AM33XX_DPLL_PER_RECAL_EN_SHIFT 13
#define AM33XX_DPLL_PER_RECAL_EN_MASK (1 << 13)
/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
#define AM33XX_DPLL_PER_RECAL_ST_SHIFT 15
#define AM33XX_DPLL_PER_RECAL_ST_MASK (1 << 15)
/* Used by RM_WKUP_RSTST */
#define AM33XX_EMULATION_M3_RST_SHIFT 6
#define AM33XX_EMULATION_M3_RST_MASK (1 << 6)
/* Used by RM_MPU_RSTST */
#define AM33XX_EMULATION_MPU_RST_SHIFT 5
#define AM33XX_EMULATION_MPU_RST_MASK (1 << 5)
/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
#define AM33XX_ENFUNC1_EXPORT_SHIFT 3
#define AM33XX_ENFUNC1_EXPORT_MASK (1 << 3)
/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
#define AM33XX_ENFUNC3_EXPORT_SHIFT 5
#define AM33XX_ENFUNC3_EXPORT_MASK (1 << 5)
/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
#define AM33XX_ENFUNC4_SHIFT 6
#define AM33XX_ENFUNC4_MASK (1 << 6)
/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
#define AM33XX_ENFUNC5_SHIFT 7
#define AM33XX_ENFUNC5_MASK (1 << 7)
/* Used by PRM_RSTST */
#define AM33XX_EXTERNAL_WARM_RST_SHIFT 5
#define AM33XX_EXTERNAL_WARM_RST_MASK (1 << 5)
/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
#define AM33XX_FORCEWKUP_EN_SHIFT 10
#define AM33XX_FORCEWKUP_EN_MASK (1 << 10)
/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
#define AM33XX_FORCEWKUP_ST_SHIFT 10
#define AM33XX_FORCEWKUP_ST_MASK (1 << 10)
/* Used by PM_GFX_PWRSTCTRL */
#define AM33XX_GFX_MEM_ONSTATE_SHIFT 17
#define AM33XX_GFX_MEM_ONSTATE_MASK (0x3 << 17)
/* Used by PM_GFX_PWRSTCTRL */
#define AM33XX_GFX_MEM_RETSTATE_SHIFT 6
#define AM33XX_GFX_MEM_RETSTATE_MASK (1 << 6)
/* Used by PM_GFX_PWRSTST */
#define AM33XX_GFX_MEM_STATEST_SHIFT 4
#define AM33XX_GFX_MEM_STATEST_MASK (0x3 << 4)
/* Used by RM_GFX_RSTCTRL, RM_GFX_RSTST */
#define AM33XX_GFX_RST_SHIFT 0
#define AM33XX_GFX_RST_MASK (1 << 0)
/* Used by PRM_RSTST */
#define AM33XX_GLOBAL_COLD_RST_SHIFT 0
#define AM33XX_GLOBAL_COLD_RST_MASK (1 << 0)
/* Used by PRM_RSTST */
#define AM33XX_GLOBAL_WARM_SW_RST_SHIFT 1
#define AM33XX_GLOBAL_WARM_SW_RST_MASK (1 << 1)
/* Used by RM_WKUP_RSTST */
#define AM33XX_ICECRUSHER_M3_RST_SHIFT 7
#define AM33XX_ICECRUSHER_M3_RST_MASK (1 << 7)
/* Used by RM_MPU_RSTST */
#define AM33XX_ICECRUSHER_MPU_RST_SHIFT 6
#define AM33XX_ICECRUSHER_MPU_RST_MASK (1 << 6)
/* Used by PRM_RSTST */
#define AM33XX_ICEPICK_RST_SHIFT 9
#define AM33XX_ICEPICK_RST_MASK (1 << 9)
/* Used by RM_PER_RSTCTRL */
#define AM33XX_PRUSS_LRST_SHIFT 1
#define AM33XX_PRUSS_LRST_MASK (1 << 1)
/* Used by PM_PER_PWRSTCTRL */
#define AM33XX_PRUSS_MEM_ONSTATE_SHIFT 5
#define AM33XX_RST_GLOBAL_WARM_SW_MASK (1 << 0)
#define AM33XX_PRUSS_MEM_ONSTATE_MASK (0x3 << 5)
/* Used by PM_PER_PWRSTCTRL */
#define AM33XX_PRUSS_MEM_RETSTATE_SHIFT 7
#define AM33XX_PRUSS_MEM_RETSTATE_MASK (1 << 7)
/* Used by PM_PER_PWRSTST */
#define AM33XX_PRUSS_MEM_STATEST_SHIFT 23
#define AM33XX_PRUSS_MEM_STATEST_MASK (0x3 << 23)
/*
* Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST,
* PM_WKUP_PWRSTST, PM_RTC_PWRSTST
*/
#define AM33XX_INTRANSITION_SHIFT 20
#define AM33XX_INTRANSITION_MASK (1 << 20)
/* Used by PM_CEFUSE_PWRSTST */
#define AM33XX_LASTPOWERSTATEENTERED_SHIFT 24
#define AM33XX_LASTPOWERSTATEENTERED_MASK (0x3 << 24)
/* Used by PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_RTC_PWRSTCTRL */
#define AM33XX_LOGICRETSTATE_SHIFT 2
#define AM33XX_LOGICRETSTATE_MASK (1 << 2)
/* Renamed from LOGICRETSTATE Used by PM_PER_PWRSTCTRL, PM_WKUP_PWRSTCTRL */
#define AM33XX_LOGICRETSTATE_3_3_SHIFT 3
#define AM33XX_LOGICRETSTATE_3_3_MASK (1 << 3)
/*
* Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST,
* PM_WKUP_PWRSTST, PM_RTC_PWRSTST
*/
#define AM33XX_LOGICSTATEST_SHIFT 2
#define AM33XX_LOGICSTATEST_MASK (1 << 2)
/*
* Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL,
* PM_MPU_PWRSTCTRL, PM_WKUP_PWRSTCTRL, PM_RTC_PWRSTCTRL
*/
#define AM33XX_LOWPOWERSTATECHANGE_SHIFT 4
#define AM33XX_LOWPOWERSTATECHANGE_MASK (1 << 4)
/* Used by PM_MPU_PWRSTCTRL */
#define AM33XX_MPU_L1_ONSTATE_SHIFT 18
#define AM33XX_MPU_L1_ONSTATE_MASK (0x3 << 18)
/* Used by PM_MPU_PWRSTCTRL */
#define AM33XX_MPU_L1_RETSTATE_SHIFT 22
#define AM33XX_MPU_L1_RETSTATE_MASK (1 << 22)
/* Used by PM_MPU_PWRSTST */
#define AM33XX_MPU_L1_STATEST_SHIFT 6
#define AM33XX_MPU_L1_STATEST_MASK (0x3 << 6)
/* Used by PM_MPU_PWRSTCTRL */
#define AM33XX_MPU_L2_ONSTATE_SHIFT 20
#define AM33XX_MPU_L2_ONSTATE_MASK (0x3 << 20)
/* Used by PM_MPU_PWRSTCTRL */
#define AM33XX_MPU_L2_RETSTATE_SHIFT 23
#define AM33XX_MPU_L2_RETSTATE_MASK (1 << 23)
/* Used by PM_MPU_PWRSTST */
#define AM33XX_MPU_L2_STATEST_SHIFT 8
#define AM33XX_MPU_L2_STATEST_MASK (0x3 << 8)
/* Used by PM_MPU_PWRSTCTRL */
#define AM33XX_MPU_RAM_ONSTATE_SHIFT 16
#define AM33XX_MPU_RAM_ONSTATE_MASK (0x3 << 16)
/* Used by PM_MPU_PWRSTCTRL */
#define AM33XX_MPU_RAM_RETSTATE_SHIFT 24
#define AM33XX_MPU_RAM_RETSTATE_MASK (1 << 24)
/* Used by PM_MPU_PWRSTST */
#define AM33XX_MPU_RAM_STATEST_SHIFT 4
#define AM33XX_MPU_RAM_STATEST_MASK (0x3 << 4)
/* Used by PRM_RSTST */
#define AM33XX_MPU_SECURITY_VIOL_RST_SHIFT 2
#define AM33XX_MPU_SECURITY_VIOL_RST_MASK (1 << 2)
/* Used by PRM_SRAM_COUNT */
#define AM33XX_PCHARGECNT_VALUE_SHIFT 0
#define AM33XX_PCHARGECNT_VALUE_MASK (0x3f << 0)
/* Used by RM_PER_RSTCTRL */
#define AM33XX_PCI_LRST_SHIFT 0
#define AM33XX_PCI_LRST_MASK (1 << 0)
/* Renamed from PCI_LRST Used by RM_PER_RSTST */
#define AM33XX_PCI_LRST_5_5_SHIFT 5
#define AM33XX_PCI_LRST_5_5_MASK (1 << 5)
/* Used by PM_PER_PWRSTCTRL */
#define AM33XX_PER_MEM_ONSTATE_SHIFT 25
#define AM33XX_PER_MEM_ONSTATE_MASK (0x3 << 25)
/* Used by PM_PER_PWRSTCTRL */
#define AM33XX_PER_MEM_RETSTATE_SHIFT 29
#define AM33XX_PER_MEM_RETSTATE_MASK (1 << 29)
/* Used by PM_PER_PWRSTST */
#define AM33XX_PER_MEM_STATEST_SHIFT 17
#define AM33XX_PER_MEM_STATEST_MASK (0x3 << 17)
/*
* Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL,
* PM_MPU_PWRSTCTRL
*/
#define AM33XX_POWERSTATE_SHIFT 0
#define AM33XX_POWERSTATE_MASK (0x3 << 0)
/* Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST */
#define AM33XX_POWERSTATEST_SHIFT 0
#define AM33XX_POWERSTATEST_MASK (0x3 << 0)
/* Used by PM_PER_PWRSTCTRL */
#define AM33XX_RAM_MEM_ONSTATE_SHIFT 30
#define AM33XX_RAM_MEM_ONSTATE_MASK (0x3 << 30)
/* Used by PM_PER_PWRSTCTRL */
#define AM33XX_RAM_MEM_RETSTATE_SHIFT 27
#define AM33XX_RAM_MEM_RETSTATE_MASK (1 << 27)
/* Used by PM_PER_PWRSTST */
#define AM33XX_RAM_MEM_STATEST_SHIFT 21
#define AM33XX_RAM_MEM_STATEST_MASK (0x3 << 21)
/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
#define AM33XX_RETMODE_ENABLE_SHIFT 0
#define AM33XX_RETMODE_ENABLE_MASK (1 << 0)
/* Used by REVISION_PRM */
#define AM33XX_REV_SHIFT 0
#define AM33XX_REV_MASK (0xff << 0)
/* Used by PRM_RSTTIME */
#define AM33XX_RSTTIME1_SHIFT 0
#define AM33XX_RSTTIME1_MASK (0xff << 0)
/* Used by PRM_RSTTIME */
#define AM33XX_RSTTIME2_SHIFT 8
#define AM33XX_RSTTIME2_MASK (0x1f << 8)
/* Used by PRM_RSTCTRL */
#define AM33XX_RST_GLOBAL_COLD_SW_SHIFT 1
#define AM33XX_RST_GLOBAL_COLD_SW_MASK (1 << 1)
/* Used by PRM_RSTCTRL */
#define AM33XX_RST_GLOBAL_WARM_SW_SHIFT 0
#define AM33XX_RST_GLOBAL_WARM_SW_MASK (1 << 0)
/* Used by PRM_SRAM_COUNT */
#define AM33XX_SLPCNT_VALUE_SHIFT 16
#define AM33XX_SLPCNT_VALUE_MASK (0xff << 16)
/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
#define AM33XX_SRAMLDO_STATUS_SHIFT 8
#define AM33XX_SRAMLDO_STATUS_MASK (1 << 8)
/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
#define AM33XX_SRAM_IN_TRANSITION_SHIFT 9
#define AM33XX_SRAM_IN_TRANSITION_MASK (1 << 9)
/* Used by PRM_SRAM_COUNT */
#define AM33XX_STARTUP_COUNT_SHIFT 24
#define AM33XX_STARTUP_COUNT_MASK (0xff << 24)
/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
#define AM33XX_TRANSITION_EN_SHIFT 8
#define AM33XX_TRANSITION_EN_MASK (1 << 8)
/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
#define AM33XX_TRANSITION_ST_SHIFT 8
#define AM33XX_TRANSITION_ST_MASK (1 << 8)
/* Used by PRM_SRAM_COUNT */
#define AM33XX_VSETUPCNT_VALUE_SHIFT 8
#define AM33XX_VSETUPCNT_VALUE_MASK (0xff << 8)
/* Used by PRM_RSTST */
#define AM33XX_WDT0_RST_SHIFT 3
#define AM33XX_WDT0_RST_MASK (1 << 3)
/* Used by PRM_RSTST */
#define AM33XX_WDT1_RST_SHIFT 4
#define AM33XX_WDT1_RST_MASK (1 << 4)
/* Used by RM_WKUP_RSTCTRL */
#define AM33XX_WKUP_M3_LRST_SHIFT 3
#define AM33XX_WKUP_M3_LRST_MASK (1 << 3)
/* Renamed from WKUP_M3_LRST Used by RM_WKUP_RSTST */
#define AM33XX_WKUP_M3_LRST_5_5_SHIFT 5
#define AM33XX_WKUP_M3_LRST_5_5_MASK (1 << 5)
#endif

481
arch/arm/mach-omap2/prm-regbits-34xx.h
View File

@ -16,115 +16,25 @@
#include "prm3xxx.h"
/* Shared register bits */
/* PRM_VC_CMD_VAL_0, PRM_VC_CMD_VAL_1 shared bits */
#define OMAP3430_ON_SHIFT 24
#define OMAP3430_ON_MASK (0xff << 24)
#define OMAP3430_ONLP_SHIFT 16
#define OMAP3430_ONLP_MASK (0xff << 16)
#define OMAP3430_RET_SHIFT 8
#define OMAP3430_RET_MASK (0xff << 8)
#define OMAP3430_OFF_SHIFT 0
#define OMAP3430_OFF_MASK (0xff << 0)
/* PRM_VP1_CONFIG, PRM_VP2_CONFIG shared bits */
#define OMAP3430_ERROROFFSET_SHIFT 24
#define OMAP3430_ERROROFFSET_MASK (0xff << 24)
#define OMAP3430_ERRORGAIN_SHIFT 16
#define OMAP3430_ERRORGAIN_MASK (0xff << 16)
#define OMAP3430_INITVOLTAGE_SHIFT 8
#define OMAP3430_INITVOLTAGE_MASK (0xff << 8)
#define OMAP3430_TIMEOUTEN_MASK (1 << 3)
#define OMAP3430_INITVDD_MASK (1 << 2)
#define OMAP3430_FORCEUPDATE_MASK (1 << 1)
#define OMAP3430_VPENABLE_MASK (1 << 0)
/* PRM_VP1_VSTEPMIN, PRM_VP2_VSTEPMIN shared bits */
#define OMAP3430_SMPSWAITTIMEMIN_SHIFT 8
#define OMAP3430_SMPSWAITTIMEMIN_MASK (0xffff << 8)
#define OMAP3430_VSTEPMIN_SHIFT 0
#define OMAP3430_VSTEPMIN_MASK (0xff << 0)
/* PRM_VP1_VSTEPMAX, PRM_VP2_VSTEPMAX shared bits */
#define OMAP3430_SMPSWAITTIMEMAX_SHIFT 8
#define OMAP3430_SMPSWAITTIMEMAX_MASK (0xffff << 8)
#define OMAP3430_VSTEPMAX_SHIFT 0
#define OMAP3430_VSTEPMAX_MASK (0xff << 0)
/* PRM_VP1_VLIMITTO, PRM_VP2_VLIMITTO shared bits */
#define OMAP3430_VDDMAX_SHIFT 24
#define OMAP3430_VDDMAX_MASK (0xff << 24)
#define OMAP3430_VDDMIN_SHIFT 16
#define OMAP3430_VDDMIN_MASK (0xff << 16)
#define OMAP3430_TIMEOUT_SHIFT 0
#define OMAP3430_TIMEOUT_MASK (0xffff << 0)
/* PRM_VP1_VOLTAGE, PRM_VP2_VOLTAGE shared bits */
#define OMAP3430_VPVOLTAGE_SHIFT 0
#define OMAP3430_VPVOLTAGE_MASK (0xff << 0)
/* PRM_VP1_STATUS, PRM_VP2_STATUS shared bits */
#define OMAP3430_VPINIDLE_MASK (1 << 0)
/* PM_WKDEP_IVA2, PM_WKDEP_MPU shared bits */
#define OMAP3430_EN_PER_SHIFT 7
#define OMAP3430_EN_PER_MASK (1 << 7)
/* PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE shared bits */
#define OMAP3430_MEMORYCHANGE_MASK (1 << 3)
/* PM_PWSTST_IVA2, PM_PWSTST_CORE shared bits */
#define OMAP3430_LOGICSTATEST_MASK (1 << 2)
/* PM_PREPWSTST_IVA2, PM_PREPWSTST_CORE shared bits */
#define OMAP3430_LASTLOGICSTATEENTERED_MASK (1 << 2)
/*
* PM_PREPWSTST_IVA2, PM_PREPWSTST_MPU, PM_PREPWSTST_CORE,
* PM_PREPWSTST_GFX, PM_PREPWSTST_DSS, PM_PREPWSTST_CAM,
* PM_PREPWSTST_PER, PM_PREPWSTST_NEON shared bits
*/
#define OMAP3430_LASTPOWERSTATEENTERED_SHIFT 0
#define OMAP3430_LASTPOWERSTATEENTERED_MASK (0x3 << 0)
/* PRM_IRQSTATUS_IVA2, PRM_IRQSTATUS_MPU shared bits */
#define OMAP3430_WKUP_ST_MASK (1 << 0)
/* PRM_IRQENABLE_IVA2, PRM_IRQENABLE_MPU shared bits */
#define OMAP3430_WKUP_EN_MASK (1 << 0)
/* PM_MPUGRPSEL1_CORE, PM_IVA2GRPSEL1_CORE shared bits */
#define OMAP3430_GRPSEL_MMC2_MASK (1 << 25)
#define OMAP3430_GRPSEL_MMC1_MASK (1 << 24)
#define OMAP3430_GRPSEL_MCSPI4_MASK (1 << 21)
#define OMAP3430_GRPSEL_MCSPI3_MASK (1 << 20)
#define OMAP3430_GRPSEL_MCSPI2_MASK (1 << 19)
#define OMAP3430_GRPSEL_MCSPI1_MASK (1 << 18)
#define OMAP3430_GRPSEL_I2C3_SHIFT 17
#define OMAP3430_GRPSEL_I2C3_MASK (1 << 17)
#define OMAP3430_GRPSEL_I2C2_SHIFT 16
#define OMAP3430_GRPSEL_I2C2_MASK (1 << 16)
#define OMAP3430_GRPSEL_I2C1_SHIFT 15
#define OMAP3430_GRPSEL_I2C1_MASK (1 << 15)
#define OMAP3430_GRPSEL_UART2_MASK (1 << 14)
#define OMAP3430_GRPSEL_UART1_MASK (1 << 13)
#define OMAP3430_GRPSEL_GPT11_MASK (1 << 12)
#define OMAP3430_GRPSEL_GPT10_MASK (1 << 11)
#define OMAP3430_GRPSEL_MCBSP5_MASK (1 << 10)
#define OMAP3430_GRPSEL_MCBSP1_MASK (1 << 9)
#define OMAP3430_GRPSEL_HSOTGUSB_MASK (1 << 4)
#define OMAP3430_GRPSEL_D2D_MASK (1 << 3)
/*
* PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM,
* PM_PWSTCTRL_PER shared bits
*/
#define OMAP3430_MEMONSTATE_SHIFT 16
#define OMAP3430_MEMONSTATE_MASK (0x3 << 16)
#define OMAP3430_MEMRETSTATE_MASK (1 << 8)
/* PM_MPUGRPSEL_PER, PM_IVA2GRPSEL_PER shared bits */
#define OMAP3630_GRPSEL_UART4_MASK (1 << 18)
#define OMAP3430_GRPSEL_GPIO6_MASK (1 << 17)
#define OMAP3430_GRPSEL_GPIO5_MASK (1 << 16)
@ -132,480 +42,89 @@
#define OMAP3430_GRPSEL_GPIO3_MASK (1 << 14)
#define OMAP3430_GRPSEL_GPIO2_MASK (1 << 13)
#define OMAP3430_GRPSEL_UART3_MASK (1 << 11)
#define OMAP3430_GRPSEL_GPT9_MASK (1 << 10)
#define OMAP3430_GRPSEL_GPT8_MASK (1 << 9)
#define OMAP3430_GRPSEL_GPT7_MASK (1 << 8)
#define OMAP3430_GRPSEL_GPT6_MASK (1 << 7)
#define OMAP3430_GRPSEL_GPT5_MASK (1 << 6)
#define OMAP3430_GRPSEL_GPT4_MASK (1 << 5)
#define OMAP3430_GRPSEL_GPT3_MASK (1 << 4)
#define OMAP3430_GRPSEL_GPT2_MASK (1 << 3)
#define OMAP3430_GRPSEL_MCBSP4_MASK (1 << 2)
#define OMAP3430_GRPSEL_MCBSP3_MASK (1 << 1)
#define OMAP3430_GRPSEL_MCBSP2_MASK (1 << 0)
/* PM_MPUGRPSEL_WKUP, PM_IVA2GRPSEL_WKUP shared bits */
#define OMAP3430_GRPSEL_IO_MASK (1 << 8)
#define OMAP3430_GRPSEL_SR2_MASK (1 << 7)
#define OMAP3430_GRPSEL_SR1_MASK (1 << 6)
#define OMAP3430_GRPSEL_GPIO1_MASK (1 << 3)
#define OMAP3430_GRPSEL_GPT12_MASK (1 << 1)
#define OMAP3430_GRPSEL_GPT1_MASK (1 << 0)
/* Bits specific to each register */
/* RM_RSTCTRL_IVA2 */
#define OMAP3430_RST3_IVA2_MASK (1 << 2)
#define OMAP3430_RST2_IVA2_MASK (1 << 1)
#define OMAP3430_RST1_IVA2_MASK (1 << 0)
/* RM_RSTST_IVA2 specific bits */
#define OMAP3430_EMULATION_VSEQ_RST_MASK (1 << 13)
#define OMAP3430_EMULATION_VHWA_RST_MASK (1 << 12)
#define OMAP3430_EMULATION_IVA2_RST_MASK (1 << 11)
#define OMAP3430_IVA2_SW_RST3_MASK (1 << 10)
#define OMAP3430_IVA2_SW_RST2_MASK (1 << 9)
#define OMAP3430_IVA2_SW_RST1_MASK (1 << 8)
/* PM_WKDEP_IVA2 specific bits */
/* PM_PWSTCTRL_IVA2 specific bits */
#define OMAP3430_L2FLATMEMONSTATE_SHIFT 22
#define OMAP3430_L2FLATMEMONSTATE_MASK (0x3 << 22)
#define OMAP3430_SHAREDL2CACHEFLATONSTATE_SHIFT 20
#define OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK (0x3 << 20)
#define OMAP3430_L1FLATMEMONSTATE_SHIFT 18
#define OMAP3430_L1FLATMEMONSTATE_MASK (0x3 << 18)
#define OMAP3430_SHAREDL1CACHEFLATONSTATE_SHIFT 16
#define OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK (0x3 << 16)
#define OMAP3430_L2FLATMEMRETSTATE_MASK (1 << 11)
#define OMAP3430_SHAREDL2CACHEFLATRETSTATE_MASK (1 << 10)
#define OMAP3430_L1FLATMEMRETSTATE_MASK (1 << 9)
#define OMAP3430_SHAREDL1CACHEFLATRETSTATE_MASK (1 << 8)
/* PM_PWSTST_IVA2 specific bits */
#define OMAP3430_L2FLATMEMSTATEST_SHIFT 10
#define OMAP3430_L2FLATMEMSTATEST_MASK (0x3 << 10)
#define OMAP3430_SHAREDL2CACHEFLATSTATEST_SHIFT 8
#define OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK (0x3 << 8)
#define OMAP3430_L1FLATMEMSTATEST_SHIFT 6
#define OMAP3430_L1FLATMEMSTATEST_MASK (0x3 << 6)
#define OMAP3430_SHAREDL1CACHEFLATSTATEST_SHIFT 4
#define OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK (0x3 << 4)
/* PM_PREPWSTST_IVA2 specific bits */
#define OMAP3430_LASTL2FLATMEMSTATEENTERED_SHIFT 10
#define OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK (0x3 << 10)
#define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_SHIFT 8
#define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK (0x3 << 8)
#define OMAP3430_LASTL1FLATMEMSTATEENTERED_SHIFT 6
#define OMAP3430_LASTL1FLATMEMSTATEENTERED_MASK (0x3 << 6)
#define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_SHIFT 4
#define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_MASK (0x3 << 4)
/* PRM_IRQSTATUS_IVA2 specific bits */
#define OMAP3430_PRM_IRQSTATUS_IVA2_IVA2_DPLL_ST_MASK (1 << 2)
#define OMAP3430_FORCEWKUP_ST_MASK (1 << 1)
/* PRM_IRQENABLE_IVA2 specific bits */
#define OMAP3430_PRM_IRQENABLE_IVA2_IVA2_DPLL_RECAL_EN_MASK (1 << 2)
#define OMAP3430_FORCEWKUP_EN_MASK (1 << 1)
/* PRM_REVISION specific bits */
/* PRM_SYSCONFIG specific bits */
/* PRM_IRQSTATUS_MPU specific bits */
#define OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT 25
#define OMAP3430ES2_SND_PERIPH_DPLL_ST_MASK (1 << 25)
#define OMAP3430_VC_TIMEOUTERR_ST_MASK (1 << 24)
#define OMAP3430_VC_RAERR_ST_MASK (1 << 23)
#define OMAP3430_VC_SAERR_ST_MASK (1 << 22)
#define OMAP3430_VP2_TRANXDONE_ST_MASK (1 << 21)
#define OMAP3430_VP2_EQVALUE_ST_MASK (1 << 20)
#define OMAP3430_VP2_NOSMPSACK_ST_MASK (1 << 19)
#define OMAP3430_VP2_MAXVDD_ST_MASK (1 << 18)
#define OMAP3430_VP2_MINVDD_ST_MASK (1 << 17)
#define OMAP3430_VP2_OPPCHANGEDONE_ST_MASK (1 << 16)
#define OMAP3430_VP1_TRANXDONE_ST_MASK (1 << 15)
#define OMAP3430_VP1_EQVALUE_ST_MASK (1 << 14)
#define OMAP3430_VP1_NOSMPSACK_ST_MASK (1 << 13)
#define OMAP3430_VP1_MAXVDD_ST_MASK (1 << 12)
#define OMAP3430_VP1_MINVDD_ST_MASK (1 << 11)
#define OMAP3430_VP1_OPPCHANGEDONE_ST_MASK (1 << 10)
#define OMAP3430_IO_ST_MASK (1 << 9)
#define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_MASK (1 << 8)
#define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT 8
#define OMAP3430_MPU_DPLL_ST_MASK (1 << 7)
#define OMAP3430_MPU_DPLL_ST_SHIFT 7
#define OMAP3430_PERIPH_DPLL_ST_MASK (1 << 6)
#define OMAP3430_PERIPH_DPLL_ST_SHIFT 6
#define OMAP3430_CORE_DPLL_ST_MASK (1 << 5)
#define OMAP3430_CORE_DPLL_ST_SHIFT 5
#define OMAP3430_TRANSITION_ST_MASK (1 << 4)
#define OMAP3430_EVGENOFF_ST_MASK (1 << 3)
#define OMAP3430_EVGENON_ST_MASK (1 << 2)
#define OMAP3430_FS_USB_WKUP_ST_MASK (1 << 1)
/* PRM_IRQENABLE_MPU specific bits */
#define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT 25
#define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_MASK (1 << 25)
#define OMAP3430_VC_TIMEOUTERR_EN_MASK (1 << 24)
#define OMAP3430_VC_RAERR_EN_MASK (1 << 23)
#define OMAP3430_VC_SAERR_EN_MASK (1 << 22)
#define OMAP3430_VP2_TRANXDONE_EN_MASK (1 << 21)
#define OMAP3430_VP2_EQVALUE_EN_MASK (1 << 20)
#define OMAP3430_VP2_NOSMPSACK_EN_MASK (1 << 19)
#define OMAP3430_VP2_MAXVDD_EN_MASK (1 << 18)
#define OMAP3430_VP2_MINVDD_EN_MASK (1 << 17)
#define OMAP3430_VP2_OPPCHANGEDONE_EN_MASK (1 << 16)
#define OMAP3430_VP1_TRANXDONE_EN_MASK (1 << 15)
#define OMAP3430_VP1_EQVALUE_EN_MASK (1 << 14)
#define OMAP3430_VP1_NOSMPSACK_EN_MASK (1 << 13)
#define OMAP3430_VP1_MAXVDD_EN_MASK (1 << 12)
#define OMAP3430_VP1_MINVDD_EN_MASK (1 << 11)
#define OMAP3430_VP1_OPPCHANGEDONE_EN_MASK (1 << 10)
#define OMAP3430_IO_EN_MASK (1 << 9)
#define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_MASK (1 << 8)
#define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT 8
#define OMAP3430_MPU_DPLL_RECAL_EN_MASK (1 << 7)
#define OMAP3430_MPU_DPLL_RECAL_EN_SHIFT 7
#define OMAP3430_PERIPH_DPLL_RECAL_EN_MASK (1 << 6)
#define OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT 6
#define OMAP3430_CORE_DPLL_RECAL_EN_MASK (1 << 5)
#define OMAP3430_CORE_DPLL_RECAL_EN_SHIFT 5
#define OMAP3430_TRANSITION_EN_MASK (1 << 4)
#define OMAP3430_EVGENOFF_EN_MASK (1 << 3)
#define OMAP3430_EVGENON_EN_MASK (1 << 2)
#define OMAP3430_FS_USB_WKUP_EN_MASK (1 << 1)
/* RM_RSTST_MPU specific bits */
#define OMAP3430_EMULATION_MPU_RST_MASK (1 << 11)
/* PM_WKDEP_MPU specific bits */
#define OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT 5
#define OMAP3430_PM_WKDEP_MPU_EN_DSS_MASK (1 << 5)
#define OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT 2
#define OMAP3430_PM_WKDEP_MPU_EN_IVA2_MASK (1 << 2)
/* PM_EVGENCTRL_MPU */
#define OMAP3430_OFFLOADMODE_SHIFT 3
#define OMAP3430_OFFLOADMODE_MASK (0x3 << 3)
#define OMAP3430_ONLOADMODE_SHIFT 1
#define OMAP3430_ONLOADMODE_MASK (0x3 << 1)
#define OMAP3430_ENABLE_MASK (1 << 0)
/* PM_EVGENONTIM_MPU */
#define OMAP3430_ONTIMEVAL_SHIFT 0
#define OMAP3430_ONTIMEVAL_MASK (0xffffffff << 0)
/* PM_EVGENOFFTIM_MPU */
#define OMAP3430_OFFTIMEVAL_SHIFT 0
#define OMAP3430_OFFTIMEVAL_MASK (0xffffffff << 0)
/* PM_PWSTCTRL_MPU specific bits */
#define OMAP3430_L2CACHEONSTATE_SHIFT 16
#define OMAP3430_L2CACHEONSTATE_MASK (0x3 << 16)
#define OMAP3430_L2CACHERETSTATE_MASK (1 << 8)
#define OMAP3430_LOGICL1CACHERETSTATE_MASK (1 << 2)
/* PM_PWSTST_MPU specific bits */
#define OMAP3430_L2CACHESTATEST_SHIFT 6
#define OMAP3430_L2CACHESTATEST_MASK (0x3 << 6)
#define OMAP3430_LOGICL1CACHESTATEST_MASK (1 << 2)
/* PM_PREPWSTST_MPU specific bits */
#define OMAP3430_LASTL2CACHESTATEENTERED_SHIFT 6
#define OMAP3430_LASTL2CACHESTATEENTERED_MASK (0x3 << 6)
#define OMAP3430_LASTLOGICL1CACHESTATEENTERED_MASK (1 << 2)
/* RM_RSTCTRL_CORE */
#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK (1 << 1)
#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK (1 << 0)
/* RM_RSTST_CORE specific bits */
#define OMAP3430_MODEM_SECURITY_VIOL_RST_MASK (1 << 10)
#define OMAP3430_RM_RSTST_CORE_MODEM_SW_RSTPWRON_MASK (1 << 9)
#define OMAP3430_RM_RSTST_CORE_MODEM_SW_RST_MASK (1 << 8)
/* PM_WKEN1_CORE specific bits */
/* PM_MPUGRPSEL1_CORE specific bits */
#define OMAP3430_GRPSEL_FSHOSTUSB_MASK (1 << 5)
/* PM_IVA2GRPSEL1_CORE specific bits */
/* PM_WKST1_CORE specific bits */
/* PM_PWSTCTRL_CORE specific bits */
#define OMAP3430_MEM2ONSTATE_SHIFT 18
#define OMAP3430_MEM2ONSTATE_MASK (0x3 << 18)
#define OMAP3430_MEM1ONSTATE_SHIFT 16
#define OMAP3430_MEM1ONSTATE_MASK (0x3 << 16)
#define OMAP3430_MEM2RETSTATE_MASK (1 << 9)
#define OMAP3430_MEM1RETSTATE_MASK (1 << 8)
/* PM_PWSTST_CORE specific bits */
#define OMAP3430_MEM2STATEST_SHIFT 6
#define OMAP3430_MEM2STATEST_MASK (0x3 << 6)
#define OMAP3430_MEM1STATEST_SHIFT 4
#define OMAP3430_MEM1STATEST_MASK (0x3 << 4)
/* PM_PREPWSTST_CORE specific bits */
#define OMAP3430_LASTMEM2STATEENTERED_SHIFT 6
#define OMAP3430_LASTMEM2STATEENTERED_MASK (0x3 << 6)
#define OMAP3430_LASTMEM1STATEENTERED_SHIFT 4
#define OMAP3430_LASTMEM1STATEENTERED_MASK (0x3 << 4)
/* RM_RSTST_GFX specific bits */
/* PM_WKDEP_GFX specific bits */
#define OMAP3430_PM_WKDEP_GFX_EN_IVA2_MASK (1 << 2)
/* PM_PWSTCTRL_GFX specific bits */
/* PM_PWSTST_GFX specific bits */
/* PM_PREPWSTST_GFX specific bits */
/* PM_WKEN_WKUP specific bits */
#define OMAP3430_EN_IO_CHAIN_MASK (1 << 16)
#define OMAP3430_EN_IO_MASK (1 << 8)
#define OMAP3430_EN_GPIO1_MASK (1 << 3)
/* PM_MPUGRPSEL_WKUP specific bits */
/* PM_IVA2GRPSEL_WKUP specific bits */
/* PM_WKST_WKUP specific bits */
#define OMAP3430_ST_IO_CHAIN_MASK (1 << 16)
#define OMAP3430_ST_IO_MASK (1 << 8)
/* PRM_CLKSEL */
#define OMAP3430_SYS_CLKIN_SEL_SHIFT 0
#define OMAP3430_SYS_CLKIN_SEL_MASK (0x7 << 0)
#define OMAP3430_SYS_CLKIN_SEL_WIDTH 3
/* PRM_CLKOUT_CTRL */
#define OMAP3430_CLKOUT_EN_MASK (1 << 7)
#define OMAP3430_CLKOUT_EN_SHIFT 7
/* RM_RSTST_DSS specific bits */
/* PM_WKEN_DSS */
#define OMAP3430_PM_WKEN_DSS_EN_DSS_MASK (1 << 0)
/* PM_WKDEP_DSS specific bits */
#define OMAP3430_PM_WKDEP_DSS_EN_IVA2_MASK (1 << 2)
/* PM_PWSTCTRL_DSS specific bits */
/* PM_PWSTST_DSS specific bits */
/* PM_PREPWSTST_DSS specific bits */
/* RM_RSTST_CAM specific bits */
/* PM_WKDEP_CAM specific bits */
#define OMAP3430_PM_WKDEP_CAM_EN_IVA2_MASK (1 << 2)
/* PM_PWSTCTRL_CAM specific bits */
/* PM_PWSTST_CAM specific bits */
/* PM_PREPWSTST_CAM specific bits */
/* PM_PWSTCTRL_USBHOST specific bits */
#define OMAP3430ES2_SAVEANDRESTORE_SHIFT 4
/* RM_RSTST_PER specific bits */
/* PM_WKEN_PER specific bits */
/* PM_MPUGRPSEL_PER specific bits */
/* PM_IVA2GRPSEL_PER specific bits */
/* PM_WKST_PER specific bits */
/* PM_WKDEP_PER specific bits */
#define OMAP3430_PM_WKDEP_PER_EN_IVA2_MASK (1 << 2)
/* PM_PWSTCTRL_PER specific bits */
/* PM_PWSTST_PER specific bits */
/* PM_PREPWSTST_PER specific bits */
/* RM_RSTST_EMU specific bits */
/* PM_PWSTST_EMU specific bits */
/* PRM_VC_SMPS_SA */
#define OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT 16
#define OMAP3430_PRM_VC_SMPS_SA_SA1_MASK (0x7f << 16)
#define OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT 0
#define OMAP3430_PRM_VC_SMPS_SA_SA0_MASK (0x7f << 0)
/* PRM_VC_SMPS_VOL_RA */
#define OMAP3430_VOLRA1_SHIFT 16
#define OMAP3430_VOLRA1_MASK (0xff << 16)
#define OMAP3430_VOLRA0_SHIFT 0
#define OMAP3430_VOLRA0_MASK (0xff << 0)
/* PRM_VC_SMPS_CMD_RA */
#define OMAP3430_CMDRA1_SHIFT 16
#define OMAP3430_CMDRA1_MASK (0xff << 16)
#define OMAP3430_CMDRA0_SHIFT 0
#define OMAP3430_CMDRA0_MASK (0xff << 0)
/* PRM_VC_CMD_VAL_0 specific bits */
#define OMAP3430_VC_CMD_ON_SHIFT 24
#define OMAP3430_VC_CMD_ON_MASK (0xFF << 24)
#define OMAP3430_VC_CMD_ONLP_SHIFT 16
#define OMAP3430_VC_CMD_ONLP_MASK (0xFF << 16)
#define OMAP3430_VC_CMD_RET_SHIFT 8
#define OMAP3430_VC_CMD_RET_MASK (0xFF << 8)
#define OMAP3430_VC_CMD_OFF_SHIFT 0
#define OMAP3430_VC_CMD_OFF_MASK (0xFF << 0)
/* PRM_VC_CMD_VAL_1 specific bits */
/* PRM_VC_CH_CONF */
#define OMAP3430_CMD1_MASK (1 << 20)
#define OMAP3430_RACEN1_MASK (1 << 19)
#define OMAP3430_RAC1_MASK (1 << 18)
#define OMAP3430_RAV1_MASK (1 << 17)
#define OMAP3430_PRM_VC_CH_CONF_SA1_MASK (1 << 16)
#define OMAP3430_CMD0_MASK (1 << 4)
#define OMAP3430_RACEN0_MASK (1 << 3)
#define OMAP3430_RAC0_MASK (1 << 2)
#define OMAP3430_RAV0_MASK (1 << 1)
#define OMAP3430_PRM_VC_CH_CONF_SA0_MASK (1 << 0)
/* PRM_VC_I2C_CFG */
#define OMAP3430_HSMASTER_MASK (1 << 5)
#define OMAP3430_SREN_MASK (1 << 4)
#define OMAP3430_HSEN_MASK (1 << 3)
#define OMAP3430_MCODE_SHIFT 0
#define OMAP3430_MCODE_MASK (0x7 << 0)
/* PRM_VC_BYPASS_VAL */
#define OMAP3430_VALID_MASK (1 << 24)
#define OMAP3430_DATA_SHIFT 16
#define OMAP3430_DATA_MASK (0xff << 16)
#define OMAP3430_REGADDR_SHIFT 8
#define OMAP3430_REGADDR_MASK (0xff << 8)
#define OMAP3430_SLAVEADDR_SHIFT 0
#define OMAP3430_SLAVEADDR_MASK (0x7f << 0)
/* PRM_RSTCTRL */
#define OMAP3430_RST_DPLL3_MASK (1 << 2)
#define OMAP3430_RST_GS_MASK (1 << 1)
/* PRM_RSTTIME */
#define OMAP3430_RSTTIME2_SHIFT 8
#define OMAP3430_RSTTIME2_MASK (0x1f << 8)
#define OMAP3430_RSTTIME1_SHIFT 0
#define OMAP3430_RSTTIME1_MASK (0xff << 0)
/* PRM_RSTST */
#define OMAP3430_ICECRUSHER_RST_SHIFT 10
#define OMAP3430_ICECRUSHER_RST_MASK (1 << 10)
#define OMAP3430_ICEPICK_RST_SHIFT 9
#define OMAP3430_ICEPICK_RST_MASK (1 << 9)
#define OMAP3430_VDD2_VOLTAGE_MANAGER_RST_SHIFT 8
#define OMAP3430_VDD2_VOLTAGE_MANAGER_RST_MASK (1 << 8)
#define OMAP3430_VDD1_VOLTAGE_MANAGER_RST_SHIFT 7
#define OMAP3430_VDD1_VOLTAGE_MANAGER_RST_MASK (1 << 7)
#define OMAP3430_EXTERNAL_WARM_RST_SHIFT 6
#define OMAP3430_EXTERNAL_WARM_RST_MASK (1 << 6)
#define OMAP3430_SECURE_WD_RST_SHIFT 5
#define OMAP3430_SECURE_WD_RST_MASK (1 << 5)
#define OMAP3430_MPU_WD_RST_SHIFT 4
#define OMAP3430_MPU_WD_RST_MASK (1 << 4)
#define OMAP3430_SECURITY_VIOL_RST_SHIFT 3
#define OMAP3430_SECURITY_VIOL_RST_MASK (1 << 3)
#define OMAP3430_GLOBAL_SW_RST_SHIFT 1
#define OMAP3430_GLOBAL_SW_RST_MASK (1 << 1)
#define OMAP3430_GLOBAL_COLD_RST_SHIFT 0
#define OMAP3430_GLOBAL_COLD_RST_MASK (1 << 0)
/* PRM_VOLTCTRL */
#define OMAP3430_SEL_VMODE_MASK (1 << 4)
#define OMAP3430_SEL_OFF_MASK (1 << 3)
#define OMAP3430_AUTO_OFF_MASK (1 << 2)
#define OMAP3430_AUTO_RET_MASK (1 << 1)
#define OMAP3430_AUTO_SLEEP_MASK (1 << 0)
/* PRM_SRAM_PCHARGE */
#define OMAP3430_PCHARGE_TIME_SHIFT 0
#define OMAP3430_PCHARGE_TIME_MASK (0xff << 0)
/* PRM_CLKSRC_CTRL */
#define OMAP3430_SYSCLKDIV_SHIFT 6
#define OMAP3430_SYSCLKDIV_MASK (0x3 << 6)
#define OMAP3430_AUTOEXTCLKMODE_SHIFT 3
#define OMAP3430_AUTOEXTCLKMODE_MASK (0x3 << 3)
#define OMAP3430_SYSCLKSEL_SHIFT 0
#define OMAP3430_SYSCLKSEL_MASK (0x3 << 0)
/* PRM_VOLTSETUP1 */
#define OMAP3430_SETUP_TIME2_SHIFT 16
#define OMAP3430_SETUP_TIME2_MASK (0xffff << 16)
#define OMAP3430_SETUP_TIME1_SHIFT 0
#define OMAP3430_SETUP_TIME1_MASK (0xffff << 0)
/* PRM_VOLTOFFSET */
#define OMAP3430_OFFSET_TIME_SHIFT 0
#define OMAP3430_OFFSET_TIME_MASK (0xffff << 0)
/* PRM_CLKSETUP */
#define OMAP3430_SETUP_TIME_SHIFT 0
#define OMAP3430_SETUP_TIME_MASK (0xffff << 0)
/* PRM_POLCTRL */
#define OMAP3430_OFFMODE_POL_MASK (1 << 3)
#define OMAP3430_CLKOUT_POL_MASK (1 << 2)
#define OMAP3430_CLKREQ_POL_MASK (1 << 1)
#define OMAP3430_EXTVOL_POL_MASK (1 << 0)
/* PRM_VOLTSETUP2 */
#define OMAP3430_OFFMODESETUPTIME_SHIFT 0
#define OMAP3430_OFFMODESETUPTIME_MASK (0xffff << 0)
/* PRM_VP1_CONFIG specific bits */
/* PRM_VP1_VSTEPMIN specific bits */
/* PRM_VP1_VSTEPMAX specific bits */
/* PRM_VP1_VLIMITTO specific bits */
/* PRM_VP1_VOLTAGE specific bits */
/* PRM_VP1_STATUS specific bits */
/* PRM_VP2_CONFIG specific bits */
/* PRM_VP2_VSTEPMIN specific bits */
/* PRM_VP2_VSTEPMAX specific bits */
/* PRM_VP2_VLIMITTO specific bits */
/* PRM_VP2_VOLTAGE specific bits */
/* PRM_VP2_STATUS specific bits */
/* RM_RSTST_NEON specific bits */
/* PM_WKDEP_NEON specific bits */
/* PM_PWSTCTRL_NEON specific bits */
/* PM_PWSTST_NEON specific bits */
/* PM_PREPWSTST_NEON specific bits */
#endif

2226
arch/arm/mach-omap2/prm-regbits-44xx.h
View File

File diff suppressed because it is too large Load Diff

2701
arch/arm/mach-omap2/prm-regbits-54xx.h
View File

File diff suppressed because it is too large Load Diff

6
arch/arm/mach-omap2/timer.c
View File

@ -600,7 +600,7 @@ static OMAP_SYS_32K_TIMER_INIT(4, 1, "timer_32k_ck", "ti,timer-alwon",
#endif
#ifdef CONFIG_ARCH_OMAP4
#ifdef CONFIG_LOCAL_TIMERS
#ifdef CONFIG_HAVE_ARM_TWD
static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, OMAP44XX_LOCAL_TWD_BASE, 29);
void __init omap4_local_timer_init(void)
{
@ -619,12 +619,12 @@ void __init omap4_local_timer_init(void)
pr_err("twd_local_timer_register failed %d\n", err);
}
}
#else /* CONFIG_LOCAL_TIMERS */
#else
void __init omap4_local_timer_init(void)
{
omap4_sync32k_timer_init();
}
#endif /* CONFIG_LOCAL_TIMERS */
#endif /* CONFIG_HAVE_ARM_TWD */
#endif /* CONFIG_ARCH_OMAP4 */
#ifdef CONFIG_SOC_OMAP5

2
arch/arm/mach-pxa/cm-x300.c
View File

@ -29,7 +29,7 @@
#include <linux/pwm_backlight.h>
#include <linux/i2c.h>
#include <linux/i2c/pca953x.h>
#include <linux/platform_data/pca953x.h>
#include <linux/i2c/pxa-i2c.h>
#include <linux/mfd/da903x.h>

2
arch/arm/mach-pxa/em-x270.c
View File

@ -30,7 +30,7 @@
#include <linux/power_supply.h>
#include <linux/apm-emulation.h>
#include <linux/i2c.h>
#include <linux/i2c/pca953x.h>
#include <linux/platform_data/pca953x.h>
#include <linux/i2c/pxa-i2c.h>
#include <linux/regulator/userspace-consumer.h>

2
arch/arm/mach-pxa/pcm990-baseboard.c
View File

@ -408,7 +408,7 @@ struct pxacamera_platform_data pcm990_pxacamera_platform_data = {
.mclk_10khz = 1000,
};
#include <linux/i2c/pca953x.h>
#include <linux/platform_data/pca953x.h>
static struct pca953x_platform_data pca9536_data = {
.gpio_base = PXA_NR_BUILTIN_GPIO,

2
arch/arm/mach-pxa/spitz.c
View File

@ -20,7 +20,7 @@
#include <linux/leds.h>
#include <linux/i2c.h>
#include <linux/i2c/pxa-i2c.h>
#include <linux/i2c/pca953x.h>
#include <linux/platform_data/pca953x.h>
#include <linux/spi/spi.h>
#include <linux/spi/ads7846.h>
#include <linux/spi/corgi_lcd.h>

2
arch/arm/mach-pxa/zeus.c
View File

@ -26,7 +26,7 @@
#include <linux/mtd/physmap.h>
#include <linux/i2c.h>
#include <linux/i2c/pxa-i2c.h>
#include <linux/i2c/pca953x.h>
#include <linux/platform_data/pca953x.h>
#include <linux/apm-emulation.h>
#include <linux/can/platform/mcp251x.h>
#include <linux/regulator/fixed.h>

2
arch/arm/mach-pxa/zylonite_pxa300.c
View File

@ -18,7 +18,7 @@
#include <linux/init.h>
#include <linux/i2c.h>
#include <linux/i2c/pxa-i2c.h>
#include <linux/i2c/pca953x.h>
#include <linux/platform_data/pca953x.h>
#include <linux/gpio.h>
#include <mach/pxa300.h>

8
arch/arm/mach-realview/Kconfig
View File

@ -13,7 +13,7 @@ config REALVIEW_EB_A9MP
depends on MACH_REALVIEW_EB
select CPU_V7
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if LOCAL_TIMERS
select HAVE_ARM_TWD if SMP
select HAVE_SMP
select MIGHT_HAVE_CACHE_L2X0
help
@ -26,7 +26,7 @@ config REALVIEW_EB_ARM11MP
select ARCH_HAS_BARRIERS if SMP
select CPU_V6K
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if LOCAL_TIMERS
select HAVE_ARM_TWD if SMP
select HAVE_SMP
select MIGHT_HAVE_CACHE_L2X0
help
@ -48,7 +48,7 @@ config MACH_REALVIEW_PB11MP
select ARM_GIC
select CPU_V6K
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if LOCAL_TIMERS
select HAVE_ARM_TWD if SMP
select HAVE_PATA_PLATFORM
select HAVE_SMP
select MIGHT_HAVE_CACHE_L2X0
@ -92,7 +92,7 @@ config MACH_REALVIEW_PBX
select ARCH_SPARSEMEM_ENABLE if CPU_V7 && !REALVIEW_HIGH_PHYS_OFFSET
select ARM_GIC
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if LOCAL_TIMERS
select HAVE_ARM_TWD if SMP
select HAVE_PATA_PLATFORM
select HAVE_SMP
select MIGHT_HAVE_CACHE_L2X0

6
arch/arm/mach-s3c24xx/Kconfig
View File

@ -30,7 +30,6 @@ config CPU_S3C2410
select S3C2410_CLOCK
select ARM_S3C2410_CPUFREQ if ARM_S3C24XX_CPUFREQ
select S3C2410_PM if PM
select SAMSUNG_HRT
select SAMSUNG_WDT_RESET
help
Support for S3C2410 and S3C2410A family from the S3C24XX line
@ -42,7 +41,6 @@ config CPU_S3C2412
select CPU_LLSERIAL_S3C2440
select S3C2412_DMA if S3C24XX_DMA
select S3C2412_PM if PM
select SAMSUNG_HRT
help
Support for the S3C2412 and S3C2413 SoCs from the S3C24XX line
@ -54,7 +52,6 @@ config CPU_S3C2416
select S3C2443_COMMON
select S3C2443_DMA if S3C24XX_DMA
select SAMSUNG_CLKSRC
select SAMSUNG_HRT
help
Support for the S3C2416 SoC from the S3C24XX line
@ -65,7 +62,6 @@ config CPU_S3C2440
select S3C2410_CLOCK
select S3C2410_PM if PM
select S3C2440_DMA if S3C24XX_DMA
select SAMSUNG_HRT
help
Support for S3C2440 Samsung Mobile CPU based systems.
@ -75,7 +71,6 @@ config CPU_S3C2442
select CPU_LLSERIAL_S3C2440
select S3C2410_CLOCK
select S3C2410_PM if PM
select SAMSUNG_HRT
help
Support for S3C2442 Samsung Mobile CPU based systems.
@ -91,7 +86,6 @@ config CPU_S3C2443
select S3C2443_COMMON
select S3C2443_DMA if S3C24XX_DMA
select SAMSUNG_CLKSRC
select SAMSUNG_HRT
help
Support for the S3C2443 SoC from the S3C24XX line

1
arch/arm/mach-s3c24xx/clock-s3c2410.c
View File

@ -281,6 +281,5 @@ int __init s3c2410_baseclk_add(void)
(clkslow & S3C2410_CLKSLOW_MPLL_OFF) ? "off" : "on",
(clkslow & S3C2410_CLKSLOW_UCLK_OFF) ? "off" : "on");
s3c_pwmclk_init();
return 0;
}

1
arch/arm/mach-s3c24xx/clock-s3c2412.c
View File

@ -757,6 +757,5 @@ int __init s3c2412_baseclk_add(void)
}
clkdev_add_table(s3c2412_clk_lookup, ARRAY_SIZE(s3c2412_clk_lookup));
s3c_pwmclk_init();
return 0;
}

2
arch/arm/mach-s3c24xx/clock-s3c2416.c
View File

@ -168,6 +168,4 @@ void __init s3c2416_init_clocks(int xtal)
s3c24xx_register_clock(&hsmmc0_clk);
clkdev_add_table(s3c2416_clk_lookup, ARRAY_SIZE(s3c2416_clk_lookup));
s3c_pwmclk_init();
}

2
arch/arm/mach-s3c24xx/clock-s3c2443.c
View File

@ -209,6 +209,4 @@ void __init s3c2443_init_clocks(int xtal)
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
clkdev_add_table(s3c2443_clk_lookup, ARRAY_SIZE(s3c2443_clk_lookup));
s3c_pwmclk_init();
}

27
arch/arm/mach-s3c24xx/common.c
View File

@ -27,6 +27,7 @@
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/serial_core.h>
#include <clocksource/samsung_pwm.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/io.h>
@ -49,6 +50,7 @@
#include <plat/clock.h>
#include <plat/cpu-freq.h>
#include <plat/pll.h>
#include <plat/pwm-core.h>
#include "common.h"
@ -216,6 +218,13 @@ static void s3c24xx_default_idle(void)
S3C2410_CLKCON);
}
static struct samsung_pwm_variant s3c24xx_pwm_variant = {
.bits = 16,
.div_base = 1,
.has_tint_cstat = false,
.tclk_mask = (1 << 4),
};
void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
{
arm_pm_idle = s3c24xx_default_idle;
@ -232,6 +241,24 @@ void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
s3c24xx_init_cpu();
s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
samsung_pwm_set_platdata(&s3c24xx_pwm_variant);
}
void __init samsung_set_timer_source(unsigned int event, unsigned int source)
{
s3c24xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
s3c24xx_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
}
void __init samsung_timer_init(void)
{
unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
IRQ_TIMER0, IRQ_TIMER1, IRQ_TIMER2, IRQ_TIMER3, IRQ_TIMER4,
};
samsung_pwm_clocksource_init(S3C_VA_TIMER,
timer_irqs, &s3c24xx_pwm_variant);
}
/* Serial port registrations */

2
arch/arm/mach-s3c24xx/include/mach/map.h
View File

@ -167,4 +167,6 @@
#define S3C_PA_SPI0 S3C2443_PA_SPI0
#define S3C_PA_SPI1 S3C2443_PA_SPI1
#define SAMSUNG_PA_TIMER S3C2410_PA_TIMER
#endif /* __ASM_ARCH_MAP_H */

4
arch/arm/mach-s3c24xx/mach-h1940.c
View File

@ -512,7 +512,7 @@ static struct platform_pwm_backlight_data backlight_data = {
static struct platform_device h1940_backlight = {
.name = "pwm-backlight",
.dev = {
.parent = &s3c_device_timer[0].dev,
.parent = &samsung_device_pwm.dev,
.platform_data = &backlight_data,
},
.id = -1,
@ -632,7 +632,7 @@ static struct platform_device *h1940_devices[] __initdata = {
&h1940_device_bluetooth,
&s3c_device_sdi,
&s3c_device_rtc,
&s3c_device_timer[0],
&samsung_device_pwm,
&h1940_backlight,
&h1940_lcd_powerdev,
&s3c_device_adc,

5
arch/arm/mach-s3c24xx/mach-rx1950.c
View File

@ -530,7 +530,7 @@ static struct platform_pwm_backlight_data rx1950_backlight_data = {
static struct platform_device rx1950_backlight = {
.name = "pwm-backlight",
.dev = {
.parent = &s3c_device_timer[0].dev,
.parent = &samsung_device_pwm.dev,
.platform_data = &rx1950_backlight_data,
},
};
@ -717,8 +717,7 @@ static struct platform_device *rx1950_devices[] __initdata = {
&s3c_device_sdi,
&s3c_device_adc,
&s3c_device_ts,
&s3c_device_timer[0],
&s3c_device_timer[1],
&samsung_device_pwm,
&rx1950_backlight,
&rx1950_device_gpiokeys,
&power_supply,

2
arch/arm/mach-s3c64xx/Kconfig
View File

@ -17,13 +17,11 @@ config PLAT_S3C64XX
# Configuration options for the S3C6410 CPU
config CPU_S3C6400
select SAMSUNG_HRT
bool
help
Enable S3C6400 CPU support
config CPU_S3C6410
select SAMSUNG_HRT
bool
help
Enable S3C6410 CPU support

2
arch/arm/mach-s3c64xx/clock.c
View File

@ -1004,6 +1004,4 @@ void __init s3c64xx_register_clocks(unsigned long xtal,
for (cnt = 0; cnt < ARRAY_SIZE(clksrc_cdev); cnt++)
s3c_register_clksrc(clksrc_cdev[cnt], 1);
clkdev_add_table(s3c64xx_clk_lookup, ARRAY_SIZE(s3c64xx_clk_lookup));
s3c_pwmclk_init();
}

32
arch/arm/mach-s3c64xx/common.c
View File

@ -27,6 +27,7 @@
#include <linux/irq.h>
#include <linux/gpio.h>
#include <linux/irqchip/arm-vic.h>
#include <clocksource/samsung_pwm.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
@ -42,7 +43,7 @@
#include <plat/pm.h>
#include <plat/gpio-cfg.h>
#include <plat/irq-uart.h>
#include <plat/irq-vic-timer.h>
#include <plat/pwm-core.h>
#include <plat/regs-irqtype.h>
#include <plat/regs-serial.h>
#include <plat/watchdog-reset.h>
@ -149,6 +150,30 @@ static struct device s3c64xx_dev = {
.bus = &s3c64xx_subsys,
};
static struct samsung_pwm_variant s3c64xx_pwm_variant = {
.bits = 32,
.div_base = 0,
.has_tint_cstat = true,
.tclk_mask = (1 << 7) | (1 << 6) | (1 << 5),
};
void __init samsung_set_timer_source(unsigned int event, unsigned int source)
{
s3c64xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
s3c64xx_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
}
void __init samsung_timer_init(void)
{
unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
IRQ_TIMER3_VIC, IRQ_TIMER4_VIC,
};
samsung_pwm_clocksource_init(S3C_VA_TIMER,
timer_irqs, &s3c64xx_pwm_variant);
}
/* read cpu identification code */
void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
@ -161,6 +186,8 @@ void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
s3c64xx_init_cpu();
s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
samsung_pwm_set_platdata(&s3c64xx_pwm_variant);
}
static __init int s3c64xx_dev_init(void)
@ -195,9 +222,6 @@ void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
/* initialise the pair of VICs */
vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, IRQ_VIC0_RESUME);
vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, IRQ_VIC1_RESUME);
/* add the timer sub-irqs */
s3c_init_vic_timer_irq(5, IRQ_TIMER0);
}
#define eint_offset(irq) ((irq) - IRQ_EINT(0))

8
arch/arm/mach-s3c64xx/include/mach/irqs.h
View File

@ -107,14 +107,6 @@
#define IRQ_TC IRQ_PENDN
#define IRQ_ADC S3C64XX_IRQ_VIC1(31)
#define S3C64XX_TIMER_IRQ(x) S3C_IRQ(64 + (x))
#define IRQ_TIMER0 S3C64XX_TIMER_IRQ(0)
#define IRQ_TIMER1 S3C64XX_TIMER_IRQ(1)
#define IRQ_TIMER2 S3C64XX_TIMER_IRQ(2)
#define IRQ_TIMER3 S3C64XX_TIMER_IRQ(3)
#define IRQ_TIMER4 S3C64XX_TIMER_IRQ(4)
/* compatibility for device defines */
#define IRQ_IIC1 IRQ_S3C6410_IIC1

1
arch/arm/mach-s3c64xx/include/mach/map.h
View File

@ -121,5 +121,6 @@
#define SAMSUNG_PA_ADC S3C64XX_PA_ADC
#define SAMSUNG_PA_CFCON S3C64XX_PA_CFCON
#define SAMSUNG_PA_KEYPAD S3C64XX_PA_KEYPAD
#define SAMSUNG_PA_TIMER S3C64XX_PA_TIMER
#endif /* __ASM_ARCH_6400_MAP_H */

2
arch/arm/mach-s3c64xx/irq-pm.c
View File

@ -22,7 +22,6 @@
#include <mach/map.h>
#include <plat/regs-serial.h>
#include <plat/regs-timer.h>
#include <mach/regs-gpio.h>
#include <plat/cpu.h>
#include <plat/pm.h>
@ -43,7 +42,6 @@ static struct sleep_save irq_save[] = {
SAVE_ITEM(S3C64XX_EINT0FLTCON2),
SAVE_ITEM(S3C64XX_EINT0FLTCON3),
SAVE_ITEM(S3C64XX_EINT0MASK),
SAVE_ITEM(S3C64XX_TINT_CSTAT),
};
static struct irq_grp_save {

6
arch/arm/mach-s3c64xx/mach-crag6410.c
View File

@ -30,7 +30,7 @@
#include <linux/basic_mmio_gpio.h>
#include <linux/spi/spi.h>
#include <linux/i2c/pca953x.h>
#include <linux/platform_data/pca953x.h>
#include <linux/platform_data/s3c-hsotg.h>
#include <video/platform_lcd.h>
@ -120,7 +120,7 @@ static struct platform_device crag6410_backlight_device = {
.name = "pwm-backlight",
.id = -1,
.dev = {
.parent = &s3c_device_timer[0].dev,
.parent = &samsung_device_pwm.dev,
.platform_data = &crag6410_backlight_data,
},
};
@ -375,7 +375,7 @@ static struct platform_device *crag6410_devices[] __initdata = {
&s3c_device_fb,
&s3c_device_ohci,
&s3c_device_usb_hsotg,
&s3c_device_timer[0],
&samsung_device_pwm,
&s3c64xx_device_iis0,
&s3c64xx_device_iis1,
&samsung_device_keypad,

4
arch/arm/mach-s3c64xx/mach-hmt.c
View File

@ -123,7 +123,7 @@ static struct platform_pwm_backlight_data hmt_backlight_data = {
static struct platform_device hmt_backlight_device = {
.name = "pwm-backlight",
.dev = {
.parent = &s3c_device_timer[1].dev,
.parent = &samsung_device_pwm.dev,
.platform_data = &hmt_backlight_data,
},
};
@ -239,7 +239,7 @@ static struct platform_device *hmt_devices[] __initdata = {
&s3c_device_nand,
&s3c_device_fb,
&s3c_device_ohci,
&s3c_device_timer[1],
&samsung_device_pwm,
&hmt_backlight_device,
&hmt_leds_device,
};

4
arch/arm/mach-s3c64xx/mach-smartq.c
View File

@ -157,7 +157,7 @@ static struct platform_pwm_backlight_data smartq_backlight_data = {
static struct platform_device smartq_backlight_device = {
.name = "pwm-backlight",
.dev = {
.parent = &s3c_device_timer[1].dev,
.parent = &samsung_device_pwm.dev,
.platform_data = &smartq_backlight_data,
},
};
@ -246,7 +246,7 @@ static struct platform_device *smartq_devices[] __initdata = {
&s3c_device_i2c0,
&s3c_device_ohci,
&s3c_device_rtc,
&s3c_device_timer[1],
&samsung_device_pwm,
&s3c_device_ts,
&s3c_device_usb_hsotg,
&s3c64xx_device_iis0,

5
arch/arm/mach-s3c64xx/mach-smdk6410.c
View File

@ -274,6 +274,7 @@ static struct platform_device *smdk6410_devices[] __initdata = {
&s3c_device_i2c1,
&s3c_device_fb,
&s3c_device_ohci,
&samsung_device_pwm,
&s3c_device_usb_hsotg,
&s3c64xx_device_iisv4,
&samsung_device_keypad,
@ -691,9 +692,9 @@ static void __init smdk6410_machine_init(void)
s3c_ide_set_platdata(&smdk6410_ide_pdata);
samsung_bl_set(&smdk6410_bl_gpio_info, &smdk6410_bl_data);
platform_add_devices(smdk6410_devices, ARRAY_SIZE(smdk6410_devices));
samsung_bl_set(&smdk6410_bl_gpio_info, &smdk6410_bl_data);
}
MACHINE_START(SMDK6410, "SMDK6410")

2
arch/arm/mach-s5p64x0/Kconfig
View File

@ -11,14 +11,12 @@ config CPU_S5P6440
bool
select S5P_SLEEP if PM
select SAMSUNG_DMADEV
select SAMSUNG_HRT
select SAMSUNG_WAKEMASK if PM
help
Enable S5P6440 CPU support
config CPU_S5P6450
bool
select SAMSUNG_HRT
select S5P_SLEEP if PM
select SAMSUNG_DMADEV
select SAMSUNG_WAKEMASK if PM

2
arch/arm/mach-s5p64x0/clock-s5p6440.c
View File

@ -629,6 +629,4 @@ void __init s5p6440_register_clocks(void)
clkdev_add_table(s5p6440_clk_lookup, ARRAY_SIZE(s5p6440_clk_lookup));
s3c24xx_register_clock(&dummy_apb_pclk);
s3c_pwmclk_init();
}

2
arch/arm/mach-s5p64x0/clock-s5p6450.c
View File

@ -698,6 +698,4 @@ void __init s5p6450_register_clocks(void)
clkdev_add_table(s5p6450_clk_lookup, ARRAY_SIZE(s5p6450_clk_lookup));
s3c24xx_register_clock(&dummy_apb_pclk);
s3c_pwmclk_init();
}

27
arch/arm/mach-s5p64x0/common.c
View File

@ -19,6 +19,7 @@
#include <linux/io.h>
#include <linux/device.h>
#include <linux/serial_core.h>
#include <clocksource/samsung_pwm.h>
#include <linux/platform_device.h>
#include <linux/sched.h>
#include <linux/dma-mapping.h>
@ -47,6 +48,7 @@
#include <plat/fb-core.h>
#include <plat/spi-core.h>
#include <plat/gpio-cfg.h>
#include <plat/pwm-core.h>
#include <plat/regs-irqtype.h>
#include <plat/regs-serial.h>
#include <plat/watchdog-reset.h>
@ -157,6 +159,30 @@ static void s5p64x0_idle(void)
cpu_do_idle();
}
static struct samsung_pwm_variant s5p64x0_pwm_variant = {
.bits = 32,
.div_base = 0,
.has_tint_cstat = true,
.tclk_mask = 0,
};
void __init samsung_set_timer_source(unsigned int event, unsigned int source)
{
s5p64x0_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
s5p64x0_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
}
void __init samsung_timer_init(void)
{
unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
IRQ_TIMER3_VIC, IRQ_TIMER4_VIC,
};
samsung_pwm_clocksource_init(S3C_VA_TIMER,
timer_irqs, &s5p64x0_pwm_variant);
}
/*
* s5p64x0_map_io
*
@ -176,6 +202,7 @@ void __init s5p64x0_init_io(struct map_desc *mach_desc, int size)
s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
samsung_wdt_reset_init(S3C_VA_WATCHDOG);
samsung_pwm_set_platdata(&s5p64x0_pwm_variant);
}
void __init s5p6440_map_io(void)

2
arch/arm/mach-s5p64x0/include/mach/irqs.h
View File

@ -141,8 +141,6 @@
#define IRQ_EINT_GROUP(grp, x) (IRQ_EINT_GROUP##grp##_BASE + (x))
#define IRQ_TIMER_BASE (11)
/* Set the default NR_IRQS */
#define NR_IRQS (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR + 1)

1
arch/arm/mach-s5p64x0/include/mach/map.h
View File

@ -76,6 +76,7 @@
#define S5P_PA_TIMER S5P64X0_PA_TIMER
#define SAMSUNG_PA_ADC S5P64X0_PA_ADC
#define SAMSUNG_PA_TIMER S5P64X0_PA_TIMER
/* UART */

5
arch/arm/mach-s5p64x0/mach-smdk6440.c
View File

@ -162,6 +162,7 @@ static struct platform_device *smdk6440_devices[] __initdata = {
&s3c_device_rtc,
&s3c_device_i2c0,
&s3c_device_i2c1,
&samsung_device_pwm,
&s3c_device_ts,
&s3c_device_wdt,
&s5p6440_device_iis,
@ -254,8 +255,6 @@ static void __init smdk6440_machine_init(void)
i2c_register_board_info(1, smdk6440_i2c_devs1,
ARRAY_SIZE(smdk6440_i2c_devs1));
samsung_bl_set(&smdk6440_bl_gpio_info, &smdk6440_bl_data);
s5p6440_set_lcd_interface();
s3c_fb_set_platdata(&smdk6440_lcd_pdata);
@ -264,6 +263,8 @@ static void __init smdk6440_machine_init(void)
s3c_sdhci2_set_platdata(&smdk6440_hsmmc2_pdata);
platform_add_devices(smdk6440_devices, ARRAY_SIZE(smdk6440_devices));
samsung_bl_set(&smdk6440_bl_gpio_info, &smdk6440_bl_data);
}
MACHINE_START(SMDK6440, "SMDK6440")

5
arch/arm/mach-s5p64x0/mach-smdk6450.c
View File

@ -180,6 +180,7 @@ static struct platform_device *smdk6450_devices[] __initdata = {
&s3c_device_rtc,
&s3c_device_i2c0,
&s3c_device_i2c1,
&samsung_device_pwm,
&s3c_device_ts,
&s3c_device_wdt,
&s5p6450_device_iis0,
@ -273,8 +274,6 @@ static void __init smdk6450_machine_init(void)
i2c_register_board_info(1, smdk6450_i2c_devs1,
ARRAY_SIZE(smdk6450_i2c_devs1));
samsung_bl_set(&smdk6450_bl_gpio_info, &smdk6450_bl_data);
s5p6450_set_lcd_interface();
s3c_fb_set_platdata(&smdk6450_lcd_pdata);
@ -283,6 +282,8 @@ static void __init smdk6450_machine_init(void)
s3c_sdhci2_set_platdata(&smdk6450_hsmmc2_pdata);
platform_add_devices(smdk6450_devices, ARRAY_SIZE(smdk6450_devices));
samsung_bl_set(&smdk6450_bl_gpio_info, &smdk6450_bl_data);
}
MACHINE_START(SMDK6450, "SMDK6450")

3
arch/arm/mach-s5p64x0/pm.c
View File

@ -18,7 +18,6 @@
#include <plat/cpu.h>
#include <plat/pm.h>
#include <plat/regs-timer.h>
#include <plat/wakeup-mask.h>
#include <mach/regs-clock.h>
@ -48,8 +47,6 @@ static struct sleep_save s5p64x0_misc_save[] = {
SAVE_ITEM(S5P64X0_MEM0CONSLP1),
SAVE_ITEM(S5P64X0_MEM0DRVCON),
SAVE_ITEM(S5P64X0_MEM1DRVCON),
SAVE_ITEM(S3C64XX_TINT_CSTAT),
};
/* DPLL is present only in S5P6450 */

1
arch/arm/mach-s5pc100/Kconfig
View File

@ -11,7 +11,6 @@ config CPU_S5PC100
bool
select S5P_EXT_INT
select SAMSUNG_DMADEV
select SAMSUNG_HRT
help
Enable S5PC100 CPU support

2
arch/arm/mach-s5pc100/clock.c
View File

@ -1358,6 +1358,4 @@ void __init s5pc100_register_clocks(void)
s3c_disable_clocks(clk_cdev[ptr], 1);
s3c24xx_register_clock(&dummy_apb_pclk);
s3c_pwmclk_init();
}

28
arch/arm/mach-s5pc100/common.c
View File

@ -22,6 +22,7 @@
#include <linux/io.h>
#include <linux/device.h>
#include <linux/serial_core.h>
#include <clocksource/samsung_pwm.h>
#include <linux/platform_device.h>
#include <linux/sched.h>
#include <linux/reboot.h>
@ -46,6 +47,7 @@
#include <plat/fb-core.h>
#include <plat/iic-core.h>
#include <plat/onenand-core.h>
#include <plat/pwm-core.h>
#include <plat/spi-core.h>
#include <plat/regs-serial.h>
#include <plat/watchdog-reset.h>
@ -132,6 +134,30 @@ static struct map_desc s5pc100_iodesc[] __initdata = {
}
};
static struct samsung_pwm_variant s5pc100_pwm_variant = {
.bits = 32,
.div_base = 0,
.has_tint_cstat = true,
.tclk_mask = (1 << 5),
};
void __init samsung_set_timer_source(unsigned int event, unsigned int source)
{
s5pc100_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
s5pc100_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
}
void __init samsung_timer_init(void)
{
unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
IRQ_TIMER3_VIC, IRQ_TIMER4_VIC,
};
samsung_pwm_clocksource_init(S3C_VA_TIMER,
timer_irqs, &s5pc100_pwm_variant);
}
/*
* s5pc100_map_io
*
@ -149,6 +175,8 @@ void __init s5pc100_init_io(struct map_desc *mach_desc, int size)
s5p_init_cpu(S5P_VA_CHIPID);
s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
samsung_pwm_set_platdata(&s5pc100_pwm_variant);
}
void __init s5pc100_map_io(void)

2
arch/arm/mach-s5pc100/include/mach/irqs.h
View File

@ -97,8 +97,6 @@
#define IRQ_SDMFIQ S5P_IRQ_VIC2(31)
#define IRQ_VIC_END S5P_IRQ_VIC2(31)
#define IRQ_TIMER_BASE (11)
#define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0))
#define S5P_EINT_BASE2 (IRQ_VIC_END + 1)

1
arch/arm/mach-s5pc100/include/mach/map.h
View File

@ -116,6 +116,7 @@
#define SAMSUNG_PA_ADC S5PC100_PA_TSADC
#define SAMSUNG_PA_CFCON S5PC100_PA_CFCON
#define SAMSUNG_PA_KEYPAD S5PC100_PA_KEYPAD
#define SAMSUNG_PA_TIMER S5PC100_PA_TIMER
#define S5PC100_VA_OTHERS (S3C_VA_SYS + 0x10000)

5
arch/arm/mach-s5pc100/mach-smdkc100.c
View File

@ -194,6 +194,7 @@ static struct platform_device *smdkc100_devices[] __initdata = {
&s3c_device_hsmmc0,
&s3c_device_hsmmc1,
&s3c_device_hsmmc2,
&samsung_device_pwm,
&s3c_device_ts,
&s3c_device_wdt,
&smdkc100_lcd_powerdev,
@ -246,9 +247,9 @@ static void __init smdkc100_machine_init(void)
gpio_request(S5PC100_GPH0(6), "GPH0");
smdkc100_lcd_power_set(&smdkc100_lcd_power_data, 0);
samsung_bl_set(&smdkc100_bl_gpio_info, &smdkc100_bl_data);
platform_add_devices(smdkc100_devices, ARRAY_SIZE(smdkc100_devices));
samsung_bl_set(&smdkc100_bl_gpio_info, &smdkc100_bl_data);
}
MACHINE_START(SMDKC100, "SMDKC100")

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