Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 fixes from Peter Anvin: "This is a collection of minor fixes for x86, plus the IRET information leak fix (forbid the use of 16-bit segments in 64-bit mode)" NOTE! We may have to relax the "forbid the use of 16-bit segments in 64-bit mode" part, since there may be people who still run and depend on 16-bit Windows binaries under Wine. But I'm taking this in the current unconditional form for now to see who (if anybody) screams bloody murder. Maybe nobody cares. And maybe we'll have to update it with some kind of runtime enablement (like our vm.mmap_min_addr tunable that people who run dosemu/qemu/wine already need to tweak). * 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86-64, modify_ldt: Ban 16-bit segments on 64-bit kernels efi: Pass correct file handle to efi_file_{read,close} x86/efi: Correct EFI boot stub use of code32_start x86/efi: Fix boot failure with EFI stub x86/platform/hyperv: Handle VMBUS driver being a module x86/apic: Reinstate error IRQ Pentium erratum 3AP workaround x86, CMCI: Add proper detection of end of CMCI storms
This commit is contained in:
commit
8eab6cd031
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@ -112,7 +112,7 @@ __file_size64(void *__fh, efi_char16_t *filename_16,
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efi_file_info_t *info;
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efi_status_t status;
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efi_guid_t info_guid = EFI_FILE_INFO_ID;
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u32 info_sz;
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u64 info_sz;
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status = efi_early->call((unsigned long)fh->open, fh, &h, filename_16,
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EFI_FILE_MODE_READ, (u64)0);
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@ -167,31 +167,31 @@ efi_file_size(efi_system_table_t *sys_table, void *__fh,
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}
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static inline efi_status_t
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efi_file_read(void *__fh, void *handle, unsigned long *size, void *addr)
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efi_file_read(void *handle, unsigned long *size, void *addr)
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{
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unsigned long func;
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if (efi_early->is64) {
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efi_file_handle_64_t *fh = __fh;
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efi_file_handle_64_t *fh = handle;
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func = (unsigned long)fh->read;
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return efi_early->call(func, handle, size, addr);
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} else {
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efi_file_handle_32_t *fh = __fh;
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efi_file_handle_32_t *fh = handle;
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func = (unsigned long)fh->read;
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return efi_early->call(func, handle, size, addr);
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}
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}
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static inline efi_status_t efi_file_close(void *__fh, void *handle)
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static inline efi_status_t efi_file_close(void *handle)
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{
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if (efi_early->is64) {
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efi_file_handle_64_t *fh = __fh;
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efi_file_handle_64_t *fh = handle;
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return efi_early->call((unsigned long)fh->close, handle);
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} else {
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efi_file_handle_32_t *fh = __fh;
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efi_file_handle_32_t *fh = handle;
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return efi_early->call((unsigned long)fh->close, handle);
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}
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@ -1016,6 +1016,9 @@ void setup_graphics(struct boot_params *boot_params)
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* Because the x86 boot code expects to be passed a boot_params we
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* need to create one ourselves (usually the bootloader would create
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* one for us).
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*
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* The caller is responsible for filling out ->code32_start in the
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* returned boot_params.
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*/
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struct boot_params *make_boot_params(struct efi_config *c)
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{
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@ -1081,8 +1084,6 @@ struct boot_params *make_boot_params(struct efi_config *c)
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hdr->vid_mode = 0xffff;
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hdr->boot_flag = 0xAA55;
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hdr->code32_start = (__u64)(unsigned long)image->image_base;
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hdr->type_of_loader = 0x21;
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/* Convert unicode cmdline to ascii */
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@ -59,6 +59,7 @@ ENTRY(efi_pe_entry)
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call make_boot_params
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cmpl $0, %eax
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je fail
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movl %esi, BP_code32_start(%eax)
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popl %ecx
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pushl %eax
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pushl %ecx
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@ -90,12 +91,7 @@ fail:
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hlt
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jmp fail
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2:
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call 3f
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3:
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popl %eax
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subl $3b, %eax
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subl BP_pref_address(%esi), %eax
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add BP_code32_start(%esi), %eax
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movl BP_code32_start(%esi), %eax
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leal preferred_addr(%eax), %eax
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jmp *%eax
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@ -261,6 +261,8 @@ ENTRY(efi_pe_entry)
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cmpq $0,%rax
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je fail
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mov %rax, %rsi
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leaq startup_32(%rip), %rax
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movl %eax, BP_code32_start(%rsi)
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jmp 2f /* Skip the relocation */
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handover_entry:
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@ -284,12 +286,7 @@ fail:
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hlt
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jmp fail
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2:
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call 3f
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3:
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popq %rax
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subq $3b, %rax
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subq BP_pref_address(%rsi), %rax
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add BP_code32_start(%esi), %eax
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movl BP_code32_start(%esi), %eax
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leaq preferred_addr(%rax), %rax
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jmp *%rax
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@ -1996,7 +1996,8 @@ static inline void __smp_error_interrupt(struct pt_regs *regs)
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};
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/* First tickle the hardware, only then report what went on. -- REW */
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apic_write(APIC_ESR, 0);
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if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */
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apic_write(APIC_ESR, 0);
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v = apic_read(APIC_ESR);
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ack_APIC_irq();
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atomic_inc(&irq_err_count);
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@ -89,6 +89,9 @@ static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait);
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static DEFINE_PER_CPU(struct mce, mces_seen);
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static int cpu_missing;
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/* CMCI storm detection filter */
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static DEFINE_PER_CPU(unsigned long, mce_polled_error);
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/*
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* MCA banks polled by the period polling timer for corrected events.
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* With Intel CMCI, this only has MCA banks which do not support CMCI (if any).
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@ -595,6 +598,7 @@ void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
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{
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struct mce m;
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int i;
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unsigned long *v;
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this_cpu_inc(mce_poll_count);
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@ -614,6 +618,8 @@ void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
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if (!(m.status & MCI_STATUS_VAL))
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continue;
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v = &get_cpu_var(mce_polled_error);
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set_bit(0, v);
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/*
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* Uncorrected or signalled events are handled by the exception
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* handler when it is enabled, so don't process those here.
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static unsigned long (*mce_adjust_timer)(unsigned long interval) =
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mce_adjust_timer_default;
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static int cmc_error_seen(void)
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{
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unsigned long *v = &__get_cpu_var(mce_polled_error);
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return test_and_clear_bit(0, v);
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}
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static void mce_timer_fn(unsigned long data)
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{
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struct timer_list *t = &__get_cpu_var(mce_timer);
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unsigned long iv;
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int notify;
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WARN_ON(smp_processor_id() != data);
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* polling interval, otherwise increase the polling interval.
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*/
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iv = __this_cpu_read(mce_next_interval);
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if (mce_notify_irq()) {
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notify = mce_notify_irq();
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notify |= cmc_error_seen();
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if (notify) {
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iv = max(iv / 2, (unsigned long) HZ/100);
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} else {
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iv = min(iv * 2, round_jiffies_relative(check_interval * HZ));
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@ -9,6 +9,7 @@
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#include <linux/interrupt.h>
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#include <linux/percpu.h>
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#include <linux/sched.h>
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#include <linux/cpumask.h>
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#include <asm/apic.h>
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#include <asm/processor.h>
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#include <asm/msr.h>
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}
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}
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static void cmci_storm_disable_banks(void)
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{
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unsigned long flags, *owned;
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int bank;
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u64 val;
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raw_spin_lock_irqsave(&cmci_discover_lock, flags);
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owned = __get_cpu_var(mce_banks_owned);
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for_each_set_bit(bank, owned, MAX_NR_BANKS) {
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rdmsrl(MSR_IA32_MCx_CTL2(bank), val);
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val &= ~MCI_CTL2_CMCI_EN;
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wrmsrl(MSR_IA32_MCx_CTL2(bank), val);
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}
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raw_spin_unlock_irqrestore(&cmci_discover_lock, flags);
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}
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static bool cmci_storm_detect(void)
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{
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unsigned int cnt = __this_cpu_read(cmci_storm_cnt);
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if (cnt <= CMCI_STORM_THRESHOLD)
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return false;
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cmci_clear();
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cmci_storm_disable_banks();
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__this_cpu_write(cmci_storm_state, CMCI_STORM_ACTIVE);
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r = atomic_add_return(1, &cmci_storm_on_cpus);
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mce_timer_kick(CMCI_POLL_INTERVAL);
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@ -125,7 +125,7 @@ int arch_show_interrupts(struct seq_file *p, int prec)
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seq_printf(p, "%10u ", per_cpu(mce_poll_count, j));
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seq_printf(p, " Machine check polls\n");
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#endif
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#if defined(CONFIG_HYPERV) || defined(CONFIG_XEN)
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#if IS_ENABLED(CONFIG_HYPERV) || defined(CONFIG_XEN)
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seq_printf(p, "%*s: ", prec, "THR");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", irq_stats(j)->irq_hv_callback_count);
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@ -229,6 +229,17 @@ static int write_ldt(void __user *ptr, unsigned long bytecount, int oldmode)
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}
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}
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/*
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* On x86-64 we do not support 16-bit segments due to
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* IRET leaking the high bits of the kernel stack address.
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*/
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#ifdef CONFIG_X86_64
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if (!ldt_info.seg_32bit) {
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error = -EINVAL;
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goto out_unlock;
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}
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#endif
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fill_ldt(&ldt, &ldt_info);
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if (oldmode)
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ldt.avl = 0;
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@ -397,7 +397,7 @@ static efi_status_t handle_cmdline_files(efi_system_table_t *sys_table_arg,
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else
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chunksize = size;
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status = efi_file_read(fh, files[j].handle,
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status = efi_file_read(files[j].handle,
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&chunksize,
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(void *)addr);
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if (status != EFI_SUCCESS) {
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size -= chunksize;
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}
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efi_file_close(fh, files[j].handle);
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efi_file_close(files[j].handle);
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}
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}
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close_handles:
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for (k = j; k < i; k++)
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efi_file_close(fh, files[k].handle);
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efi_file_close(files[k].handle);
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free_files:
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efi_call_early(free_pool, files);
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fail:
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