[PATCH] skge: spelling fixes
Fix some of my bad spelling. Signed-off-by: Stephen Hemminger <shemminger@osdl.org> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
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1631aef151
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@ -130,7 +130,7 @@ static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
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regs->len - B3_RI_WTO_R1);
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regs->len - B3_RI_WTO_R1);
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}
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}
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/* Wake on Lan only supported on Yukon chps with rev 1 or above */
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/* Wake on Lan only supported on Yukon chips with rev 1 or above */
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static int wol_supported(const struct skge_hw *hw)
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static int wol_supported(const struct skge_hw *hw)
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{
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{
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return !((hw->chip_id == CHIP_ID_GENESIS ||
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return !((hw->chip_id == CHIP_ID_GENESIS ||
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@ -170,8 +170,8 @@ static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
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return 0;
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return 0;
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}
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}
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/* Determine supported/adverised modes based on hardware.
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/* Determine supported/advertised modes based on hardware.
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* Note: ethtoool ADVERTISED_xxx == SUPPORTED_xxx
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* Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
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*/
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*/
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static u32 skge_supported_modes(const struct skge_hw *hw)
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static u32 skge_supported_modes(const struct skge_hw *hw)
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{
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{
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@ -532,13 +532,13 @@ static inline u32 hwkhz(const struct skge_hw *hw)
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return 78215; /* or: 78.125 MHz */
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return 78215; /* or: 78.125 MHz */
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}
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}
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/* Chip hz to microseconds */
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/* Chip HZ to microseconds */
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static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
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static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
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{
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{
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return (ticks * 1000) / hwkhz(hw);
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return (ticks * 1000) / hwkhz(hw);
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}
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}
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/* Microseconds to chip hz */
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/* Microseconds to chip HZ */
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static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
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static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
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{
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{
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return hwkhz(hw) * usec / 1000;
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return hwkhz(hw) * usec / 1000;
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@ -1163,7 +1163,7 @@ static void bcom_phy_init(struct skge_port *skge, int jumbo)
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xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
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xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
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xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
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xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
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/* Use link status change interrrupt */
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/* Use link status change interrupt */
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xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
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xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
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bcom_check_link(hw, port);
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bcom_check_link(hw, port);
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@ -1203,7 +1203,7 @@ static void genesis_mac_init(struct skge_hw *hw, int port)
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skge_write32(hw, B2_GP_IO, r);
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skge_write32(hw, B2_GP_IO, r);
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skge_read32(hw, B2_GP_IO);
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skge_read32(hw, B2_GP_IO);
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/* Enable GMII interfac */
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/* Enable GMII interface */
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xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
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xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
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bcom_phy_init(skge, jumbo);
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bcom_phy_init(skge, jumbo);
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@ -1254,7 +1254,7 @@ static void genesis_mac_init(struct skge_hw *hw, int port)
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* that jumbo frames larger than 8192 bytes will be
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* that jumbo frames larger than 8192 bytes will be
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* truncated. Disabling all bad frame filtering causes
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* truncated. Disabling all bad frame filtering causes
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* the RX FIFO to operate in streaming mode, in which
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* the RX FIFO to operate in streaming mode, in which
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* case the XMAC will start transfering frames out of the
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* case the XMAC will start transferring frames out of the
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* RX FIFO as soon as the FIFO threshold is reached.
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* RX FIFO as soon as the FIFO threshold is reached.
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*/
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*/
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xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
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xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
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@ -1321,7 +1321,7 @@ static void genesis_stop(struct skge_port *skge)
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port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
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port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
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/*
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/*
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* If the transfer stucks at the MAC the STOP command will not
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* If the transfer sticks at the MAC the STOP command will not
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* terminate if we don't flush the XMAC's transmit FIFO !
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* terminate if we don't flush the XMAC's transmit FIFO !
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*/
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*/
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xm_write32(hw, port, XM_MODE,
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xm_write32(hw, port, XM_MODE,
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@ -1559,7 +1559,7 @@ static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
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return v;
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return v;
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}
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}
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/* Marvell Phy Initailization */
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/* Marvell Phy Initialization */
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static void yukon_init(struct skge_hw *hw, int port)
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static void yukon_init(struct skge_hw *hw, int port)
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{
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{
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struct skge_port *skge = netdev_priv(hw->dev[port]);
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struct skge_port *skge = netdev_priv(hw->dev[port]);
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@ -2156,7 +2156,7 @@ static int skge_up(struct net_device *dev)
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hw->intr_mask |= portirqmask[port];
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hw->intr_mask |= portirqmask[port];
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skge_write32(hw, B0_IMSK, hw->intr_mask);
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skge_write32(hw, B0_IMSK, hw->intr_mask);
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/* Initialze MAC */
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/* Initialize MAC */
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spin_lock_bh(&hw->phy_lock);
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spin_lock_bh(&hw->phy_lock);
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if (hw->chip_id == CHIP_ID_GENESIS)
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if (hw->chip_id == CHIP_ID_GENESIS)
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genesis_mac_init(hw, port);
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genesis_mac_init(hw, port);
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@ -2476,7 +2476,7 @@ static void yukon_set_multicast(struct net_device *dev)
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reg = gma_read16(hw, port, GM_RX_CTRL);
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reg = gma_read16(hw, port, GM_RX_CTRL);
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reg |= GM_RXCR_UCF_ENA;
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reg |= GM_RXCR_UCF_ENA;
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if (dev->flags & IFF_PROMISC) /* promiscious */
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if (dev->flags & IFF_PROMISC) /* promiscuous */
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reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
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reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
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else if (dev->flags & IFF_ALLMULTI) /* all multicast */
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else if (dev->flags & IFF_ALLMULTI) /* all multicast */
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memset(filter, 0xff, sizeof(filter));
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memset(filter, 0xff, sizeof(filter));
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@ -2799,7 +2799,7 @@ static void skge_error_irq(struct skge_hw *hw)
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}
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}
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/*
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/*
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* Interrrupt from PHY are handled in tasklet (soft irq)
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* Interrupt from PHY are handled in tasklet (soft irq)
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* because accessing phy registers requires spin wait which might
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* because accessing phy registers requires spin wait which might
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* cause excess interrupt latency.
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* cause excess interrupt latency.
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*/
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*/
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@ -3233,7 +3233,7 @@ static int __devinit skge_probe(struct pci_dev *pdev,
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}
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}
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#ifdef __BIG_ENDIAN
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#ifdef __BIG_ENDIAN
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/* byte swap decriptors in hardware */
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/* byte swap descriptors in hardware */
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{
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{
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u32 reg;
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u32 reg;
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