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Merge branch 'at91/cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc 

* 'at91/cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux-arm-soc:
  at91: add arch specific ioremap support
  at91: factorize sram init
  at91: move register clocks to soc generic init
  at91: move clock subsystem init to soc generic init
  at91: use structure to store the current soc
  at91: remove AT91_DBGU offset from dbgu register macro
  at91: factorize at91 interrupts init to soc
  at91: introduce commom AT91_BASE_SYS
This commit is contained in:
Linus Torvalds 2011-07-29 23:32:53 -07:00
parent cb7dee8d22 fb149f9e28
commit 8f57be8ee4
58 changed files with 698 additions and 747 deletions
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2
arch/arm/mach-at91/Makefile
View File

@ -2,7 +2,7 @@
# Makefile for the linux kernel.
#
obj-y := irq.o gpio.o
obj-y := irq.o gpio.o setup.o
obj-m :=
obj-n :=
obj- :=

45
arch/arm/mach-at91/at91cap9.c
View File

@ -25,23 +25,10 @@
#include <mach/at91_rstc.h>
#include <mach/at91_shdwc.h>
#include "soc.h"
#include "generic.h"
#include "clock.h"
static struct map_desc at91cap9_io_desc[] __initdata = {
{
.virtual = AT91_VA_BASE_SYS,
.pfn = __phys_to_pfn(AT91_BASE_SYS),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = AT91_IO_VIRT_BASE - AT91CAP9_SRAM_SIZE,
.pfn = __phys_to_pfn(AT91CAP9_SRAM_BASE),
.length = AT91CAP9_SRAM_SIZE,
.type = MT_DEVICE,
},
};
/* --------------------------------------------------------------------
* Clocks
* -------------------------------------------------------------------- */
@ -339,24 +326,17 @@ static void at91cap9_poweroff(void)
* AT91CAP9 processor initialization
* -------------------------------------------------------------------- */
void __init at91cap9_map_io(void)
static void __init at91cap9_map_io(void)
{
/* Map peripherals */
iotable_init(at91cap9_io_desc, ARRAY_SIZE(at91cap9_io_desc));
at91_init_sram(0, AT91CAP9_SRAM_BASE, AT91CAP9_SRAM_SIZE);
}
void __init at91cap9_initialize(unsigned long main_clock)
static void __init at91cap9_initialize(void)
{
at91_arch_reset = at91cap9_reset;
pm_power_off = at91cap9_poweroff;
at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1);
/* Init clock subsystem */
at91_clock_init(main_clock);
/* Register the processor-specific clocks */
at91cap9_register_clocks();
/* Register GPIO subsystem */
at91_gpio_init(at91cap9_gpio, 4);
@ -409,14 +389,9 @@ static unsigned int at91cap9_default_irq_priority[NR_AIC_IRQS] __initdata = {
0, /* Advanced Interrupt Controller (IRQ1) */
};
void __init at91cap9_init_interrupts(unsigned int priority[NR_AIC_IRQS])
{
if (!priority)
priority = at91cap9_default_irq_priority;
/* Initialize the AIC interrupt controller */
at91_aic_init(priority);
/* Enable GPIO interrupts */
at91_gpio_irq_setup();
}
struct at91_init_soc __initdata at91cap9_soc = {
.map_io = at91cap9_map_io,
.default_irq_priority = at91cap9_default_irq_priority,
.register_clocks = at91cap9_register_clocks,
.init = at91cap9_initialize,
};

47
arch/arm/mach-at91/at91rm9200.c
View File

@ -20,25 +20,16 @@
#include <mach/at91_st.h>
#include <mach/cpu.h>
#include "soc.h"
#include "generic.h"
#include "clock.h"
static struct map_desc at91rm9200_io_desc[] __initdata = {
{
.virtual = AT91_VA_BASE_SYS,
.pfn = __phys_to_pfn(AT91_BASE_SYS),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = AT91_VA_BASE_EMAC,
.pfn = __phys_to_pfn(AT91RM9200_BASE_EMAC),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = AT91_IO_VIRT_BASE - AT91RM9200_SRAM_SIZE,
.pfn = __phys_to_pfn(AT91RM9200_SRAM_BASE),
.length = AT91RM9200_SRAM_SIZE,
.type = MT_DEVICE,
},
};
@ -304,24 +295,17 @@ static void at91rm9200_reset(void)
at91_sys_write(AT91_ST_CR, AT91_ST_WDRST);
}
int rm9200_type;
EXPORT_SYMBOL(rm9200_type);
void __init at91rm9200_set_type(int type)
{
rm9200_type = type;
}
/* --------------------------------------------------------------------
* AT91RM9200 processor initialization
* -------------------------------------------------------------------- */
void __init at91rm9200_map_io(void)
static void __init at91rm9200_map_io(void)
{
/* Map peripherals */
at91_init_sram(0, AT91RM9200_SRAM_BASE, AT91RM9200_SRAM_SIZE);
iotable_init(at91rm9200_io_desc, ARRAY_SIZE(at91rm9200_io_desc));
}
void __init at91rm9200_initialize(unsigned long main_clock)
static void __init at91rm9200_initialize(void)
{
at91_arch_reset = at91rm9200_reset;
at91_extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1)
@ -329,12 +313,6 @@ void __init at91rm9200_initialize(unsigned long main_clock)
| (1 << AT91RM9200_ID_IRQ4) | (1 << AT91RM9200_ID_IRQ5)
| (1 << AT91RM9200_ID_IRQ6);
/* Init clock subsystem */
at91_clock_init(main_clock);
/* Register the processor-specific clocks */
at91rm9200_register_clocks();
/* Initialize GPIO subsystem */
at91_gpio_init(at91rm9200_gpio,
cpu_is_at91rm9200_bga() ? AT91RM9200_BGA : AT91RM9200_PQFP);
@ -383,14 +361,9 @@ static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = {
0 /* Advanced Interrupt Controller (IRQ6) */
};
void __init at91rm9200_init_interrupts(unsigned int priority[NR_AIC_IRQS])
{
if (!priority)
priority = at91rm9200_default_irq_priority;
/* Initialize the AIC interrupt controller */
at91_aic_init(priority);
/* Enable GPIO interrupts */
at91_gpio_irq_setup();
}
struct at91_init_soc __initdata at91rm9200_soc = {
.map_io = at91rm9200_map_io,
.default_irq_priority = at91rm9200_default_irq_priority,
.register_clocks = at91rm9200_register_clocks,
.init = at91rm9200_initialize,
};

100
arch/arm/mach-at91/at91sam9260.c
View File

@ -17,58 +17,16 @@
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/cpu.h>
#include <mach/at91_dbgu.h>
#include <mach/at91sam9260.h>
#include <mach/at91_pmc.h>
#include <mach/at91_rstc.h>
#include <mach/at91_shdwc.h>
#include "soc.h"
#include "generic.h"
#include "clock.h"
static struct map_desc at91sam9260_io_desc[] __initdata = {
{
.virtual = AT91_VA_BASE_SYS,
.pfn = __phys_to_pfn(AT91_BASE_SYS),
.length = SZ_16K,
.type = MT_DEVICE,
}
};
static struct map_desc at91sam9260_sram_desc[] __initdata = {
{
.virtual = AT91_IO_VIRT_BASE - AT91SAM9260_SRAM0_SIZE,
.pfn = __phys_to_pfn(AT91SAM9260_SRAM0_BASE),
.length = AT91SAM9260_SRAM0_SIZE,
.type = MT_DEVICE,
}, {
.virtual = AT91_IO_VIRT_BASE - AT91SAM9260_SRAM0_SIZE - AT91SAM9260_SRAM1_SIZE,
.pfn = __phys_to_pfn(AT91SAM9260_SRAM1_BASE),
.length = AT91SAM9260_SRAM1_SIZE,
.type = MT_DEVICE,
}
};
static struct map_desc at91sam9g20_sram_desc[] __initdata = {
{
.virtual = AT91_IO_VIRT_BASE - AT91SAM9G20_SRAM0_SIZE,
.pfn = __phys_to_pfn(AT91SAM9G20_SRAM0_BASE),
.length = AT91SAM9G20_SRAM0_SIZE,
.type = MT_DEVICE,
}, {
.virtual = AT91_IO_VIRT_BASE - AT91SAM9G20_SRAM0_SIZE - AT91SAM9G20_SRAM1_SIZE,
.pfn = __phys_to_pfn(AT91SAM9G20_SRAM1_BASE),
.length = AT91SAM9G20_SRAM1_SIZE,
.type = MT_DEVICE,
}
};
static struct map_desc at91sam9xe_sram_desc[] __initdata = {
{
.pfn = __phys_to_pfn(AT91SAM9XE_SRAM_BASE),
.type = MT_DEVICE,
}
};
/* --------------------------------------------------------------------
* Clocks
* -------------------------------------------------------------------- */
@ -330,11 +288,9 @@ static void at91sam9260_poweroff(void)
static void __init at91sam9xe_map_io(void)
{
unsigned long cidr, sram_size;
unsigned long sram_size;
cidr = at91_sys_read(AT91_DBGU_CIDR);
switch (cidr & AT91_CIDR_SRAMSIZ) {
switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
case AT91_CIDR_SRAMSIZ_32K:
sram_size = 2 * SZ_16K;
break;
@ -343,38 +299,29 @@ static void __init at91sam9xe_map_io(void)
sram_size = SZ_16K;
}
at91sam9xe_sram_desc->virtual = AT91_IO_VIRT_BASE - sram_size;
at91sam9xe_sram_desc->length = sram_size;
iotable_init(at91sam9xe_sram_desc, ARRAY_SIZE(at91sam9xe_sram_desc));
at91_init_sram(0, AT91SAM9XE_SRAM_BASE, sram_size);
}
void __init at91sam9260_map_io(void)
static void __init at91sam9260_map_io(void)
{
/* Map peripherals */
iotable_init(at91sam9260_io_desc, ARRAY_SIZE(at91sam9260_io_desc));
if (cpu_is_at91sam9xe())
if (cpu_is_at91sam9xe()) {
at91sam9xe_map_io();
else if (cpu_is_at91sam9g20())
iotable_init(at91sam9g20_sram_desc, ARRAY_SIZE(at91sam9g20_sram_desc));
else
iotable_init(at91sam9260_sram_desc, ARRAY_SIZE(at91sam9260_sram_desc));
} else if (cpu_is_at91sam9g20()) {
at91_init_sram(0, AT91SAM9G20_SRAM0_BASE, AT91SAM9G20_SRAM0_SIZE);
at91_init_sram(1, AT91SAM9G20_SRAM1_BASE, AT91SAM9G20_SRAM1_SIZE);
} else {
at91_init_sram(0, AT91SAM9260_SRAM0_BASE, AT91SAM9260_SRAM0_SIZE);
at91_init_sram(1, AT91SAM9260_SRAM1_BASE, AT91SAM9260_SRAM1_SIZE);
}
}
void __init at91sam9260_initialize(unsigned long main_clock)
static void __init at91sam9260_initialize(void)
{
at91_arch_reset = at91sam9_alt_reset;
pm_power_off = at91sam9260_poweroff;
at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
| (1 << AT91SAM9260_ID_IRQ2);
/* Init clock subsystem */
at91_clock_init(main_clock);
/* Register the processor-specific clocks */
at91sam9260_register_clocks();
/* Register GPIO subsystem */
at91_gpio_init(at91sam9260_gpio, 3);
}
@ -421,14 +368,9 @@ static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
0, /* Advanced Interrupt Controller */
};
void __init at91sam9260_init_interrupts(unsigned int priority[NR_AIC_IRQS])
{
if (!priority)
priority = at91sam9260_default_irq_priority;
/* Initialize the AIC interrupt controller */
at91_aic_init(priority);
/* Enable GPIO interrupts */
at91_gpio_irq_setup();
}
struct at91_init_soc __initdata at91sam9260_soc = {
.map_io = at91sam9260_map_io,
.default_irq_priority = at91sam9260_default_irq_priority,
.register_clocks = at91sam9260_register_clocks,
.init = at91sam9260_initialize,
};

62
arch/arm/mach-at91/at91sam9261.c
View File

@ -22,36 +22,10 @@
#include <mach/at91_rstc.h>
#include <mach/at91_shdwc.h>
#include "soc.h"
#include "generic.h"
#include "clock.h"
static struct map_desc at91sam9261_io_desc[] __initdata = {
{
.virtual = AT91_VA_BASE_SYS,
.pfn = __phys_to_pfn(AT91_BASE_SYS),
.length = SZ_16K,
.type = MT_DEVICE,
},
};
static struct map_desc at91sam9261_sram_desc[] __initdata = {
{
.virtual = AT91_IO_VIRT_BASE - AT91SAM9261_SRAM_SIZE,
.pfn = __phys_to_pfn(AT91SAM9261_SRAM_BASE),
.length = AT91SAM9261_SRAM_SIZE,
.type = MT_DEVICE,
},
};
static struct map_desc at91sam9g10_sram_desc[] __initdata = {
{
.virtual = AT91_IO_VIRT_BASE - AT91SAM9G10_SRAM_SIZE,
.pfn = __phys_to_pfn(AT91SAM9G10_SRAM_BASE),
.length = AT91SAM9G10_SRAM_SIZE,
.type = MT_DEVICE,
},
};
/* --------------------------------------------------------------------
* Clocks
* -------------------------------------------------------------------- */
@ -302,30 +276,21 @@ static void at91sam9261_poweroff(void)
* AT91SAM9261 processor initialization
* -------------------------------------------------------------------- */
void __init at91sam9261_map_io(void)
static void __init at91sam9261_map_io(void)
{
/* Map peripherals */
iotable_init(at91sam9261_io_desc, ARRAY_SIZE(at91sam9261_io_desc));
if (cpu_is_at91sam9g10())
iotable_init(at91sam9g10_sram_desc, ARRAY_SIZE(at91sam9g10_sram_desc));
at91_init_sram(0, AT91SAM9G10_SRAM_BASE, AT91SAM9G10_SRAM_SIZE);
else
iotable_init(at91sam9261_sram_desc, ARRAY_SIZE(at91sam9261_sram_desc));
at91_init_sram(0, AT91SAM9261_SRAM_BASE, AT91SAM9261_SRAM_SIZE);
}
void __init at91sam9261_initialize(unsigned long main_clock)
static void __init at91sam9261_initialize(void)
{
at91_arch_reset = at91sam9_alt_reset;
pm_power_off = at91sam9261_poweroff;
at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
| (1 << AT91SAM9261_ID_IRQ2);
/* Init clock subsystem */
at91_clock_init(main_clock);
/* Register the processor-specific clocks */
at91sam9261_register_clocks();
/* Register GPIO subsystem */
at91_gpio_init(at91sam9261_gpio, 3);
}
@ -372,14 +337,9 @@ static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = {
0, /* Advanced Interrupt Controller */
};
void __init at91sam9261_init_interrupts(unsigned int priority[NR_AIC_IRQS])
{
if (!priority)
priority = at91sam9261_default_irq_priority;
/* Initialize the AIC interrupt controller */
at91_aic_init(priority);
/* Enable GPIO interrupts */
at91_gpio_irq_setup();
}
struct at91_init_soc __initdata at91sam9261_soc = {
.map_io = at91sam9261_map_io,
.default_irq_priority = at91sam9261_default_irq_priority,
.register_clocks = at91sam9261_register_clocks,
.init = at91sam9261_initialize,
};

51
arch/arm/mach-at91/at91sam9263.c
View File

@ -21,28 +21,10 @@
#include <mach/at91_rstc.h>
#include <mach/at91_shdwc.h>
#include "soc.h"
#include "generic.h"
#include "clock.h"
static struct map_desc at91sam9263_io_desc[] __initdata = {
{
.virtual = AT91_VA_BASE_SYS,
.pfn = __phys_to_pfn(AT91_BASE_SYS),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = AT91_IO_VIRT_BASE - AT91SAM9263_SRAM0_SIZE,
.pfn = __phys_to_pfn(AT91SAM9263_SRAM0_BASE),
.length = AT91SAM9263_SRAM0_SIZE,
.type = MT_DEVICE,
}, {
.virtual = AT91_IO_VIRT_BASE - AT91SAM9263_SRAM0_SIZE - AT91SAM9263_SRAM1_SIZE,
.pfn = __phys_to_pfn(AT91SAM9263_SRAM1_BASE),
.length = AT91SAM9263_SRAM1_SIZE,
.type = MT_DEVICE,
},
};
/* --------------------------------------------------------------------
* Clocks
* -------------------------------------------------------------------- */
@ -313,24 +295,18 @@ static void at91sam9263_poweroff(void)
* AT91SAM9263 processor initialization
* -------------------------------------------------------------------- */
void __init at91sam9263_map_io(void)
static void __init at91sam9263_map_io(void)
{
/* Map peripherals */
iotable_init(at91sam9263_io_desc, ARRAY_SIZE(at91sam9263_io_desc));
at91_init_sram(0, AT91SAM9263_SRAM0_BASE, AT91SAM9263_SRAM0_SIZE);
at91_init_sram(1, AT91SAM9263_SRAM1_BASE, AT91SAM9263_SRAM1_SIZE);
}
void __init at91sam9263_initialize(unsigned long main_clock)
static void __init at91sam9263_initialize(void)
{
at91_arch_reset = at91sam9_alt_reset;
pm_power_off = at91sam9263_poweroff;
at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1);
/* Init clock subsystem */
at91_clock_init(main_clock);
/* Register the processor-specific clocks */
at91sam9263_register_clocks();
/* Register GPIO subsystem */
at91_gpio_init(at91sam9263_gpio, 5);
}
@ -377,14 +353,9 @@ static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = {
0, /* Advanced Interrupt Controller (IRQ1) */
};
void __init at91sam9263_init_interrupts(unsigned int priority[NR_AIC_IRQS])
{
if (!priority)
priority = at91sam9263_default_irq_priority;
/* Initialize the AIC interrupt controller */
at91_aic_init(priority);
/* Enable GPIO interrupts */
at91_gpio_irq_setup();
}
struct at91_init_soc __initdata at91sam9263_soc = {
.map_io = at91sam9263_map_io,
.default_irq_priority = at91sam9263_default_irq_priority,
.register_clocks = at91sam9263_register_clocks,
.init = at91sam9263_initialize,
};

45
arch/arm/mach-at91/at91sam9g45.c
View File

@ -22,23 +22,10 @@
#include <mach/at91_shdwc.h>
#include <mach/cpu.h>
#include "soc.h"
#include "generic.h"
#include "clock.h"
static struct map_desc at91sam9g45_io_desc[] __initdata = {
{
.virtual = AT91_VA_BASE_SYS,
.pfn = __phys_to_pfn(AT91_BASE_SYS),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = AT91_IO_VIRT_BASE - AT91SAM9G45_SRAM_SIZE,
.pfn = __phys_to_pfn(AT91SAM9G45_SRAM_BASE),
.length = AT91SAM9G45_SRAM_SIZE,
.type = MT_DEVICE,
}
};
/* --------------------------------------------------------------------
* Clocks
* -------------------------------------------------------------------- */
@ -329,24 +316,17 @@ static void at91sam9g45_poweroff(void)
* AT91SAM9G45 processor initialization
* -------------------------------------------------------------------- */
void __init at91sam9g45_map_io(void)
static void __init at91sam9g45_map_io(void)
{
/* Map peripherals */
iotable_init(at91sam9g45_io_desc, ARRAY_SIZE(at91sam9g45_io_desc));
at91_init_sram(0, AT91SAM9G45_SRAM_BASE, AT91SAM9G45_SRAM_SIZE);
}
void __init at91sam9g45_initialize(unsigned long main_clock)
static void __init at91sam9g45_initialize(void)
{
at91_arch_reset = at91sam9g45_reset;
pm_power_off = at91sam9g45_poweroff;
at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0);
/* Init clock subsystem */
at91_clock_init(main_clock);
/* Register the processor-specific clocks */
at91sam9g45_register_clocks();
/* Register GPIO subsystem */
at91_gpio_init(at91sam9g45_gpio, 5);
}
@ -393,14 +373,9 @@ static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = {
0, /* Advanced Interrupt Controller (IRQ0) */
};
void __init at91sam9g45_init_interrupts(unsigned int priority[NR_AIC_IRQS])
{
if (!priority)
priority = at91sam9g45_default_irq_priority;
/* Initialize the AIC interrupt controller */
at91_aic_init(priority);
/* Enable GPIO interrupts */
at91_gpio_irq_setup();
}
struct at91_init_soc __initdata at91sam9g45_soc = {
.map_io = at91sam9g45_map_io,
.default_irq_priority = at91sam9g45_default_irq_priority,
.register_clocks = at91sam9g45_register_clocks,
.init = at91sam9g45_initialize,
};

59
arch/arm/mach-at91/at91sam9rl.c
View File

@ -16,30 +16,16 @@
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/cpu.h>
#include <mach/at91_dbgu.h>
#include <mach/at91sam9rl.h>
#include <mach/at91_pmc.h>
#include <mach/at91_rstc.h>
#include <mach/at91_shdwc.h>
#include "soc.h"
#include "generic.h"
#include "clock.h"
static struct map_desc at91sam9rl_io_desc[] __initdata = {
{
.virtual = AT91_VA_BASE_SYS,
.pfn = __phys_to_pfn(AT91_BASE_SYS),
.length = SZ_16K,
.type = MT_DEVICE,
},
};
static struct map_desc at91sam9rl_sram_desc[] __initdata = {
{
.pfn = __phys_to_pfn(AT91SAM9RL_SRAM_BASE),
.type = MT_DEVICE,
}
};
/* --------------------------------------------------------------------
* Clocks
* -------------------------------------------------------------------- */
@ -287,16 +273,11 @@ static void at91sam9rl_poweroff(void)
* AT91SAM9RL processor initialization
* -------------------------------------------------------------------- */
void __init at91sam9rl_map_io(void)
static void __init at91sam9rl_map_io(void)
{
unsigned long cidr, sram_size;
unsigned long sram_size;
/* Map peripherals */
iotable_init(at91sam9rl_io_desc, ARRAY_SIZE(at91sam9rl_io_desc));
cidr = at91_sys_read(AT91_DBGU_CIDR);
switch (cidr & AT91_CIDR_SRAMSIZ) {
switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
case AT91_CIDR_SRAMSIZ_32K:
sram_size = 2 * SZ_16K;
break;
@ -305,25 +286,16 @@ void __init at91sam9rl_map_io(void)
sram_size = SZ_16K;
}
at91sam9rl_sram_desc->virtual = AT91_IO_VIRT_BASE - sram_size;
at91sam9rl_sram_desc->length = sram_size;
/* Map SRAM */
iotable_init(at91sam9rl_sram_desc, ARRAY_SIZE(at91sam9rl_sram_desc));
at91_init_sram(0, AT91SAM9RL_SRAM_BASE, sram_size);
}
void __init at91sam9rl_initialize(unsigned long main_clock)
static void __init at91sam9rl_initialize(void)
{
at91_arch_reset = at91sam9_alt_reset;
pm_power_off = at91sam9rl_poweroff;
at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0);
/* Init clock subsystem */
at91_clock_init(main_clock);
/* Register the processor-specific clocks */
at91sam9rl_register_clocks();
/* Register GPIO subsystem */
at91_gpio_init(at91sam9rl_gpio, 4);
}
@ -370,14 +342,9 @@ static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
0, /* Advanced Interrupt Controller */
};
void __init at91sam9rl_init_interrupts(unsigned int priority[NR_AIC_IRQS])
{
if (!priority)
priority = at91sam9rl_default_irq_priority;
/* Initialize the AIC interrupt controller */
at91_aic_init(priority);
/* Enable GPIO interrupts */
at91_gpio_irq_setup();
}
struct at91_init_soc __initdata at91sam9rl_soc = {
.map_io = at91sam9rl_map_io,
.default_irq_priority = at91sam9rl_default_irq_priority,
.register_clocks = at91sam9rl_register_clocks,
.init = at91sam9rl_initialize,
};

11
arch/arm/mach-at91/board-1arm.c
View File

@ -46,7 +46,7 @@ static void __init onearm_init_early(void)
at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
/* Initialize processor: 18.432 MHz crystal */
at91rm9200_initialize(18432000);
at91_initialize(18432000);
/* DBGU on ttyS0. (Rx & Tx only) */
at91_register_uart(0, 0, 0);
@ -63,11 +63,6 @@ static void __init onearm_init_early(void)
at91_set_serial_console(0);
}
static void __init onearm_init_irq(void)
{
at91rm9200_init_interrupts(NULL);
}
static struct at91_eth_data __initdata onearm_eth_data = {
.phy_irq_pin = AT91_PIN_PC4,
.is_rmii = 1,
@ -97,8 +92,8 @@ static void __init onearm_board_init(void)
MACHINE_START(ONEARM, "Ajeco 1ARM single board computer")
/* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
.timer = &at91rm9200_timer,
.map_io = at91rm9200_map_io,
.map_io = at91_map_io,
.init_early = onearm_init_early,
.init_irq = onearm_init_irq,
.init_irq = at91_init_irq_default,
.init_machine = onearm_board_init,
MACHINE_END

12
arch/arm/mach-at91/board-afeb-9260v1.c
View File

@ -51,7 +51,7 @@
static void __init afeb9260_init_early(void)
{
/* Initialize processor: 18.432 MHz crystal */
at91sam9260_initialize(18432000);
at91_initialize(18432000);
/* DBGU on ttyS0. (Rx & Tx only) */
at91_register_uart(0, 0, 0);
@ -70,12 +70,6 @@ static void __init afeb9260_init_early(void)
at91_set_serial_console(0);
}
static void __init afeb9260_init_irq(void)
{
at91sam9260_init_interrupts(NULL);
}
/*
* USB Host port
*/
@ -219,9 +213,9 @@ static void __init afeb9260_board_init(void)
MACHINE_START(AFEB9260, "Custom afeb9260 board")
/* Maintainer: Sergey Lapin <slapin@ossfans.org> */
.timer = &at91sam926x_timer,
.map_io = at91sam9260_map_io,
.map_io = at91_map_io,
.init_early = afeb9260_init_early,
.init_irq = afeb9260_init_irq,
.init_irq = at91_init_irq_default,
.init_machine = afeb9260_board_init,
MACHINE_END

12
arch/arm/mach-at91/board-cam60.c
View File

@ -48,7 +48,7 @@
static void __init cam60_init_early(void)
{
/* Initialize processor: 10 MHz crystal */
at91sam9260_initialize(10000000);
at91_initialize(10000000);
/* DBGU on ttyS0. (Rx & Tx only) */
at91_register_uart(0, 0, 0);
@ -57,12 +57,6 @@ static void __init cam60_init_early(void)
at91_set_serial_console(0);
}
static void __init cam60_init_irq(void)
{
at91sam9260_init_interrupts(NULL);
}
/*
* USB Host
*/
@ -199,8 +193,8 @@ static void __init cam60_board_init(void)
MACHINE_START(CAM60, "KwikByte CAM60")
/* Maintainer: KwikByte */
.timer = &at91sam926x_timer,
.map_io = at91sam9260_map_io,
.map_io = at91_map_io,
.init_early = cam60_init_early,
.init_irq = cam60_init_irq,
.init_irq = at91_init_irq_default,
.init_machine = cam60_board_init,
MACHINE_END

12
arch/arm/mach-at91/board-cap9adk.c
View File

@ -53,7 +53,7 @@
static void __init cap9adk_init_early(void)
{
/* Initialize processor: 12 MHz crystal */
at91cap9_initialize(12000000);
at91_initialize(12000000);
/* Setup the LEDs: USER1 and USER2 LED for cpu/timer... */
at91_init_leds(AT91_PIN_PA10, AT91_PIN_PA11);
@ -65,12 +65,6 @@ static void __init cap9adk_init_early(void)
at91_set_serial_console(0);
}
static void __init cap9adk_init_irq(void)
{
at91cap9_init_interrupts(NULL);
}
/*
* USB Host port
*/
@ -397,8 +391,8 @@ static void __init cap9adk_board_init(void)
MACHINE_START(AT91CAP9ADK, "Atmel AT91CAP9A-DK")
/* Maintainer: Stelian Pop <stelian.pop@leadtechdesign.com> */
.timer = &at91sam926x_timer,
.map_io = at91cap9_map_io,
.map_io = at91_map_io,
.init_early = cap9adk_init_early,
.init_irq = cap9adk_init_irq,
.init_irq = at91_init_irq_default,
.init_machine = cap9adk_board_init,
MACHINE_END

11
arch/arm/mach-at91/board-carmeva.c
View File

@ -43,7 +43,7 @@
static void __init carmeva_init_early(void)
{
/* Initialize processor: 20.000 MHz crystal */
at91rm9200_initialize(20000000);
at91_initialize(20000000);
/* DBGU on ttyS0. (Rx & Tx only) */
at91_register_uart(0, 0, 0);
@ -57,11 +57,6 @@ static void __init carmeva_init_early(void)
at91_set_serial_console(0);
}
static void __init carmeva_init_irq(void)
{
at91rm9200_init_interrupts(NULL);
}
static struct at91_eth_data __initdata carmeva_eth_data = {
.phy_irq_pin = AT91_PIN_PC4,
.is_rmii = 1,
@ -163,8 +158,8 @@ static void __init carmeva_board_init(void)
MACHINE_START(CARMEVA, "Carmeva")
/* Maintainer: Conitec Datasystems */
.timer = &at91rm9200_timer,
.map_io = at91rm9200_map_io,
.map_io = at91_map_io,
.init_early = carmeva_init_early,
.init_irq = carmeva_init_irq,
.init_irq = at91_init_irq_default,
.init_machine = carmeva_board_init,
MACHINE_END

11
arch/arm/mach-at91/board-cpu9krea.c
View File

@ -50,7 +50,7 @@
static void __init cpu9krea_init_early(void)
{
/* Initialize processor: 18.432 MHz crystal */
at91sam9260_initialize(18432000);
at91_initialize(18432000);
/* DGBU on ttyS0. (Rx & Tx only) */
at91_register_uart(0, 0, 0);
@ -81,11 +81,6 @@ static void __init cpu9krea_init_early(void)
at91_set_serial_console(0);
}
static void __init cpu9krea_init_irq(void)
{
at91sam9260_init_interrupts(NULL);
}
/*
* USB Host port
*/
@ -376,8 +371,8 @@ MACHINE_START(CPUAT9G20, "Eukrea CPU9G20")
#endif
/* Maintainer: Eric Benard - EUKREA Electromatique */
.timer = &at91sam926x_timer,
.map_io = at91sam9260_map_io,
.map_io = at91_map_io,
.init_early = cpu9krea_init_early,
.init_irq = cpu9krea_init_irq,
.init_irq = at91_init_irq_default,
.init_machine = cpu9krea_board_init,
MACHINE_END

11
arch/arm/mach-at91/board-cpuat91.c
View File

@ -57,7 +57,7 @@ static void __init cpuat91_init_early(void)
at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
/* Initialize processor: 18.432 MHz crystal */
at91rm9200_initialize(18432000);
at91_initialize(18432000);
/* DBGU on ttyS0. (Rx & Tx only) */
at91_register_uart(0, 0, 0);
@ -82,11 +82,6 @@ static void __init cpuat91_init_early(void)
at91_set_serial_console(0);
}
static void __init cpuat91_init_irq(void)
{
at91rm9200_init_interrupts(NULL);
}
static struct at91_eth_data __initdata cpuat91_eth_data = {
.is_rmii = 1,
};
@ -180,8 +175,8 @@ static void __init cpuat91_board_init(void)
MACHINE_START(CPUAT91, "Eukrea")
/* Maintainer: Eric Benard - EUKREA Electromatique */
.timer = &at91rm9200_timer,
.map_io = at91rm9200_map_io,
.map_io = at91_map_io,
.init_early = cpuat91_init_early,
.init_irq = cpuat91_init_irq,
.init_irq = at91_init_irq_default,
.init_machine = cpuat91_board_init,
MACHINE_END

11
arch/arm/mach-at91/board-csb337.c
View File

@ -46,7 +46,7 @@
static void __init csb337_init_early(void)
{
/* Initialize processor: 3.6864 MHz crystal */
at91rm9200_initialize(3686400);
at91_initialize(3686400);
/* Setup the LEDs */
at91_init_leds(AT91_PIN_PB0, AT91_PIN_PB1);
@ -58,11 +58,6 @@ static void __init csb337_init_early(void)
at91_set_serial_console(0);
}
static void __init csb337_init_irq(void)
{
at91rm9200_init_interrupts(NULL);
}
static struct at91_eth_data __initdata csb337_eth_data = {
.phy_irq_pin = AT91_PIN_PC2,
.is_rmii = 0,
@ -258,8 +253,8 @@ static void __init csb337_board_init(void)
MACHINE_START(CSB337, "Cogent CSB337")
/* Maintainer: Bill Gatliff */
.timer = &at91rm9200_timer,
.map_io = at91rm9200_map_io,
.map_io = at91_map_io,
.init_early = csb337_init_early,
.init_irq = csb337_init_irq,
.init_irq = at91_init_irq_default,
.init_machine = csb337_board_init,
MACHINE_END

11
arch/arm/mach-at91/board-csb637.c
View File

@ -43,7 +43,7 @@
static void __init csb637_init_early(void)
{
/* Initialize processor: 3.6864 MHz crystal */
at91rm9200_initialize(3686400);
at91_initialize(3686400);
/* DBGU on ttyS0. (Rx & Tx only) */
at91_register_uart(0, 0, 0);
@ -52,11 +52,6 @@ static void __init csb637_init_early(void)
at91_set_serial_console(0);
}
static void __init csb637_init_irq(void)
{
at91rm9200_init_interrupts(NULL);
}
static struct at91_eth_data __initdata csb637_eth_data = {
.phy_irq_pin = AT91_PIN_PC0,
.is_rmii = 0,
@ -139,8 +134,8 @@ static void __init csb637_board_init(void)
MACHINE_START(CSB637, "Cogent CSB637")
/* Maintainer: Bill Gatliff */
.timer = &at91rm9200_timer,
.map_io = at91rm9200_map_io,
.map_io = at91_map_io,
.init_early = csb637_init_early,
.init_irq = csb637_init_irq,
.init_irq = at91_init_irq_default,
.init_machine = csb637_board_init,
MACHINE_END

11
arch/arm/mach-at91/board-eb9200.c
View File

@ -43,7 +43,7 @@
static void __init eb9200_init_early(void)
{
/* Initialize processor: 18.432 MHz crystal */
at91rm9200_initialize(18432000);
at91_initialize(18432000);
/* DBGU on ttyS0. (Rx & Tx only) */
at91_register_uart(0, 0, 0);
@ -60,11 +60,6 @@ static void __init eb9200_init_early(void)
at91_set_serial_console(0);
}
static void __init eb9200_init_irq(void)
{
at91rm9200_init_interrupts(NULL);
}
static struct at91_eth_data __initdata eb9200_eth_data = {
.phy_irq_pin = AT91_PIN_PC4,
.is_rmii = 1,
@ -121,8 +116,8 @@ static void __init eb9200_board_init(void)
MACHINE_START(ATEB9200, "Embest ATEB9200")
.timer = &at91rm9200_timer,
.map_io = at91rm9200_map_io,
.map_io = at91_map_io,
.init_early = eb9200_init_early,
.init_irq = eb9200_init_irq,
.init_irq = at91_init_irq_default,
.init_machine = eb9200_board_init,
MACHINE_END

11
arch/arm/mach-at91/board-ecbat91.c
View File

@ -49,7 +49,7 @@ static void __init ecb_at91init_early(void)
at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
/* Initialize processor: 18.432 MHz crystal */
at91rm9200_initialize(18432000);
at91_initialize(18432000);
/* Setup the LEDs */
at91_init_leds(AT91_PIN_PC7, AT91_PIN_PC7);
@ -64,11 +64,6 @@ static void __init ecb_at91init_early(void)
at91_set_serial_console(0);
}
static void __init ecb_at91init_irq(void)
{
at91rm9200_init_interrupts(NULL);
}
static struct at91_eth_data __initdata ecb_at91eth_data = {
.phy_irq_pin = AT91_PIN_PC4,
.is_rmii = 0,
@ -173,8 +168,8 @@ static void __init ecb_at91board_init(void)
MACHINE_START(ECBAT91, "emQbit's ECB_AT91")
/* Maintainer: emQbit.com */
.timer = &at91rm9200_timer,
.map_io = at91rm9200_map_io,
.map_io = at91_map_io,
.init_early = ecb_at91init_early,
.init_irq = ecb_at91init_irq,
.init_irq = at91_init_irq_default,
.init_machine = ecb_at91board_init,
MACHINE_END

11
arch/arm/mach-at91/board-eco920.c
View File

@ -35,7 +35,7 @@ static void __init eco920_init_early(void)
/* Set cpu type: PQFP */
at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
at91rm9200_initialize(18432000);
at91_initialize(18432000);
/* Setup the LEDs */
at91_init_leds(AT91_PIN_PB0, AT91_PIN_PB1);
@ -47,11 +47,6 @@ static void __init eco920_init_early(void)
at91_set_serial_console(0);
}
static void __init eco920_init_irq(void)
{
at91rm9200_init_interrupts(NULL);
}
static struct at91_eth_data __initdata eco920_eth_data = {
.phy_irq_pin = AT91_PIN_PC2,
.is_rmii = 1,
@ -135,8 +130,8 @@ static void __init eco920_board_init(void)
MACHINE_START(ECO920, "eco920")
/* Maintainer: Sascha Hauer */
.timer = &at91rm9200_timer,
.map_io = at91rm9200_map_io,
.map_io = at91_map_io,
.init_early = eco920_init_early,
.init_irq = eco920_init_irq,
.init_irq = at91_init_irq_default,
.init_machine = eco920_board_init,
MACHINE_END

11
arch/arm/mach-at91/board-flexibity.c
View File

@ -40,7 +40,7 @@
static void __init flexibity_init_early(void)
{
/* Initialize processor: 18.432 MHz crystal */
at91sam9260_initialize(18432000);
at91_initialize(18432000);
/* DBGU on ttyS0. (Rx & Tx only) */
at91_register_uart(0, 0, 0);
@ -49,11 +49,6 @@ static void __init flexibity_init_early(void)
at91_set_serial_console(0);
}
static void __init flexibity_init_irq(void)
{
at91sam9260_init_interrupts(NULL);
}
/* USB Host port */
static struct at91_usbh_data __initdata flexibity_usbh_data = {
.ports = 2,
@ -155,8 +150,8 @@ static void __init flexibity_board_init(void)
MACHINE_START(FLEXIBITY, "Flexibity Connect")
/* Maintainer: Maxim Osipov */
.timer = &at91sam926x_timer,
.map_io = at91sam9260_map_io,
.map_io = at91_map_io,
.init_early = flexibity_init_early,
.init_irq = flexibity_init_irq,
.init_irq = at91_init_irq_default,
.init_machine = flexibity_board_init,
MACHINE_END

12
arch/arm/mach-at91/board-foxg20.c
View File

@ -60,7 +60,7 @@
static void __init foxg20_init_early(void)
{
/* Initialize processor: 18.432 MHz crystal */
at91sam9260_initialize(18432000);
at91_initialize(18432000);
/* DBGU on ttyS0. (Rx & Tx only) */
at91_register_uart(0, 0, 0);
@ -101,12 +101,6 @@ static void __init foxg20_init_early(void)
}
static void __init foxg20_init_irq(void)
{
at91sam9260_init_interrupts(NULL);
}
/*
* USB Host port
*/
@ -267,8 +261,8 @@ static void __init foxg20_board_init(void)
MACHINE_START(ACMENETUSFOXG20, "Acme Systems srl FOX Board G20")
/* Maintainer: Sergio Tanzilli */
.timer = &at91sam926x_timer,
.map_io = at91sam9260_map_io,
.map_io = at91_map_io,
.init_early = foxg20_init_early,
.init_irq = foxg20_init_irq,
.init_irq = at91_init_irq_default,
.init_machine = foxg20_board_init,
MACHINE_END

9
arch/arm/mach-at91/board-gsia18s.c
View File

@ -75,11 +75,6 @@ static void __init gsia18s_init_early(void)
at91_register_uart(AT91SAM9260_ID_US4, 5, 0);
}
static void __init init_irq(void)
{
at91sam9260_init_interrupts(NULL);
}
/*
* Two USB Host ports
*/
@ -577,8 +572,8 @@ static void __init gsia18s_board_init(void)
MACHINE_START(GSIA18S, "GS_IA18_S")
.timer = &at91sam926x_timer,
.map_io = at91sam9260_map_io,
.map_io = at91_map_io,
.init_early = gsia18s_init_early,
.init_irq = init_irq,
.init_irq = at91_init_irq_default,
.init_machine = gsia18s_board_init,
MACHINE_END

11
arch/arm/mach-at91/board-kafa.c
View File

@ -46,7 +46,7 @@ static void __init kafa_init_early(void)
at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
/* Initialize processor: 18.432 MHz crystal */
at91rm9200_initialize(18432000);
at91_initialize(18432000);
/* Set up the LEDs */
at91_init_leds(AT91_PIN_PB4, AT91_PIN_PB4);
@ -61,11 +61,6 @@ static void __init kafa_init_early(void)
at91_set_serial_console(0);
}
static void __init kafa_init_irq(void)
{
at91rm9200_init_interrupts(NULL);
}
static struct at91_eth_data __initdata kafa_eth_data = {
.phy_irq_pin = AT91_PIN_PC4,
.is_rmii = 0,
@ -99,8 +94,8 @@ static void __init kafa_board_init(void)
MACHINE_START(KAFA, "Sperry-Sun KAFA")
/* Maintainer: Sergei Sharonov */
.timer = &at91rm9200_timer,
.map_io = at91rm9200_map_io,
.map_io = at91_map_io,
.init_early = kafa_init_early,
.init_irq = kafa_init_irq,
.init_irq = at91_init_irq_default,
.init_machine = kafa_board_init,
MACHINE_END

11
arch/arm/mach-at91/board-kb9202.c
View File

@ -48,7 +48,7 @@ static void __init kb9202_init_early(void)
at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
/* Initialize processor: 10 MHz crystal */
at91rm9200_initialize(10000000);
at91_initialize(10000000);
/* Set up the LEDs */
at91_init_leds(AT91_PIN_PC19, AT91_PIN_PC18);
@ -69,11 +69,6 @@ static void __init kb9202_init_early(void)
at91_set_serial_console(0);
}
static void __init kb9202_init_irq(void)
{
at91rm9200_init_interrupts(NULL);
}
static struct at91_eth_data __initdata kb9202_eth_data = {
.phy_irq_pin = AT91_PIN_PB29,
.is_rmii = 0,
@ -140,8 +135,8 @@ static void __init kb9202_board_init(void)
MACHINE_START(KB9200, "KB920x")
/* Maintainer: KwikByte, Inc. */
.timer = &at91rm9200_timer,
.map_io = at91rm9200_map_io,
.map_io = at91_map_io,
.init_early = kb9202_init_early,
.init_irq = kb9202_init_irq,
.init_irq = at91_init_irq_default,
.init_machine = kb9202_board_init,
MACHINE_END

12
arch/arm/mach-at91/board-neocore926.c
View File

@ -54,7 +54,7 @@
static void __init neocore926_init_early(void)
{
/* Initialize processor: 20 MHz crystal */
at91sam9263_initialize(20000000);
at91_initialize(20000000);
/* DBGU on ttyS0. (Rx & Tx only) */
at91_register_uart(0, 0, 0);
@ -66,12 +66,6 @@ static void __init neocore926_init_early(void)
at91_set_serial_console(0);
}
static void __init neocore926_init_irq(void)
{
at91sam9263_init_interrupts(NULL);
}
/*
* USB Host port
*/
@ -388,8 +382,8 @@ static void __init neocore926_board_init(void)
MACHINE_START(NEOCORE926, "ADENEO NEOCORE 926")
/* Maintainer: ADENEO */
.timer = &at91sam926x_timer,
.map_io = at91sam9263_map_io,
.map_io = at91_map_io,
.init_early = neocore926_init_early,
.init_irq = neocore926_init_irq,
.init_irq = at91_init_irq_default,
.init_machine = neocore926_board_init,
MACHINE_END

11
arch/arm/mach-at91/board-pcontrol-g20.c
View File

@ -53,13 +53,6 @@ static void __init pcontrol_g20_init_early(void)
at91_register_uart(AT91SAM9260_ID_US4, 3, 0);
}
static void __init init_irq(void)
{
at91sam9260_init_interrupts(NULL);
}
static struct sam9_smc_config __initdata pcontrol_smc_config[2] = { {
.ncs_read_setup = 16,
.nrd_setup = 18,
@ -223,8 +216,8 @@ static void __init pcontrol_g20_board_init(void)
MACHINE_START(PCONTROL_G20, "PControl G20")
/* Maintainer: pgsellmann@portner-elektronik.at */
.timer = &at91sam926x_timer,
.map_io = at91sam9260_map_io,
.map_io = at91_map_io,
.init_early = pcontrol_g20_init_early,
.init_irq = init_irq,
.init_irq = at91_init_irq_default,
.init_machine = pcontrol_g20_board_init,
MACHINE_END

11
arch/arm/mach-at91/board-picotux200.c
View File

@ -46,7 +46,7 @@
static void __init picotux200_init_early(void)
{
/* Initialize processor: 18.432 MHz crystal */
at91rm9200_initialize(18432000);
at91_initialize(18432000);
/* DBGU on ttyS0. (Rx & Tx only) */
at91_register_uart(0, 0, 0);
@ -60,11 +60,6 @@ static void __init picotux200_init_early(void)
at91_set_serial_console(0);
}
static void __init picotux200_init_irq(void)
{
at91rm9200_init_interrupts(NULL);
}
static struct at91_eth_data __initdata picotux200_eth_data = {
.phy_irq_pin = AT91_PIN_PC4,
.is_rmii = 1,
@ -124,8 +119,8 @@ static void __init picotux200_board_init(void)
MACHINE_START(PICOTUX2XX, "picotux 200")
/* Maintainer: Kleinhenz Elektronik GmbH */
.timer = &at91rm9200_timer,
.map_io = at91rm9200_map_io,
.map_io = at91_map_io,
.init_early = picotux200_init_early,
.init_irq = picotux200_init_irq,
.init_irq = at91_init_irq_default,
.init_machine = picotux200_board_init,
MACHINE_END

12
arch/arm/mach-at91/board-qil-a9260.c
View File

@ -51,7 +51,7 @@
static void __init ek_init_early(void)
{
/* Initialize processor: 12.000 MHz crystal */
at91sam9260_initialize(12000000);
at91_initialize(12000000);
/* DBGU on ttyS0. (Rx & Tx only) */
at91_register_uart(0, 0, 0);
@ -72,12 +72,6 @@ static void __init ek_init_early(void)
}
static void __init ek_init_irq(void)
{
at91sam9260_init_interrupts(NULL);
}
/*
* USB Host port
*/
@ -269,8 +263,8 @@ static void __init ek_board_init(void)
MACHINE_START(QIL_A9260, "CALAO QIL_A9260")
/* Maintainer: calao-systems */
.timer = &at91sam926x_timer,
.map_io = at91sam9260_map_io,
.map_io = at91_map_io,
.init_early = ek_init_early,
.init_irq = ek_init_irq,
.init_irq = at91_init_irq_default,
.init_machine = ek_board_init,
MACHINE_END

11
arch/arm/mach-at91/board-rm9200dk.c
View File

@ -48,7 +48,7 @@
static void __init dk_init_early(void)
{
/* Initialize processor: 18.432 MHz crystal */
at91rm9200_initialize(18432000);
at91_initialize(18432000);
/* Setup the LEDs */
at91_init_leds(AT91_PIN_PB2, AT91_PIN_PB2);
@ -65,11 +65,6 @@ static void __init dk_init_early(void)
at91_set_serial_console(0);
}
static void __init dk_init_irq(void)
{
at91rm9200_init_interrupts(NULL);
}
static struct at91_eth_data __initdata dk_eth_data = {
.phy_irq_pin = AT91_PIN_PC4,
.is_rmii = 1,
@ -228,8 +223,8 @@ static void __init dk_board_init(void)
MACHINE_START(AT91RM9200DK, "Atmel AT91RM9200-DK")
/* Maintainer: SAN People/Atmel */
.timer = &at91rm9200_timer,
.map_io = at91rm9200_map_io,
.map_io = at91_map_io,
.init_early = dk_init_early,
.init_irq = dk_init_irq,
.init_irq = at91_init_irq_default,
.init_machine = dk_board_init,
MACHINE_END

11
arch/arm/mach-at91/board-rm9200ek.c
View File

@ -48,7 +48,7 @@
static void __init ek_init_early(void)
{
/* Initialize processor: 18.432 MHz crystal */
at91rm9200_initialize(18432000);
at91_initialize(18432000);
/* Setup the LEDs */
at91_init_leds(AT91_PIN_PB1, AT91_PIN_PB2);
@ -65,11 +65,6 @@ static void __init ek_init_early(void)
at91_set_serial_console(0);
}
static void __init ek_init_irq(void)
{
at91rm9200_init_interrupts(NULL);
}
static struct at91_eth_data __initdata ek_eth_data = {
.phy_irq_pin = AT91_PIN_PC4,
.is_rmii = 1,
@ -194,8 +189,8 @@ static void __init ek_board_init(void)
MACHINE_START(AT91RM9200EK, "Atmel AT91RM9200-EK")
/* Maintainer: SAN People/Atmel */
.timer = &at91rm9200_timer,
.map_io = at91rm9200_map_io,
.map_io = at91_map_io,
.init_early = ek_init_early,
.init_irq = ek_init_irq,
.init_irq = at91_init_irq_default,
.init_machine = ek_board_init,
MACHINE_END

12
arch/arm/mach-at91/board-sam9-l9260.c
View File

@ -47,7 +47,7 @@
static void __init ek_init_early(void)
{
/* Initialize processor: 18.432 MHz crystal */
at91sam9260_initialize(18432000);
at91_initialize(18432000);
/* Setup the LEDs */
at91_init_leds(AT91_PIN_PA9, AT91_PIN_PA6);
@ -67,12 +67,6 @@ static void __init ek_init_early(void)
at91_set_serial_console(0);
}
static void __init ek_init_irq(void)
{
at91sam9260_init_interrupts(NULL);
}
/*
* USB Host port
*/
@ -213,8 +207,8 @@ static void __init ek_board_init(void)
MACHINE_START(SAM9_L9260, "Olimex SAM9-L9260")
/* Maintainer: Olimex */
.timer = &at91sam926x_timer,
.map_io = at91sam9260_map_io,
.map_io = at91_map_io,
.init_early = ek_init_early,
.init_irq = ek_init_irq,
.init_irq = at91_init_irq_default,
.init_machine = ek_board_init,
MACHINE_END

12
arch/arm/mach-at91/board-sam9260ek.c
View File

@ -53,7 +53,7 @@
static void __init ek_init_early(void)
{
/* Initialize processor: 18.432 MHz crystal */
at91sam9260_initialize(18432000);
at91_initialize(18432000);
/* DBGU on ttyS0. (Rx & Tx only) */
at91_register_uart(0, 0, 0);
@ -70,12 +70,6 @@ static void __init ek_init_early(void)
at91_set_serial_console(0);
}
static void __init ek_init_irq(void)
{
at91sam9260_init_interrupts(NULL);
}
/*
* USB Host port
*/
@ -354,8 +348,8 @@ static void __init ek_board_init(void)
MACHINE_START(AT91SAM9260EK, "Atmel AT91SAM9260-EK")
/* Maintainer: Atmel */
.timer = &at91sam926x_timer,
.map_io = at91sam9260_map_io,
.map_io = at91_map_io,
.init_early = ek_init_early,
.init_irq = ek_init_irq,
.init_irq = at91_init_irq_default,
.init_machine = ek_board_init,
MACHINE_END

12
arch/arm/mach-at91/board-sam9261ek.c
View File

@ -57,7 +57,7 @@
static void __init ek_init_early(void)
{
/* Initialize processor: 18.432 MHz crystal */
at91sam9261_initialize(18432000);
at91_initialize(18432000);
/* Setup the LEDs */
at91_init_leds(AT91_PIN_PA13, AT91_PIN_PA14);
@ -69,12 +69,6 @@ static void __init ek_init_early(void)
at91_set_serial_console(0);
}
static void __init ek_init_irq(void)
{
at91sam9261_init_interrupts(NULL);
}
/*
* DM9000 ethernet device
*/
@ -621,8 +615,8 @@ MACHINE_START(AT91SAM9G10EK, "Atmel AT91SAM9G10-EK")
#endif
/* Maintainer: Atmel */
.timer = &at91sam926x_timer,
.map_io = at91sam9261_map_io,
.map_io = at91_map_io,
.init_early = ek_init_early,
.init_irq = ek_init_irq,
.init_irq = at91_init_irq_default,
.init_machine = ek_board_init,
MACHINE_END

12
arch/arm/mach-at91/board-sam9263ek.c
View File

@ -56,7 +56,7 @@
static void __init ek_init_early(void)
{
/* Initialize processor: 16.367 MHz crystal */
at91sam9263_initialize(16367660);
at91_initialize(16367660);
/* DBGU on ttyS0. (Rx & Tx only) */
at91_register_uart(0, 0, 0);
@ -68,12 +68,6 @@ static void __init ek_init_early(void)
at91_set_serial_console(0);
}
static void __init ek_init_irq(void)
{
at91sam9263_init_interrupts(NULL);
}
/*
* USB Host port
*/
@ -452,8 +446,8 @@ static void __init ek_board_init(void)
MACHINE_START(AT91SAM9263EK, "Atmel AT91SAM9263-EK")
/* Maintainer: Atmel */
.timer = &at91sam926x_timer,
.map_io = at91sam9263_map_io,
.map_io = at91_map_io,
.init_early = ek_init_early,
.init_irq = ek_init_irq,
.init_irq = at91_init_irq_default,
.init_machine = ek_board_init,
MACHINE_END

16
arch/arm/mach-at91/board-sam9g20ek.c
View File

@ -64,7 +64,7 @@ static int inline ek_have_2mmc(void)
static void __init ek_init_early(void)
{
/* Initialize processor: 18.432 MHz crystal */
at91sam9260_initialize(18432000);
at91_initialize(18432000);
/* DBGU on ttyS0. (Rx & Tx only) */
at91_register_uart(0, 0, 0);
@ -81,12 +81,6 @@ static void __init ek_init_early(void)
at91_set_serial_console(0);
}
static void __init ek_init_irq(void)
{
at91sam9260_init_interrupts(NULL);
}
/*
* USB Host port
*/
@ -404,17 +398,17 @@ static void __init ek_board_init(void)
MACHINE_START(AT91SAM9G20EK, "Atmel AT91SAM9G20-EK")
/* Maintainer: Atmel */
.timer = &at91sam926x_timer,
.map_io = at91sam9260_map_io,
.map_io = at91_map_io,
.init_early = ek_init_early,
.init_irq = ek_init_irq,
.init_irq = at91_init_irq_default,
.init_machine = ek_board_init,
MACHINE_END
MACHINE_START(AT91SAM9G20EK_2MMC, "Atmel AT91SAM9G20-EK 2 MMC Slot Mod")
/* Maintainer: Atmel */
.timer = &at91sam926x_timer,
.map_io = at91sam9260_map_io,
.map_io = at91_map_io,
.init_early = ek_init_early,
.init_irq = ek_init_irq,
.init_irq = at91_init_irq_default,
.init_machine = ek_board_init,
MACHINE_END

12
arch/arm/mach-at91/board-sam9m10g45ek.c
View File

@ -50,7 +50,7 @@
static void __init ek_init_early(void)
{
/* Initialize processor: 12.000 MHz crystal */
at91sam9g45_initialize(12000000);
at91_initialize(12000000);
/* DGBU on ttyS0. (Rx & Tx only) */
at91_register_uart(0, 0, 0);
@ -63,12 +63,6 @@ static void __init ek_init_early(void)
at91_set_serial_console(0);
}
static void __init ek_init_irq(void)
{
at91sam9g45_init_interrupts(NULL);
}
/*
* USB HS Host port (common to OHCI & EHCI)
*/
@ -422,8 +416,8 @@ static void __init ek_board_init(void)
MACHINE_START(AT91SAM9M10G45EK, "Atmel AT91SAM9M10G45-EK")
/* Maintainer: Atmel */
.timer = &at91sam926x_timer,
.map_io = at91sam9g45_map_io,
.map_io = at91_map_io,
.init_early = ek_init_early,
.init_irq = ek_init_irq,
.init_irq = at91_init_irq_default,
.init_machine = ek_board_init,
MACHINE_END

12
arch/arm/mach-at91/board-sam9rlek.c
View File

@ -41,7 +41,7 @@
static void __init ek_init_early(void)
{
/* Initialize processor: 12.000 MHz crystal */
at91sam9rl_initialize(12000000);
at91_initialize(12000000);
/* DBGU on ttyS0. (Rx & Tx only) */
at91_register_uart(0, 0, 0);
@ -53,12 +53,6 @@ static void __init ek_init_early(void)
at91_set_serial_console(0);
}
static void __init ek_init_irq(void)
{
at91sam9rl_init_interrupts(NULL);
}
/*
* USB HS Device port
*/
@ -330,8 +324,8 @@ static void __init ek_board_init(void)
MACHINE_START(AT91SAM9RLEK, "Atmel AT91SAM9RL-EK")
/* Maintainer: Atmel */
.timer = &at91sam926x_timer,
.map_io = at91sam9rl_map_io,
.map_io = at91_map_io,
.init_early = ek_init_early,
.init_irq = ek_init_irq,
.init_irq = at91_init_irq_default,
.init_machine = ek_board_init,
MACHINE_END

11
arch/arm/mach-at91/board-snapper9260.c
View File

@ -42,7 +42,7 @@
static void __init snapper9260_init_early(void)
{
at91sam9260_initialize(18432000);
at91_initialize(18432000);
/* Debug on ttyS0 */
at91_register_uart(0, 0, 0);
@ -55,11 +55,6 @@ static void __init snapper9260_init_early(void)
at91_register_uart(AT91SAM9260_ID_US2, 3, 0);
}
static void __init snapper9260_init_irq(void)
{
at91sam9260_init_interrupts(NULL);
}
static struct at91_usbh_data __initdata snapper9260_usbh_data = {
.ports = 2,
};
@ -179,9 +174,9 @@ static void __init snapper9260_board_init(void)
MACHINE_START(SNAPPER_9260, "Bluewater Systems Snapper 9260/9G20 module")
.timer = &at91sam926x_timer,
.map_io = at91sam9260_map_io,
.map_io = at91_map_io,
.init_early = snapper9260_init_early,
.init_irq = snapper9260_init_irq,
.init_irq = at91_init_irq_default,
.init_machine = snapper9260_board_init,
MACHINE_END

16
arch/arm/mach-at91/board-stamp9g20.c
View File

@ -35,7 +35,7 @@
void __init stamp9g20_init_early(void)
{
/* Initialize processor: 18.432 MHz crystal */
at91sam9260_initialize(18432000);
at91_initialize(18432000);
/* DGBU on ttyS0. (Rx & Tx only) */
at91_register_uart(0, 0, 0);
@ -76,12 +76,6 @@ static void __init portuxg20_init_early(void)
at91_register_uart(AT91SAM9260_ID_US5, 6, 0);
}
static void __init init_irq(void)
{
at91sam9260_init_interrupts(NULL);
}
/*
* NAND flash
*/
@ -299,17 +293,17 @@ static void __init stamp9g20evb_board_init(void)
MACHINE_START(PORTUXG20, "taskit PortuxG20")
/* Maintainer: taskit GmbH */
.timer = &at91sam926x_timer,
.map_io = at91sam9260_map_io,
.map_io = at91_map_io,
.init_early = portuxg20_init_early,
.init_irq = init_irq,
.init_irq = at91_init_irq_default,
.init_machine = portuxg20_board_init,
MACHINE_END
MACHINE_START(STAMP9G20, "taskit Stamp9G20")
/* Maintainer: taskit GmbH */
.timer = &at91sam926x_timer,
.map_io = at91sam9260_map_io,
.map_io = at91_map_io,
.init_early = stamp9g20evb_init_early,
.init_irq = init_irq,
.init_irq = at91_init_irq_default,
.init_machine = stamp9g20evb_board_init,
MACHINE_END

12
arch/arm/mach-at91/board-usb-a9260.c
View File

@ -51,7 +51,7 @@
static void __init ek_init_early(void)
{
/* Initialize processor: 12.000 MHz crystal */
at91sam9260_initialize(12000000);
at91_initialize(12000000);
/* DBGU on ttyS0. (Rx & Tx only) */
at91_register_uart(0, 0, 0);
@ -60,12 +60,6 @@ static void __init ek_init_early(void)
at91_set_serial_console(0);
}
static void __init ek_init_irq(void)
{
at91sam9260_init_interrupts(NULL);
}
/*
* USB Host port
*/
@ -229,8 +223,8 @@ static void __init ek_board_init(void)
MACHINE_START(USB_A9260, "CALAO USB_A9260")
/* Maintainer: calao-systems */
.timer = &at91sam926x_timer,
.map_io = at91sam9260_map_io,
.map_io = at91_map_io,
.init_early = ek_init_early,
.init_irq = ek_init_irq,
.init_irq = at91_init_irq_default,
.init_machine = ek_board_init,
MACHINE_END

12
arch/arm/mach-at91/board-usb-a9263.c
View File

@ -50,7 +50,7 @@
static void __init ek_init_early(void)
{
/* Initialize processor: 12.00 MHz crystal */
at91sam9263_initialize(12000000);
at91_initialize(12000000);
/* DBGU on ttyS0. (Rx & Tx only) */
at91_register_uart(0, 0, 0);
@ -59,12 +59,6 @@ static void __init ek_init_early(void)
at91_set_serial_console(0);
}
static void __init ek_init_irq(void)
{
at91sam9263_init_interrupts(NULL);
}
/*
* USB Host port
*/
@ -245,8 +239,8 @@ static void __init ek_board_init(void)
MACHINE_START(USB_A9263, "CALAO USB_A9263")
/* Maintainer: calao-systems */
.timer = &at91sam926x_timer,
.map_io = at91sam9263_map_io,
.map_io = at91_map_io,
.init_early = ek_init_early,
.init_irq = ek_init_irq,
.init_irq = at91_init_irq_default,
.init_machine = ek_board_init,
MACHINE_END

12
arch/arm/mach-at91/board-yl-9200.c
View File

@ -56,7 +56,7 @@ static void __init yl9200_init_early(void)
at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
/* Initialize processor: 18.432 MHz crystal */
at91rm9200_initialize(18432000);
at91_initialize(18432000);
/* Setup the LEDs D2=PB17 (timer), D3=PB16 (cpu) */
at91_init_leds(AT91_PIN_PB16, AT91_PIN_PB17);
@ -79,12 +79,6 @@ static void __init yl9200_init_early(void)
at91_set_serial_console(0);
}
static void __init yl9200_init_irq(void)
{
at91rm9200_init_interrupts(NULL);
}
/*
* LEDs
*/
@ -599,8 +593,8 @@ static void __init yl9200_board_init(void)
MACHINE_START(YL9200, "uCdragon YL-9200")
/* Maintainer: S.Birtles */
.timer = &at91rm9200_timer,
.map_io = at91rm9200_map_io,
.map_io = at91_map_io,
.init_early = yl9200_init_early,
.init_irq = yl9200_init_irq,
.init_irq = at91_init_irq_default,
.init_machine = yl9200_board_init,
MACHINE_END

34
arch/arm/mach-at91/generic.h
View File

@ -11,35 +11,19 @@
#include <linux/clkdev.h>
/* Map io */
extern void __init at91rm9200_map_io(void);
extern void __init at91sam9260_map_io(void);
extern void __init at91sam9261_map_io(void);
extern void __init at91sam9263_map_io(void);
extern void __init at91sam9rl_map_io(void);
extern void __init at91sam9g45_map_io(void);
extern void __init at91x40_map_io(void);
extern void __init at91cap9_map_io(void);
extern void __init at91_map_io(void);
extern void __init at91_init_sram(int bank, unsigned long base,
unsigned int length);
/* Processors */
extern void __init at91rm9200_set_type(int type);
extern void __init at91rm9200_initialize(unsigned long main_clock);
extern void __init at91sam9260_initialize(unsigned long main_clock);
extern void __init at91sam9261_initialize(unsigned long main_clock);
extern void __init at91sam9263_initialize(unsigned long main_clock);
extern void __init at91sam9rl_initialize(unsigned long main_clock);
extern void __init at91sam9g45_initialize(unsigned long main_clock);
extern void __init at91_initialize(unsigned long main_clock);
extern void __init at91x40_initialize(unsigned long main_clock);
extern void __init at91cap9_initialize(unsigned long main_clock);
/* Interrupts */
extern void __init at91rm9200_init_interrupts(unsigned int priority[]);
extern void __init at91sam9260_init_interrupts(unsigned int priority[]);
extern void __init at91sam9261_init_interrupts(unsigned int priority[]);
extern void __init at91sam9263_init_interrupts(unsigned int priority[]);
extern void __init at91sam9rl_init_interrupts(unsigned int priority[]);
extern void __init at91sam9g45_init_interrupts(unsigned int priority[]);
extern void __init at91_init_irq_default(void);
extern void __init at91_init_interrupts(unsigned int priority[]);
extern void __init at91x40_init_interrupts(unsigned int priority[]);
extern void __init at91cap9_init_interrupts(unsigned int priority[]);
extern void __init at91_aic_init(unsigned int priority[]);
/* Timer */
@ -49,7 +33,6 @@ extern struct sys_timer at91sam926x_timer;
extern struct sys_timer at91x40_timer;
/* Clocks */
extern int __init at91_clock_init(unsigned long main_clock);
/*
* function to specify the clock of the default console. As we do not
* use the device/driver bus, the dev_name is not intialize. So we need
@ -62,6 +45,11 @@ extern void __init at91sam9263_set_console_clock(int id);
extern void __init at91sam9rl_set_console_clock(int id);
extern void __init at91sam9g45_set_console_clock(int id);
extern void __init at91cap9_set_console_clock(int id);
#ifdef CONFIG_AT91_PMC_UNIT
extern int __init at91_clock_init(unsigned long main_clock);
#else
static int inline at91_clock_init(unsigned long main_clock) { return 0; }
#endif
struct device;
/* Power Management */

27
arch/arm/mach-at91/include/mach/at91_dbgu.h
View File

@ -16,22 +16,25 @@
#ifndef AT91_DBGU_H
#define AT91_DBGU_H
#define dbgu_readl(dbgu, field) \
__raw_readl(AT91_VA_BASE_SYS + dbgu + AT91_DBGU_ ## field)
#ifdef AT91_DBGU
#define AT91_DBGU_CR (AT91_DBGU + 0x00) /* Control Register */
#define AT91_DBGU_MR (AT91_DBGU + 0x04) /* Mode Register */
#define AT91_DBGU_IER (AT91_DBGU + 0x08) /* Interrupt Enable Register */
#define AT91_DBGU_CR (0x00) /* Control Register */
#define AT91_DBGU_MR (0x04) /* Mode Register */
#define AT91_DBGU_IER (0x08) /* Interrupt Enable Register */
#define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */
#define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */
#define AT91_DBGU_IDR (AT91_DBGU + 0x0c) /* Interrupt Disable Register */
#define AT91_DBGU_IMR (AT91_DBGU + 0x10) /* Interrupt Mask Register */
#define AT91_DBGU_SR (AT91_DBGU + 0x14) /* Status Register */
#define AT91_DBGU_RHR (AT91_DBGU + 0x18) /* Receiver Holding Register */
#define AT91_DBGU_THR (AT91_DBGU + 0x1c) /* Transmitter Holding Register */
#define AT91_DBGU_BRGR (AT91_DBGU + 0x20) /* Baud Rate Generator Register */
#define AT91_DBGU_IDR (0x0c) /* Interrupt Disable Register */
#define AT91_DBGU_IMR (0x10) /* Interrupt Mask Register */
#define AT91_DBGU_SR (0x14) /* Status Register */
#define AT91_DBGU_RHR (0x18) /* Receiver Holding Register */
#define AT91_DBGU_THR (0x1c) /* Transmitter Holding Register */
#define AT91_DBGU_BRGR (0x20) /* Baud Rate Generator Register */
#define AT91_DBGU_CIDR (AT91_DBGU + 0x40) /* Chip ID Register */
#define AT91_DBGU_EXID (AT91_DBGU + 0x44) /* Chip ID Extension Register */
#define AT91_DBGU_FNR (AT91_DBGU + 0x48) /* Force NTRST Register [SAM9 only] */
#define AT91_DBGU_CIDR (0x40) /* Chip ID Register */
#define AT91_DBGU_EXID (0x44) /* Chip ID Extension Register */
#define AT91_DBGU_FNR (0x48) /* Force NTRST Register [SAM9 only] */
#define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */
#endif /* AT91_DBGU */

1
arch/arm/mach-at91/include/mach/at91cap9.h
View File

@ -75,7 +75,6 @@
#define AT91CAP9_BASE_EMAC 0xfffbc000
#define AT91CAP9_BASE_ADC 0xfffc0000
#define AT91CAP9_BASE_ISI 0xfffc4000
#define AT91_BASE_SYS 0xffffe200
/*
* System Peripherals (offset from AT91_BASE_SYS)

1
arch/arm/mach-at91/include/mach/at91rm9200.h
View File

@ -74,7 +74,6 @@
#define AT91RM9200_BASE_SSC1 0xfffd4000
#define AT91RM9200_BASE_SSC2 0xfffd8000
#define AT91RM9200_BASE_SPI 0xfffe0000
#define AT91_BASE_SYS 0xfffff000
/*

1
arch/arm/mach-at91/include/mach/at91sam9260.h
View File

@ -76,7 +76,6 @@
#define AT91SAM9260_BASE_TC4 0xfffdc040
#define AT91SAM9260_BASE_TC5 0xfffdc080
#define AT91SAM9260_BASE_ADC 0xfffe0000
#define AT91_BASE_SYS 0xffffe800
/*
* System Peripherals (offset from AT91_BASE_SYS)

1
arch/arm/mach-at91/include/mach/at91sam9261.h
View File

@ -60,7 +60,6 @@
#define AT91SAM9261_BASE_SSC2 0xfffc4000
#define AT91SAM9261_BASE_SPI0 0xfffc8000
#define AT91SAM9261_BASE_SPI1 0xfffcc000
#define AT91_BASE_SYS 0xffffea00
/*

1
arch/arm/mach-at91/include/mach/at91sam9263.h
View File

@ -70,7 +70,6 @@
#define AT91SAM9263_BASE_EMAC 0xfffbc000
#define AT91SAM9263_BASE_ISI 0xfffc4000
#define AT91SAM9263_BASE_2DGE 0xfffc8000
#define AT91_BASE_SYS 0xffffe000
/*
* System Peripherals (offset from AT91_BASE_SYS)

1
arch/arm/mach-at91/include/mach/at91sam9g45.h
View File

@ -82,7 +82,6 @@
#define AT91SAM9G45_BASE_TC3 0xfffd4000
#define AT91SAM9G45_BASE_TC4 0xfffd4040
#define AT91SAM9G45_BASE_TC5 0xfffd4080
#define AT91_BASE_SYS 0xffffe200
/*
* System Peripherals (offset from AT91_BASE_SYS)

1
arch/arm/mach-at91/include/mach/at91sam9rl.h
View File

@ -64,7 +64,6 @@
#define AT91SAM9RL_BASE_TSC 0xfffd0000
#define AT91SAM9RL_BASE_UDPHS 0xfffd4000
#define AT91SAM9RL_BASE_AC97C 0xfffd8000
#define AT91_BASE_SYS 0xffffc000
/*

163
arch/arm/mach-at91/include/mach/cpu.h
View File

@ -1,7 +1,8 @@
/*
* arch/arm/mach-at91/include/mach/cpu.h
*
* Copyright (C) 2006 SAN People
* Copyright (C) 2006 SAN People
* Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -10,12 +11,8 @@
*
*/
#ifndef __ASM_ARCH_CPU_H
#define __ASM_ARCH_CPU_H
#include <mach/hardware.h>
#include <mach/at91_dbgu.h>
#ifndef __MACH_CPU_H__
#define __MACH_CPU_H__
#define ARCH_ID_AT91RM9200 0x09290780
#define ARCH_ID_AT91SAM9260 0x019803a0
@ -39,16 +36,6 @@
#define ARCH_ID_AT91M40807 0x14080745
#define ARCH_ID_AT91R40008 0x44000840
static inline unsigned long at91_cpu_identify(void)
{
return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION);
}
static inline unsigned long at91_cpu_fully_identify(void)
{
return at91_sys_read(AT91_DBGU_CIDR);
}
#define ARCH_EXID_AT91SAM9M11 0x00000001
#define ARCH_EXID_AT91SAM9M10 0x00000002
#define ARCH_EXID_AT91SAM9G46 0x00000003
@ -60,40 +47,80 @@ static inline unsigned long at91_cpu_fully_identify(void)
#define ARCH_EXID_AT91SAM9G25 0x00000003
#define ARCH_EXID_AT91SAM9X25 0x00000004
static inline unsigned long at91_exid_identify(void)
{
return at91_sys_read(AT91_DBGU_EXID);
}
#define ARCH_FAMILY_AT91X92 0x09200000
#define ARCH_FAMILY_AT91SAM9 0x01900000
#define ARCH_FAMILY_AT91SAM9XE 0x02900000
static inline unsigned long at91_arch_identify(void)
{
return (at91_sys_read(AT91_DBGU_CIDR) & AT91_CIDR_ARCH);
}
#ifdef CONFIG_ARCH_AT91CAP9
#include <mach/at91_pmc.h>
/* PMC revision */
#define ARCH_REVISION_CAP9_B 0x399
#define ARCH_REVISION_CAP9_C 0x601
static inline unsigned long at91cap9_rev_identify(void)
{
return (at91_sys_read(AT91_PMC_VER));
}
#endif
#ifdef CONFIG_ARCH_AT91RM9200
extern int rm9200_type;
/* RM9200 type */
#define ARCH_REVISON_9200_BGA (0 << 0)
#define ARCH_REVISON_9200_PQFP (1 << 0)
#define cpu_is_at91rm9200() (at91_cpu_identify() == ARCH_ID_AT91RM9200)
#define cpu_is_at91rm9200_bga() (!cpu_is_at91rm9200_pqfp())
#define cpu_is_at91rm9200_pqfp() (cpu_is_at91rm9200() && rm9200_type & ARCH_REVISON_9200_PQFP)
enum at91_soc_type {
/* 920T */
AT91_SOC_RM9200,
/* CAP */
AT91_SOC_CAP9,
/* SAM92xx */
AT91_SOC_SAM9260, AT91_SOC_SAM9261, AT91_SOC_SAM9263,
/* SAM9Gxx */
AT91_SOC_SAM9G10, AT91_SOC_SAM9G20, AT91_SOC_SAM9G45,
/* SAM9RL */
AT91_SOC_SAM9RL,
/* SAM9X5 */
AT91_SOC_SAM9X5,
/* Unknown type */
AT91_SOC_NONE
};
enum at91_soc_subtype {
/* RM9200 */
AT91_SOC_RM9200_BGA, AT91_SOC_RM9200_PQFP,
/* CAP9 */
AT91_SOC_CAP9_REV_B, AT91_SOC_CAP9_REV_C,
/* SAM9260 */
AT91_SOC_SAM9XE,
/* SAM9G45 */
AT91_SOC_SAM9G45ES, AT91_SOC_SAM9M10, AT91_SOC_SAM9G46, AT91_SOC_SAM9M11,
/* SAM9X5 */
AT91_SOC_SAM9G15, AT91_SOC_SAM9G35, AT91_SOC_SAM9X35,
AT91_SOC_SAM9G25, AT91_SOC_SAM9X25,
/* Unknown subtype */
AT91_SOC_SUBTYPE_NONE
};
struct at91_socinfo {
unsigned int type, subtype;
unsigned int cidr, exid;
};
extern struct at91_socinfo at91_soc_initdata;
const char *at91_get_soc_type(struct at91_socinfo *c);
const char *at91_get_soc_subtype(struct at91_socinfo *c);
static inline int at91_soc_is_detected(void)
{
return at91_soc_initdata.type != AT91_SOC_NONE;
}
#ifdef CONFIG_ARCH_AT91RM9200
#define cpu_is_at91rm9200() (at91_soc_initdata.type == AT91_SOC_RM9200)
#define cpu_is_at91rm9200_bga() (at91_soc_initdata.subtype == AT91_SOC_RM9200_BGA)
#define cpu_is_at91rm9200_pqfp() (at91_soc_initdata.subtype == AT91_SOC_RM9200_PQFP)
#else
#define cpu_is_at91rm9200() (0)
#define cpu_is_at91rm9200_bga() (0)
@ -101,52 +128,49 @@ extern int rm9200_type;
#endif
#ifdef CONFIG_ARCH_AT91SAM9260
#define cpu_is_at91sam9xe() (at91_arch_identify() == ARCH_FAMILY_AT91SAM9XE)
#define cpu_is_at91sam9260() ((at91_cpu_identify() == ARCH_ID_AT91SAM9260) || cpu_is_at91sam9xe())
#define cpu_is_at91sam9xe() (at91_soc_initdata.subtype == AT91_SOC_SAM9XE)
#define cpu_is_at91sam9260() (at91_soc_initdata.type == AT91_SOC_SAM9260)
#else
#define cpu_is_at91sam9xe() (0)
#define cpu_is_at91sam9260() (0)
#endif
#ifdef CONFIG_ARCH_AT91SAM9G20
#define cpu_is_at91sam9g20() (at91_cpu_identify() == ARCH_ID_AT91SAM9G20)
#define cpu_is_at91sam9g20() (at91_soc_initdata.type == AT91_SOC_SAM9G20)
#else
#define cpu_is_at91sam9g20() (0)
#endif
#ifdef CONFIG_ARCH_AT91SAM9261
#define cpu_is_at91sam9261() (at91_cpu_identify() == ARCH_ID_AT91SAM9261)
#define cpu_is_at91sam9261() (at91_soc_initdata.type == AT91_SOC_SAM9261)
#else
#define cpu_is_at91sam9261() (0)
#endif
#ifdef CONFIG_ARCH_AT91SAM9G10
#define cpu_is_at91sam9g10() ((at91_cpu_identify() & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10)
#define cpu_is_at91sam9g10() (at91_soc_initdata.type == AT91_SOC_SAM9G10)
#else
#define cpu_is_at91sam9g10() (0)
#endif
#ifdef CONFIG_ARCH_AT91SAM9263
#define cpu_is_at91sam9263() (at91_cpu_identify() == ARCH_ID_AT91SAM9263)
#define cpu_is_at91sam9263() (at91_soc_initdata.type == AT91_SOC_SAM9263)
#else
#define cpu_is_at91sam9263() (0)
#endif
#ifdef CONFIG_ARCH_AT91SAM9RL
#define cpu_is_at91sam9rl() (at91_cpu_identify() == ARCH_ID_AT91SAM9RL64)
#define cpu_is_at91sam9rl() (at91_soc_initdata.type == AT91_SOC_SAM9RL)
#else
#define cpu_is_at91sam9rl() (0)
#endif
#ifdef CONFIG_ARCH_AT91SAM9G45
#define cpu_is_at91sam9g45() (at91_cpu_identify() == ARCH_ID_AT91SAM9G45)
#define cpu_is_at91sam9g45es() (at91_cpu_fully_identify() == ARCH_ID_AT91SAM9G45ES)
#define cpu_is_at91sam9m10() (cpu_is_at91sam9g45() && \
(at91_exid_identify() == ARCH_EXID_AT91SAM9M10))
#define cpu_is_at91sam9m46() (cpu_is_at91sam9g45() && \
(at91_exid_identify() == ARCH_EXID_AT91SAM9G46))
#define cpu_is_at91sam9m11() (cpu_is_at91sam9g45() && \
(at91_exid_identify() == ARCH_EXID_AT91SAM9M11))
#define cpu_is_at91sam9g45() (at91_soc_initdata.type == AT91_SOC_SAM9G45)
#define cpu_is_at91sam9g45es() (at91_soc_initdata.subtype == AT91_SOC_SAM9G45ES)
#define cpu_is_at91sam9m10() (at91_soc_initdata.subtype == AT91_SOC_SAM9M10)
#define cpu_is_at91sam9g46() (at91_soc_initdata.subtype == AT91_SOC_SAM9G46)
#define cpu_is_at91sam9m11() (at91_soc_initdata.subtype == AT91_SOC_SAM9M11)
#else
#define cpu_is_at91sam9g45() (0)
#define cpu_is_at91sam9g45es() (0)
@ -156,17 +180,12 @@ extern int rm9200_type;
#endif
#ifdef CONFIG_ARCH_AT91SAM9X5
#define cpu_is_at91sam9x5() (at91_cpu_identify() == ARCH_ID_AT91SAM9X5)
#define cpu_is_at91sam9g15() (cpu_is_at91sam9x5() && \
(at91_exid_identify() == ARCH_EXID_AT91SAM9G15))
#define cpu_is_at91sam9g35() (cpu_is_at91sam9x5() && \
(at91_exid_identify() == ARCH_EXID_AT91SAM9G35))
#define cpu_is_at91sam9x35() (cpu_is_at91sam9x5() && \
(at91_exid_identify() == ARCH_EXID_AT91SAM9X35))
#define cpu_is_at91sam9g25() (cpu_is_at91sam9x5() && \
(at91_exid_identify() == ARCH_EXID_AT91SAM9G25))
#define cpu_is_at91sam9x25() (cpu_is_at91sam9x5() && \
(at91_exid_identify() == ARCH_EXID_AT91SAM9X25))
#define cpu_is_at91sam9x5() (at91_soc_initdata.type == AT91_SOC_SAM9X5)
#define cpu_is_at91sam9g15() (at91_soc_initdata.subtype == AT91_SOC_SAM9G15)
#define cpu_is_at91sam9g35() (at91_soc_initdata.subtype == AT91_SOC_SAM9G35)
#define cpu_is_at91sam9x35() (at91_soc_initdata.subtype == AT91_SOC_SAM9X35)
#define cpu_is_at91sam9g25() (at91_soc_initdata.subtype == AT91_SOC_SAM9G25)
#define cpu_is_at91sam9x25() (at91_soc_initdata.subtype == AT91_SOC_SAM9X25)
#else
#define cpu_is_at91sam9x5() (0)
#define cpu_is_at91sam9g15() (0)
@ -177,9 +196,9 @@ extern int rm9200_type;
#endif
#ifdef CONFIG_ARCH_AT91CAP9
#define cpu_is_at91cap9() (at91_cpu_identify() == ARCH_ID_AT91CAP9)
#define cpu_is_at91cap9_revB() (at91cap9_rev_identify() == ARCH_REVISION_CAP9_B)
#define cpu_is_at91cap9_revC() (at91cap9_rev_identify() == ARCH_REVISION_CAP9_C)
#define cpu_is_at91cap9() (at91_soc_initdata.type == AT91_SOC_CAP9)
#define cpu_is_at91cap9_revB() (at91_soc_initdata.subtype == AT91_SOC_CAP9_REV_B)
#define cpu_is_at91cap9_revC() (at91_soc_initdata.subtype == AT91_SOC_CAP9_REV_C)
#else
#define cpu_is_at91cap9() (0)
#define cpu_is_at91cap9_revB() (0)
@ -192,4 +211,4 @@ extern int rm9200_type;
*/
#define cpu_is_at32ap7000() (0)
#endif
#endif /* __MACH_CPU_H__ */

14
arch/arm/mach-at91/include/mach/debug-macro.S
View File

@ -15,23 +15,23 @@
#include <mach/at91_dbgu.h>
.macro addruart, rp, rv
ldr \rp, =(AT91_BASE_SYS + AT91_DBGU) @ System peripherals (phys address)
ldr \rv, =(AT91_VA_BASE_SYS + AT91_DBGU) @ System peripherals (virt address)
ldr \rp, =(AT91_BASE_SYS + AT91_DBGU) @ System peripherals (phys address)
ldr \rv, =(AT91_VA_BASE_SYS + AT91_DBGU) @ System peripherals (virt address)
.endm
.macro senduart,rd,rx
strb \rd, [\rx, #(AT91_DBGU_THR - AT91_DBGU)] @ Write to Transmitter Holding Register
strb \rd, [\rx, #(AT91_DBGU_THR)] @ Write to Transmitter Holding Register
.endm
.macro waituart,rd,rx
1001: ldr \rd, [\rx, #(AT91_DBGU_SR - AT91_DBGU)] @ Read Status Register
tst \rd, #AT91_DBGU_TXRDY @ DBGU_TXRDY = 1 when ready to transmit
1001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register
tst \rd, #AT91_DBGU_TXRDY @ DBGU_TXRDY = 1 when ready to transmit
beq 1001b
.endm
.macro busyuart,rd,rx
1001: ldr \rd, [\rx, #(AT91_DBGU_SR - AT91_DBGU)] @ Read Status Register
tst \rd, #AT91_DBGU_TXEMPTY @ DBGU_TXEMPTY = 1 when transmission complete
1001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register
tst \rd, #AT91_DBGU_TXEMPTY @ DBGU_TXEMPTY = 1 when transmission complete
beq 1001b
.endm

14
arch/arm/mach-at91/include/mach/hardware.h
View File

@ -36,6 +36,20 @@
#error "Unsupported AT91 processor"
#endif
#if !defined(CONFIG_ARCH_AT91X40)
/*
* On all at91 except rm9200 and x40 have the System Controller starts
* at address 0xffffc000 and has a size of 16KiB.
*
* On rm9200 it's start at 0xfffe4000 of 111KiB with non reserved data starting
* at 0xfffff000
*
* Removes the individual definitions of AT91_BASE_SYS and
* replaces them with a common version at base 0xfffffc000 and size 16KiB
* and map the same memory space
*/
#define AT91_BASE_SYS 0xffffc000
#endif
/*
* Peripheral identifiers/interrupts.

11
arch/arm/mach-at91/include/mach/io.h
View File

@ -21,14 +21,23 @@
#ifndef __ASM_ARCH_IO_H
#define __ASM_ARCH_IO_H
#include <mach/hardware.h>
#define IO_SPACE_LIMIT 0xFFFFFFFF
#define __io(a) __typesafe_io(a)
#define __mem_pci(a) (a)
#ifndef __ASSEMBLY__
#ifndef CONFIG_ARCH_AT91X40
#define __arch_ioremap at91_ioremap
#define __arch_iounmap at91_iounmap
#endif
void __iomem *at91_ioremap(unsigned long phys, size_t size, unsigned int type);
void at91_iounmap(volatile void __iomem *addr);
static inline unsigned int at91_sys_read(unsigned int reg_offset)
{
void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS;

297
arch/arm/mach-at91/setup.c Normal file
View File

@ -0,0 +1,297 @@
/*
* Copyright (C) 2007 Atmel Corporation.
* Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
* Under GPLv2
*/
#include <linux/module.h>
#include <linux/io.h>
#include <linux/mm.h>
#include <asm/mach/map.h>
#include <mach/hardware.h>
#include <mach/cpu.h>
#include <mach/at91_dbgu.h>
#include <mach/at91_pmc.h>
#include "soc.h"
#include "generic.h"
struct at91_init_soc __initdata at91_boot_soc;
struct at91_socinfo at91_soc_initdata;
EXPORT_SYMBOL(at91_soc_initdata);
void __init at91rm9200_set_type(int type)
{
if (type == ARCH_REVISON_9200_PQFP)
at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
else
at91_soc_initdata.subtype = AT91_SOC_RM9200_PQFP;
}
void __init at91_init_irq_default(void)
{
at91_init_interrupts(at91_boot_soc.default_irq_priority);
}
void __init at91_init_interrupts(unsigned int *priority)
{
/* Initialize the AIC interrupt controller */
at91_aic_init(priority);
/* Enable GPIO interrupts */
at91_gpio_irq_setup();
}
static struct map_desc sram_desc[2] __initdata;
void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
{
struct map_desc *desc = &sram_desc[bank];
desc->virtual = AT91_IO_VIRT_BASE - length;
if (bank > 0)
desc->virtual -= sram_desc[bank - 1].length;
desc->pfn = __phys_to_pfn(base);
desc->length = length;
desc->type = MT_DEVICE;
pr_info("AT91: sram at 0x%lx of 0x%x mapped at 0x%lx\n",
base, length, desc->virtual);
iotable_init(desc, 1);
}
static struct map_desc at91_io_desc __initdata = {
.virtual = AT91_VA_BASE_SYS,
.pfn = __phys_to_pfn(AT91_BASE_SYS),
.length = SZ_16K,
.type = MT_DEVICE,
};
void __iomem *at91_ioremap(unsigned long p, size_t size, unsigned int type)
{
if (p >= AT91_BASE_SYS && p <= (AT91_BASE_SYS + SZ_16K - 1))
return (void __iomem *)AT91_IO_P2V(p);
return __arm_ioremap_caller(p, size, type, __builtin_return_address(0));
}
EXPORT_SYMBOL(at91_ioremap);
void at91_iounmap(volatile void __iomem *addr)
{
unsigned long virt = (unsigned long)addr;
if (virt >= VMALLOC_START && virt < VMALLOC_END)
__iounmap(addr);
}
EXPORT_SYMBOL(at91_iounmap);
#define AT91_DBGU0 0xfffff200
#define AT91_DBGU1 0xffffee00
static void __init soc_detect(u32 dbgu_base)
{
u32 cidr, socid;
cidr = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_CIDR);
socid = cidr & ~AT91_CIDR_VERSION;
switch (socid) {
case ARCH_ID_AT91CAP9: {
#ifdef CONFIG_AT91_PMC_UNIT
u32 pmc_ver = at91_sys_read(AT91_PMC_VER);
if (pmc_ver == ARCH_REVISION_CAP9_B)
at91_soc_initdata.subtype = AT91_SOC_CAP9_REV_B;
else if (pmc_ver == ARCH_REVISION_CAP9_C)
at91_soc_initdata.subtype = AT91_SOC_CAP9_REV_C;
#endif
at91_soc_initdata.type = AT91_SOC_CAP9;
at91_boot_soc = at91cap9_soc;
break;
}
case ARCH_ID_AT91RM9200:
at91_soc_initdata.type = AT91_SOC_RM9200;
at91_boot_soc = at91rm9200_soc;
break;
case ARCH_ID_AT91SAM9260:
at91_soc_initdata.type = AT91_SOC_SAM9260;
at91_boot_soc = at91sam9260_soc;
break;
case ARCH_ID_AT91SAM9261:
at91_soc_initdata.type = AT91_SOC_SAM9261;
at91_boot_soc = at91sam9261_soc;
break;
case ARCH_ID_AT91SAM9263:
at91_soc_initdata.type = AT91_SOC_SAM9263;
at91_boot_soc = at91sam9263_soc;
break;
case ARCH_ID_AT91SAM9G20:
at91_soc_initdata.type = AT91_SOC_SAM9G20;
at91_boot_soc = at91sam9260_soc;
break;
case ARCH_ID_AT91SAM9G45:
at91_soc_initdata.type = AT91_SOC_SAM9G45;
if (cidr == ARCH_ID_AT91SAM9G45ES)
at91_soc_initdata.subtype = AT91_SOC_SAM9G45ES;
at91_boot_soc = at91sam9g45_soc;
break;
case ARCH_ID_AT91SAM9RL64:
at91_soc_initdata.type = AT91_SOC_SAM9RL;
at91_boot_soc = at91sam9rl_soc;
break;
case ARCH_ID_AT91SAM9X5:
at91_soc_initdata.type = AT91_SOC_SAM9X5;
at91_boot_soc = at91sam9x5_soc;
break;
}
/* at91sam9g10 */
if ((cidr & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
at91_soc_initdata.type = AT91_SOC_SAM9G10;
at91_boot_soc = at91sam9261_soc;
}
/* at91sam9xe */
else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) {
at91_soc_initdata.type = AT91_SOC_SAM9260;
at91_soc_initdata.subtype = AT91_SOC_SAM9XE;
at91_boot_soc = at91sam9260_soc;
}
if (!at91_soc_is_detected())
return;
at91_soc_initdata.cidr = cidr;
/* sub version of soc */
at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
if (at91_soc_initdata.type == AT91_SOC_SAM9G45) {
switch (at91_soc_initdata.exid) {
case ARCH_EXID_AT91SAM9M10:
at91_soc_initdata.subtype = AT91_SOC_SAM9M10;
break;
case ARCH_EXID_AT91SAM9G46:
at91_soc_initdata.subtype = AT91_SOC_SAM9G46;
break;
case ARCH_EXID_AT91SAM9M11:
at91_soc_initdata.subtype = AT91_SOC_SAM9M11;
break;
}
}
if (at91_soc_initdata.type == AT91_SOC_SAM9X5) {
switch (at91_soc_initdata.exid) {
case ARCH_EXID_AT91SAM9G15:
at91_soc_initdata.subtype = AT91_SOC_SAM9G15;
break;
case ARCH_EXID_AT91SAM9G35:
at91_soc_initdata.subtype = AT91_SOC_SAM9G35;
break;
case ARCH_EXID_AT91SAM9X35:
at91_soc_initdata.subtype = AT91_SOC_SAM9X35;
break;
case ARCH_EXID_AT91SAM9G25:
at91_soc_initdata.subtype = AT91_SOC_SAM9G25;
break;
case ARCH_EXID_AT91SAM9X25:
at91_soc_initdata.subtype = AT91_SOC_SAM9X25;
break;
}
}
}
static const char *soc_name[] = {
[AT91_SOC_RM9200] = "at91rm9200",
[AT91_SOC_CAP9] = "at91cap9",
[AT91_SOC_SAM9260] = "at91sam9260",
[AT91_SOC_SAM9261] = "at91sam9261",
[AT91_SOC_SAM9263] = "at91sam9263",
[AT91_SOC_SAM9G10] = "at91sam9g10",
[AT91_SOC_SAM9G20] = "at91sam9g20",
[AT91_SOC_SAM9G45] = "at91sam9g45",
[AT91_SOC_SAM9RL] = "at91sam9rl",
[AT91_SOC_SAM9X5] = "at91sam9x5",
[AT91_SOC_NONE] = "Unknown"
};
const char *at91_get_soc_type(struct at91_socinfo *c)
{
return soc_name[c->type];
}
EXPORT_SYMBOL(at91_get_soc_type);
static const char *soc_subtype_name[] = {
[AT91_SOC_RM9200_BGA] = "at91rm9200 BGA",
[AT91_SOC_RM9200_PQFP] = "at91rm9200 PQFP",
[AT91_SOC_CAP9_REV_B] = "at91cap9 revB",
[AT91_SOC_CAP9_REV_C] = "at91cap9 revC",
[AT91_SOC_SAM9XE] = "at91sam9xe",
[AT91_SOC_SAM9G45ES] = "at91sam9g45es",
[AT91_SOC_SAM9M10] = "at91sam9m10",
[AT91_SOC_SAM9G46] = "at91sam9g46",
[AT91_SOC_SAM9M11] = "at91sam9m11",
[AT91_SOC_SAM9G15] = "at91sam9g15",
[AT91_SOC_SAM9G35] = "at91sam9g35",
[AT91_SOC_SAM9X35] = "at91sam9x35",
[AT91_SOC_SAM9G25] = "at91sam9g25",
[AT91_SOC_SAM9X25] = "at91sam9x25",
[AT91_SOC_SUBTYPE_NONE] = "Unknown"
};
const char *at91_get_soc_subtype(struct at91_socinfo *c)
{
return soc_subtype_name[c->subtype];
}
EXPORT_SYMBOL(at91_get_soc_subtype);
void __init at91_map_io(void)
{
/* Map peripherals */
iotable_init(&at91_io_desc, 1);
at91_soc_initdata.type = AT91_SOC_NONE;
at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
soc_detect(AT91_DBGU0);
if (!at91_soc_is_detected())
soc_detect(AT91_DBGU1);
if (!at91_soc_is_detected())
panic("AT91: Impossible to detect the SOC type");
pr_info("AT91: Detected soc type: %s\n",
at91_get_soc_type(&at91_soc_initdata));
pr_info("AT91: Detected soc subtype: %s\n",
at91_get_soc_subtype(&at91_soc_initdata));
if (!at91_soc_is_enabled())
panic("AT91: Soc not enabled");
if (at91_boot_soc.map_io)
at91_boot_soc.map_io();
}
void __init at91_initialize(unsigned long main_clock)
{
/* Init clock subsystem */
at91_clock_init(main_clock);
/* Register the processor-specific clocks */
at91_boot_soc.register_clocks();
at91_boot_soc.init();
}

59
arch/arm/mach-at91/soc.h Normal file
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/*
* Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
* Under GPLv2
*/
struct at91_init_soc {
unsigned int *default_irq_priority;
void (*map_io)(void);
void (*register_clocks)(void);
void (*init)(void);
};
extern struct at91_init_soc at91_boot_soc;
extern struct at91_init_soc at91cap9_soc;
extern struct at91_init_soc at91rm9200_soc;
extern struct at91_init_soc at91sam9260_soc;
extern struct at91_init_soc at91sam9261_soc;
extern struct at91_init_soc at91sam9263_soc;
extern struct at91_init_soc at91sam9g45_soc;
extern struct at91_init_soc at91sam9rl_soc;
extern struct at91_init_soc at91sam9x5_soc;
static inline int at91_soc_is_enabled(void)
{
return at91_boot_soc.init != NULL;
}
#if !defined(CONFIG_ARCH_AT91CAP9)
#define at91cap9_soc at91_boot_soc
#endif
#if !defined(CONFIG_ARCH_AT91RM9200)
#define at91rm9200_soc at91_boot_soc
#endif
#if !(defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20))
#define at91sam9260_soc at91_boot_soc
#endif
#if !(defined(CONFIG_ARCH_AT91SAM9261) || defined(CONFIG_ARCH_AT91SAM9G10))
#define at91sam9261_soc at91_boot_soc
#endif
#if !defined(CONFIG_ARCH_AT91SAM9263)
#define at91sam9263_soc at91_boot_soc
#endif
#if !defined(CONFIG_ARCH_AT91SAM9G45)
#define at91sam9g45_soc at91_boot_soc
#endif
#if !defined(CONFIG_ARCH_AT91SAM9RL)
#define at91sam9rl_soc at91_boot_soc
#endif
#if !defined(CONFIG_ARCH_AT91SAM9X5)
#define at91sam9x5_soc at91_boot_soc
#endif