MN10300: Add CPU register bits for AM34
Add CPU register declarations for the AM34 subarch. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
This commit is contained in:
Akira Takeuchi
David Howells
parent
06019be31a
commit
8fbbf7c76a
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@ -17,6 +17,7 @@ config AM33_3
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config AM34_2
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def_bool n
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select MN10300_HAS_ATOMIC_OPS_UNIT
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config MMU
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def_bool y
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@ -124,6 +125,12 @@ config MN10300_CPU_AM33V2
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endchoice
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config MN10300_HAS_ATOMIC_OPS_UNIT
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def_bool n
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help
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This should be enabled if the processor has an atomic ops unit
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capable of doing LL/SC equivalent operations.
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config FPU
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bool "FPU present"
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default y
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@ -15,7 +15,6 @@
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#include <linux/types.h>
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#endif
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#ifdef CONFIG_MN10300_CPU_AM33V2
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/* we tell the compiler to pretend to be AM33 so that it doesn't try and use
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* the FP regs, but tell the assembler that we're actually allowed AM33v2
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* instructions */
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@ -24,7 +23,6 @@ asm(" .am33_2\n");
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#else
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.am33_2
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#endif
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#endif
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#ifdef __KERNEL__
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@ -58,6 +56,9 @@ asm(" .am33_2\n");
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#define EPSW_nAR 0x00040000 /* register bank control */
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#define EPSW_ML 0x00080000 /* monitor level */
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#define EPSW_FE 0x00100000 /* FPU enable */
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#define EPSW_IM_SHIFT 8 /* EPSW_IM_SHIFT determines the interrupt mode */
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#define NUM2EPSW_IM(num) ((num) << EPSW_IM_SHIFT)
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/* FPU registers */
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#define FPCR_EF_I 0x00000001 /* inexact result FPU exception flag */
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@ -99,9 +100,11 @@ asm(" .am33_2\n");
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#define CPUREV __SYSREGC(0xc0000050, u32) /* CPU revision register */
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#define CPUREV_TYPE 0x0000000f /* CPU type */
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#define CPUREV_TYPE_S 0
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#define CPUREV_TYPE_AM33V1 0x00000000 /* - AM33 V1 core, AM33/1.00 arch */
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#define CPUREV_TYPE_AM33V2 0x00000001 /* - AM33 V2 core, AM33/2.00 arch */
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#define CPUREV_TYPE_AM34V1 0x00000002 /* - AM34 V1 core, AM33/2.00 arch */
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#define CPUREV_TYPE_AM33_1 0x00000000 /* - AM33-1 core, AM33/1.00 arch */
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#define CPUREV_TYPE_AM33_2 0x00000001 /* - AM33-2 core, AM33/2.00 arch */
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#define CPUREV_TYPE_AM34_1 0x00000002 /* - AM34-1 core, AM33/2.00 arch */
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#define CPUREV_TYPE_AM33_3 0x00000003 /* - AM33-3 core, AM33/2.00 arch */
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#define CPUREV_TYPE_AM34_2 0x00000004 /* - AM34-2 core, AM33/3.00 arch */
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#define CPUREV_REVISION 0x000000f0 /* CPU revision */
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#define CPUREV_REVISION_S 4
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#define CPUREV_ICWAY 0x00000f00 /* number of instruction cache ways */
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@ -180,6 +183,21 @@ asm(" .am33_2\n");
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#define CHCTR_ICWMD 0x0f00 /* instruction cache way mode */
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#define CHCTR_DCWMD 0xf000 /* data cache way mode */
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#ifdef CONFIG_AM34_2
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#define ICIVCR __SYSREG(0xc0000c00, u32) /* icache area invalidate control */
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#define ICIVCR_ICIVBSY 0x00000008 /* icache area invalidate busy */
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#define ICIVCR_ICI 0x00000001 /* icache area invalidate */
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#define ICIVMR __SYSREG(0xc0000c04, u32) /* icache area invalidate mask */
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#define DCPGCR __SYSREG(0xc0000c10, u32) /* data cache area purge control */
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#define DCPGCR_DCPGBSY 0x00000008 /* data cache area purge busy */
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#define DCPGCR_DCP 0x00000002 /* data cache area purge */
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#define DCPGCR_DCI 0x00000001 /* data cache area invalidate */
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#define DCPGMR __SYSREG(0xc0000c14, u32) /* data cache area purge mask */
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#endif /* CONFIG_AM34_2 */
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/* MMU control registers */
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#define MMUCTR __SYSREG(0xc0000090, u32) /* MMU control register */
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#define MMUCTR_IRP 0x0000003f /* instruction TLB replace pointer */
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@ -203,6 +221,9 @@ asm(" .am33_2\n");
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#define MMUCTR_DTL_LOCK0_3 0x03000000 /* - entry 0-3 locked */
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#define MMUCTR_DTL_LOCK0_7 0x04000000 /* - entry 0-7 locked */
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#define MMUCTR_DTL_LOCK0_15 0x05000000 /* - entry 0-15 locked */
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#ifdef CONFIG_AM34_2
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#define MMUCTR_WTE 0x80000000 /* write-through cache TLB entry bit enable */
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#endif
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#define PIDR __SYSREG(0xc0000094, u16) /* PID register */
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#define PIDR_PID 0x00ff /* process identifier */
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@ -285,6 +306,47 @@ asm(" .am33_2\n");
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#define MMUFCR_xFC_PR_RWK_RWU 0x01c0 /* - R/W kernel and R/W user */
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#define MMUFCR_xFC_ILLADDR 0x0200 /* illegal address excep flag */
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#ifdef CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT
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/* atomic operation registers */
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#define AAR __SYSREG(0xc0000a00, u32) /* cacheable address */
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#define AAR2 __SYSREG(0xc0000a04, u32) /* uncacheable address */
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#define ADR __SYSREG(0xc0000a08, u32) /* data */
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#define ASR __SYSREG(0xc0000a0c, u32) /* status */
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#define AARU __SYSREG(0xd400aa00, u32) /* user address */
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#define ADRU __SYSREG(0xd400aa08, u32) /* user data */
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#define ASRU __SYSREG(0xd400aa0c, u32) /* user status */
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#define ASR_RW 0x00000008 /* read */
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#define ASR_BW 0x00000004 /* bus error */
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#define ASR_IW 0x00000002 /* interrupt */
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#define ASR_LW 0x00000001 /* bus lock */
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#define ASRU_RW ASR_RW /* read */
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#define ASRU_BW ASR_BW /* bus error */
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#define ASRU_IW ASR_IW /* interrupt */
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#define ASRU_LW ASR_LW /* bus lock */
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/* in inline ASM, we stick the base pointer in to a reg and use offsets from
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* it */
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#define ATOMIC_OPS_BASE_ADDR 0xc0000a00
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#ifndef __ASSEMBLY__
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asm(
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"_AAR = 0\n"
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"_AAR2 = 4\n"
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"_ADR = 8\n"
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"_ASR = 12\n");
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#else
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#define _AAR 0
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#define _AAR2 4
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#define _ADR 8
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#define _ASR 12
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#endif
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/* physical page address for userspace atomic operations registers */
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#define USER_ATOMIC_OPS_PAGE_ADDR 0xd400a000
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#endif /* CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT */
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#endif /* __KERNEL__ */
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#endif /* _ASM_CPU_REGS_H */
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