ahci-imx: Port to library-ised ahci_platform
This avoids the ugliness of creating a nested platform device from probe. While moving it around anyways, move the mk6q phy init code from probe to imx_sata_enable, as the phy needs to be re-initialized on resume too, otherwise the drive won't be recognized after resume. Tested on a wandboard i.mx6 quad. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Tejun Heo <tj@kernel.org>
This commit is contained in:
Hans de Goede
Tejun Heo
parent
c5754b5220
commit
90870d79d4
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@ -5,8 +5,9 @@ Each SATA controller should have its own node.
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Required properties:
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- compatible : compatible list, one of "snps,spear-ahci",
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"snps,exynos5440-ahci", "ibm,476gtr-ahci", or
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"allwinner,sun4i-a10-ahci"
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"snps,exynos5440-ahci", "ibm,476gtr-ahci",
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"allwinner,sun4i-a10-ahci", "fsl,imx53-ahci" or
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"fsl,imx6q-ahci"
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- interrupts : <interrupt mapping for SATA IRQ>
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- reg : <registers mapping>
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@ -15,6 +16,10 @@ Optional properties:
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- clocks : a list of phandle + clock specifier pairs
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- target-supply : regulator for SATA target power
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"fsl,imx53-ahci", "fsl,imx6q-ahci" required properties:
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- clocks : must contain the sata, sata_ref and ahb clocks
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- clock-names : must contain "ahb" for the ahb clock
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Examples:
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sata@ffe08000 {
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compatible = "snps,spear-ahci";
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@ -42,13 +42,7 @@ enum ahci_imx_type {
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struct imx_ahci_priv {
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struct platform_device *ahci_pdev;
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enum ahci_imx_type type;
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/* i.MX53 clock */
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struct clk *sata_gate_clk;
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/* Common clock */
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struct clk *sata_ref_clk;
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struct clk *ahb_clk;
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struct regmap *gpr;
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bool no_device;
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bool first_time;
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@ -58,288 +52,32 @@ static int ahci_imx_hotplug;
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module_param_named(hotplug, ahci_imx_hotplug, int, 0644);
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MODULE_PARM_DESC(hotplug, "AHCI IMX hot-plug support (0=Don't support, 1=support)");
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static int imx_sata_clock_enable(struct device *dev)
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static void ahci_imx_host_stop(struct ata_host *host);
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static int imx_sata_enable(struct ahci_host_priv *hpriv)
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{
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struct imx_ahci_priv *imxpriv = dev_get_drvdata(dev->parent);
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struct imx_ahci_priv *imxpriv = hpriv->plat_data;
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int ret;
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if (imxpriv->type == AHCI_IMX53) {
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ret = clk_prepare_enable(imxpriv->sata_gate_clk);
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if (ret < 0) {
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dev_err(dev, "prepare-enable sata_gate clock err:%d\n",
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ret);
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if (imxpriv->no_device)
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return 0;
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if (hpriv->target_pwr) {
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ret = regulator_enable(hpriv->target_pwr);
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if (ret)
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return ret;
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}
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}
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ret = clk_prepare_enable(imxpriv->sata_ref_clk);
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if (ret < 0) {
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dev_err(dev, "prepare-enable sata_ref clock err:%d\n",
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ret);
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goto clk_err;
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}
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if (imxpriv->type == AHCI_IMX6Q) {
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regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
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IMX6Q_GPR13_SATA_MPLL_CLK_EN,
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IMX6Q_GPR13_SATA_MPLL_CLK_EN);
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}
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usleep_range(1000, 2000);
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return 0;
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clk_err:
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if (imxpriv->type == AHCI_IMX53)
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clk_disable_unprepare(imxpriv->sata_gate_clk);
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return ret;
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}
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static void imx_sata_clock_disable(struct device *dev)
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{
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struct imx_ahci_priv *imxpriv = dev_get_drvdata(dev->parent);
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if (imxpriv->type == AHCI_IMX6Q) {
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regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
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IMX6Q_GPR13_SATA_MPLL_CLK_EN,
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!IMX6Q_GPR13_SATA_MPLL_CLK_EN);
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}
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clk_disable_unprepare(imxpriv->sata_ref_clk);
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if (imxpriv->type == AHCI_IMX53)
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clk_disable_unprepare(imxpriv->sata_gate_clk);
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}
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static void ahci_imx_error_handler(struct ata_port *ap)
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{
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u32 reg_val;
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struct ata_device *dev;
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struct ata_host *host = dev_get_drvdata(ap->dev);
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struct ahci_host_priv *hpriv = host->private_data;
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void __iomem *mmio = hpriv->mmio;
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struct imx_ahci_priv *imxpriv = dev_get_drvdata(ap->dev->parent);
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ahci_error_handler(ap);
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if (!(imxpriv->first_time) || ahci_imx_hotplug)
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return;
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imxpriv->first_time = false;
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ata_for_each_dev(dev, &ap->link, ENABLED)
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return;
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/*
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* Disable link to save power. An imx ahci port can't be recovered
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* without full reset once the pddq mode is enabled making it
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* impossible to use as part of libata LPM.
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*/
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reg_val = readl(mmio + PORT_PHY_CTL);
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writel(reg_val | PORT_PHY_CTL_PDDQ_LOC, mmio + PORT_PHY_CTL);
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imx_sata_clock_disable(ap->dev);
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imxpriv->no_device = true;
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}
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static int ahci_imx_softreset(struct ata_link *link, unsigned int *class,
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unsigned long deadline)
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{
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struct ata_port *ap = link->ap;
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struct imx_ahci_priv *imxpriv = dev_get_drvdata(ap->dev->parent);
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int ret = -EIO;
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if (imxpriv->type == AHCI_IMX53)
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ret = ahci_pmp_retry_srst_ops.softreset(link, class, deadline);
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else if (imxpriv->type == AHCI_IMX6Q)
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ret = ahci_ops.softreset(link, class, deadline);
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return ret;
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}
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static struct ata_port_operations ahci_imx_ops = {
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.inherits = &ahci_platform_ops,
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.error_handler = ahci_imx_error_handler,
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.softreset = ahci_imx_softreset,
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};
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static const struct ata_port_info ahci_imx_port_info = {
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.flags = AHCI_FLAG_COMMON,
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.pio_mask = ATA_PIO4,
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.udma_mask = ATA_UDMA6,
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.port_ops = &ahci_imx_ops,
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};
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static int imx_sata_init(struct device *dev, void __iomem *mmio)
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{
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int ret = 0;
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unsigned int reg_val;
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struct imx_ahci_priv *imxpriv = dev_get_drvdata(dev->parent);
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ret = imx_sata_clock_enable(dev);
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ret = ahci_platform_enable_clks(hpriv);
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if (ret < 0)
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return ret;
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/*
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* Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL,
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* and IP vendor specific register HOST_TIMER1MS.
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* Configure CAP_SSS (support stagered spin up).
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* Implement the port0.
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* Get the ahb clock rate, and configure the TIMER1MS register.
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*/
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reg_val = readl(mmio + HOST_CAP);
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if (!(reg_val & HOST_CAP_SSS)) {
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reg_val |= HOST_CAP_SSS;
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writel(reg_val, mmio + HOST_CAP);
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}
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reg_val = readl(mmio + HOST_PORTS_IMPL);
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if (!(reg_val & 0x1)) {
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reg_val |= 0x1;
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writel(reg_val, mmio + HOST_PORTS_IMPL);
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}
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reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000;
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writel(reg_val, mmio + HOST_TIMER1MS);
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return 0;
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}
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static void imx_sata_exit(struct device *dev)
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{
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imx_sata_clock_disable(dev);
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}
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static int imx_ahci_suspend(struct device *dev)
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{
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struct imx_ahci_priv *imxpriv = dev_get_drvdata(dev->parent);
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/*
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* If no_device is set, The CLKs had been gated off in the
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* initialization so don't do it again here.
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*/
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if (!imxpriv->no_device)
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imx_sata_clock_disable(dev);
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return 0;
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}
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static int imx_ahci_resume(struct device *dev)
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{
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struct imx_ahci_priv *imxpriv = dev_get_drvdata(dev->parent);
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int ret = 0;
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if (!imxpriv->no_device)
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ret = imx_sata_clock_enable(dev);
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return ret;
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}
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static struct ahci_platform_data imx_sata_pdata = {
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.init = imx_sata_init,
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.exit = imx_sata_exit,
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.ata_port_info = &ahci_imx_port_info,
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.suspend = imx_ahci_suspend,
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.resume = imx_ahci_resume,
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};
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static const struct of_device_id imx_ahci_of_match[] = {
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{ .compatible = "fsl,imx53-ahci", .data = (void *)AHCI_IMX53 },
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{ .compatible = "fsl,imx6q-ahci", .data = (void *)AHCI_IMX6Q },
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{},
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};
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MODULE_DEVICE_TABLE(of, imx_ahci_of_match);
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static int imx_ahci_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct resource *mem, *irq, res[2];
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const struct of_device_id *of_id;
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enum ahci_imx_type type;
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const struct ahci_platform_data *pdata = NULL;
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struct imx_ahci_priv *imxpriv;
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struct device *ahci_dev;
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struct platform_device *ahci_pdev;
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int ret;
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of_id = of_match_device(imx_ahci_of_match, dev);
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if (!of_id)
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return -EINVAL;
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type = (enum ahci_imx_type)of_id->data;
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pdata = &imx_sata_pdata;
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imxpriv = devm_kzalloc(dev, sizeof(*imxpriv), GFP_KERNEL);
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if (!imxpriv) {
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dev_err(dev, "can't alloc ahci_host_priv\n");
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return -ENOMEM;
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}
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ahci_pdev = platform_device_alloc("ahci", -1);
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if (!ahci_pdev)
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return -ENODEV;
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ahci_dev = &ahci_pdev->dev;
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ahci_dev->parent = dev;
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imxpriv->no_device = false;
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imxpriv->first_time = true;
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imxpriv->type = type;
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imxpriv->ahb_clk = devm_clk_get(dev, "ahb");
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if (IS_ERR(imxpriv->ahb_clk)) {
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dev_err(dev, "can't get ahb clock.\n");
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ret = PTR_ERR(imxpriv->ahb_clk);
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goto err_out;
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}
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if (type == AHCI_IMX53) {
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imxpriv->sata_gate_clk = devm_clk_get(dev, "sata_gate");
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if (IS_ERR(imxpriv->sata_gate_clk)) {
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dev_err(dev, "can't get sata_gate clock.\n");
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ret = PTR_ERR(imxpriv->sata_gate_clk);
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goto err_out;
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}
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}
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imxpriv->sata_ref_clk = devm_clk_get(dev, "sata_ref");
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if (IS_ERR(imxpriv->sata_ref_clk)) {
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dev_err(dev, "can't get sata_ref clock.\n");
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ret = PTR_ERR(imxpriv->sata_ref_clk);
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goto err_out;
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}
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imxpriv->ahci_pdev = ahci_pdev;
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platform_set_drvdata(pdev, imxpriv);
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mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
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if (!mem || !irq) {
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dev_err(dev, "no mmio/irq resource\n");
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ret = -ENOMEM;
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goto err_out;
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}
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res[0] = *mem;
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res[1] = *irq;
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ahci_dev->coherent_dma_mask = DMA_BIT_MASK(32);
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ahci_dev->dma_mask = &ahci_dev->coherent_dma_mask;
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ahci_dev->of_node = dev->of_node;
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if (type == AHCI_IMX6Q) {
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imxpriv->gpr = syscon_regmap_lookup_by_compatible(
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"fsl,imx6q-iomuxc-gpr");
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if (IS_ERR(imxpriv->gpr)) {
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dev_err(dev,
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"failed to find fsl,imx6q-iomux-gpr regmap\n");
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ret = PTR_ERR(imxpriv->gpr);
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goto err_out;
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}
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goto disable_regulator;
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if (imxpriv->type == AHCI_IMX6Q) {
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/*
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* Set PHY Paremeters, two steps to configure the GPR13,
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* set PHY Paremeters, two steps to configure the GPR13,
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* one write for rest of parameters, mask of first write
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* is 0x07fffffe, and the other one write for setting
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* the mpll_clk_en happens in imx_sata_clock_enable().
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* is 0x07ffffff, and the other one write for setting
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* the mpll_clk_en.
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*/
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regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
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IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK |
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@ -360,42 +98,227 @@ static int imx_ahci_probe(struct platform_device *pdev)
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IMX6Q_GPR13_SATA_TX_ATTEN_9_16 |
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IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB |
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IMX6Q_GPR13_SATA_TX_LVL_1_025_V);
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regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
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IMX6Q_GPR13_SATA_MPLL_CLK_EN,
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IMX6Q_GPR13_SATA_MPLL_CLK_EN);
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}
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ret = platform_device_add_resources(ahci_pdev, res, 2);
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if (ret)
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goto err_out;
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ret = platform_device_add_data(ahci_pdev, pdata, sizeof(*pdata));
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if (ret)
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goto err_out;
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ret = platform_device_add(ahci_pdev);
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if (ret) {
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err_out:
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platform_device_put(ahci_pdev);
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return ret;
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}
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usleep_range(1000, 2000);
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return 0;
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disable_regulator:
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if (hpriv->target_pwr)
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regulator_disable(hpriv->target_pwr);
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return ret;
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}
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static int imx_ahci_remove(struct platform_device *pdev)
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static void imx_sata_disable(struct ahci_host_priv *hpriv)
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{
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struct imx_ahci_priv *imxpriv = platform_get_drvdata(pdev);
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struct platform_device *ahci_pdev = imxpriv->ahci_pdev;
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struct imx_ahci_priv *imxpriv = hpriv->plat_data;
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if (imxpriv->no_device)
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return;
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if (imxpriv->type == AHCI_IMX6Q) {
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regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
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IMX6Q_GPR13_SATA_MPLL_CLK_EN,
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!IMX6Q_GPR13_SATA_MPLL_CLK_EN);
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}
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ahci_platform_disable_clks(hpriv);
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if (hpriv->target_pwr)
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regulator_disable(hpriv->target_pwr);
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}
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static void ahci_imx_error_handler(struct ata_port *ap)
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{
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u32 reg_val;
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struct ata_device *dev;
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struct ata_host *host = dev_get_drvdata(ap->dev);
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struct ahci_host_priv *hpriv = host->private_data;
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void __iomem *mmio = hpriv->mmio;
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struct imx_ahci_priv *imxpriv = hpriv->plat_data;
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ahci_error_handler(ap);
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if (!(imxpriv->first_time) || ahci_imx_hotplug)
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return;
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imxpriv->first_time = false;
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ata_for_each_dev(dev, &ap->link, ENABLED)
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return;
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/*
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* Disable link to save power. An imx ahci port can't be recovered
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* without full reset once the pddq mode is enabled making it
|
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* impossible to use as part of libata LPM.
|
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*/
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reg_val = readl(mmio + PORT_PHY_CTL);
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writel(reg_val | PORT_PHY_CTL_PDDQ_LOC, mmio + PORT_PHY_CTL);
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imx_sata_disable(hpriv);
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imxpriv->no_device = true;
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}
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static int ahci_imx_softreset(struct ata_link *link, unsigned int *class,
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unsigned long deadline)
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{
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struct ata_port *ap = link->ap;
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struct ata_host *host = dev_get_drvdata(ap->dev);
|
||||
struct ahci_host_priv *hpriv = host->private_data;
|
||||
struct imx_ahci_priv *imxpriv = hpriv->plat_data;
|
||||
int ret = -EIO;
|
||||
|
||||
if (imxpriv->type == AHCI_IMX53)
|
||||
ret = ahci_pmp_retry_srst_ops.softreset(link, class, deadline);
|
||||
else if (imxpriv->type == AHCI_IMX6Q)
|
||||
ret = ahci_ops.softreset(link, class, deadline);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct ata_port_operations ahci_imx_ops = {
|
||||
.inherits = &ahci_ops,
|
||||
.host_stop = ahci_imx_host_stop,
|
||||
.error_handler = ahci_imx_error_handler,
|
||||
.softreset = ahci_imx_softreset,
|
||||
};
|
||||
|
||||
static const struct ata_port_info ahci_imx_port_info = {
|
||||
.flags = AHCI_FLAG_COMMON,
|
||||
.pio_mask = ATA_PIO4,
|
||||
.udma_mask = ATA_UDMA6,
|
||||
.port_ops = &ahci_imx_ops,
|
||||
};
|
||||
|
||||
static const struct of_device_id imx_ahci_of_match[] = {
|
||||
{ .compatible = "fsl,imx53-ahci", .data = (void *)AHCI_IMX53 },
|
||||
{ .compatible = "fsl,imx6q-ahci", .data = (void *)AHCI_IMX6Q },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, imx_ahci_of_match);
|
||||
|
||||
static int imx_ahci_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
const struct of_device_id *of_id;
|
||||
struct ahci_host_priv *hpriv;
|
||||
struct imx_ahci_priv *imxpriv;
|
||||
unsigned int reg_val;
|
||||
int ret;
|
||||
|
||||
of_id = of_match_device(imx_ahci_of_match, dev);
|
||||
if (!of_id)
|
||||
return -EINVAL;
|
||||
|
||||
imxpriv = devm_kzalloc(dev, sizeof(*imxpriv), GFP_KERNEL);
|
||||
if (!imxpriv)
|
||||
return -ENOMEM;
|
||||
|
||||
imxpriv->no_device = false;
|
||||
imxpriv->first_time = true;
|
||||
imxpriv->type = (enum ahci_imx_type)of_id->data;
|
||||
imxpriv->ahb_clk = devm_clk_get(dev, "ahb");
|
||||
if (IS_ERR(imxpriv->ahb_clk)) {
|
||||
dev_err(dev, "can't get ahb clock.\n");
|
||||
return PTR_ERR(imxpriv->ahb_clk);
|
||||
}
|
||||
|
||||
if (imxpriv->type == AHCI_IMX6Q) {
|
||||
imxpriv->gpr = syscon_regmap_lookup_by_compatible(
|
||||
"fsl,imx6q-iomuxc-gpr");
|
||||
if (IS_ERR(imxpriv->gpr)) {
|
||||
dev_err(dev,
|
||||
"failed to find fsl,imx6q-iomux-gpr regmap\n");
|
||||
return PTR_ERR(imxpriv->gpr);
|
||||
}
|
||||
}
|
||||
|
||||
hpriv = ahci_platform_get_resources(pdev);
|
||||
if (IS_ERR(hpriv))
|
||||
return PTR_ERR(hpriv);
|
||||
|
||||
hpriv->plat_data = imxpriv;
|
||||
|
||||
ret = imx_sata_enable(hpriv);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/*
|
||||
* Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL,
|
||||
* and IP vendor specific register HOST_TIMER1MS.
|
||||
* Configure CAP_SSS (support stagered spin up).
|
||||
* Implement the port0.
|
||||
* Get the ahb clock rate, and configure the TIMER1MS register.
|
||||
*/
|
||||
reg_val = readl(hpriv->mmio + HOST_CAP);
|
||||
if (!(reg_val & HOST_CAP_SSS)) {
|
||||
reg_val |= HOST_CAP_SSS;
|
||||
writel(reg_val, hpriv->mmio + HOST_CAP);
|
||||
}
|
||||
reg_val = readl(hpriv->mmio + HOST_PORTS_IMPL);
|
||||
if (!(reg_val & 0x1)) {
|
||||
reg_val |= 0x1;
|
||||
writel(reg_val, hpriv->mmio + HOST_PORTS_IMPL);
|
||||
}
|
||||
|
||||
reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000;
|
||||
writel(reg_val, hpriv->mmio + HOST_TIMER1MS);
|
||||
|
||||
ret = ahci_platform_init_host(pdev, hpriv, &ahci_imx_port_info, 0, 0);
|
||||
if (ret)
|
||||
imx_sata_disable(hpriv);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void ahci_imx_host_stop(struct ata_host *host)
|
||||
{
|
||||
struct ahci_host_priv *hpriv = host->private_data;
|
||||
|
||||
imx_sata_disable(hpriv);
|
||||
}
|
||||
|
||||
static int imx_ahci_suspend(struct device *dev)
|
||||
{
|
||||
struct ata_host *host = dev_get_drvdata(dev);
|
||||
struct ahci_host_priv *hpriv = host->private_data;
|
||||
int ret;
|
||||
|
||||
ret = ahci_platform_suspend_host(dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
imx_sata_disable(hpriv);
|
||||
|
||||
platform_device_unregister(ahci_pdev);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int imx_ahci_resume(struct device *dev)
|
||||
{
|
||||
struct ata_host *host = dev_get_drvdata(dev);
|
||||
struct ahci_host_priv *hpriv = host->private_data;
|
||||
int ret;
|
||||
|
||||
ret = imx_sata_enable(hpriv);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return ahci_platform_resume_host(dev);
|
||||
}
|
||||
|
||||
static SIMPLE_DEV_PM_OPS(ahci_imx_pm_ops, imx_ahci_suspend, imx_ahci_resume);
|
||||
|
||||
static struct platform_driver imx_ahci_driver = {
|
||||
.probe = imx_ahci_probe,
|
||||
.remove = imx_ahci_remove,
|
||||
.remove = ata_platform_remove_one,
|
||||
.driver = {
|
||||
.name = "ahci-imx",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = imx_ahci_of_match,
|
||||
.pm = &ahci_imx_pm_ops,
|
||||
},
|
||||
};
|
||||
module_platform_driver(imx_ahci_driver);
|
||||
|
|
|
|||
Loading…
Reference in New Issue