ARM: EXYNOS4: Add support Core1 Power On/Off with hotplug in/out
To insert the code for power on/off with pmu control to support hotplug in/out core1 As for hotplug.c, the codes for core1 to be hotplug in/out is inserted. As for regs-pmu.h, S5P_CORE_LOCAL_PWR_EN is defined. As for platsmp.c, the codes for core1 to be powered on is inserted. Signed-off-by: JungHi Min <junghi.min@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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@ -13,9 +13,12 @@
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/smp.h>
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#include <linux/io.h>
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#include <asm/cacheflush.h>
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#include <mach/regs-pmu.h>
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extern volatile int pen_release;
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static inline void cpu_enter_lowpower(void)
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@ -58,12 +61,12 @@ static inline void cpu_leave_lowpower(void)
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static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
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{
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/*
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* there is no power-control hardware on this platform, so all
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* we can do is put the core into WFI; this is safe as the calling
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* code will have already disabled interrupts
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*/
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for (;;) {
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/* make cpu1 to be turned off at next WFI command */
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if (cpu == 1)
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__raw_writel(0, S5P_ARM_CORE1_CONFIGURATION);
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/*
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* here's the WFI
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*/
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@ -158,6 +158,7 @@
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#define S5P_PMU_GPS_CONF S5P_PMUREG(0x3CE0)
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#define S5P_PMU_SATA_PHY_CONTROL_EN 0x1
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#define S5P_CORE_LOCAL_PWR_EN 0x3
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#define S5P_INT_LOCAL_PWR_EN 0x7
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#define S5P_CHECK_SLEEP 0x00000BAD
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@ -28,9 +28,12 @@
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#include <mach/hardware.h>
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#include <mach/regs-clock.h>
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#include <mach/regs-pmu.h>
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extern void exynos4_secondary_startup(void);
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#define CPU1_BOOT_REG S5P_VA_SYSRAM
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/*
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* control for which core is the next to come out of the secondary
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* boot "holding pen"
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@ -125,16 +128,41 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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*/
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write_pen_release(cpu);
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if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {
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__raw_writel(S5P_CORE_LOCAL_PWR_EN,
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S5P_ARM_CORE1_CONFIGURATION);
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timeout = 10;
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/* wait max 10 ms until cpu1 is on */
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while ((__raw_readl(S5P_ARM_CORE1_STATUS)
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& S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) {
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if (timeout-- == 0)
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break;
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mdelay(1);
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}
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if (timeout == 0) {
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printk(KERN_ERR "cpu1 power enable failed");
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spin_unlock(&boot_lock);
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return -ETIMEDOUT;
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}
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}
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/*
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* Send the secondary CPU a soft interrupt, thereby causing
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* the boot monitor to read the system wide flags register,
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* and branch to the address found there.
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*/
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gic_raise_softirq(cpumask_of(cpu), 1);
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timeout = jiffies + (1 * HZ);
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while (time_before(jiffies, timeout)) {
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smp_rmb();
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__raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)),
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CPU1_BOOT_REG);
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gic_raise_softirq(cpumask_of(cpu), 1);
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if (pen_release == -1)
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break;
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