powerpc/mm/radix: Add LPID based tlb flush helpers
We add a tlb flush variant, to flush LPID mappings. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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@ -32,5 +32,7 @@ extern void radix__flush_tlb_pwc(struct mmu_gather *tlb, unsigned long addr);
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#define radix___flush_tlb_page(mm,addr,p,i) radix___local_flush_tlb_page(mm,addr,p,i)
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#define radix__flush_tlb_pwc(tlb, addr) radix__local_flush_tlb_pwc(tlb, addr)
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#endif
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extern void radix__flush_tlb_lpid_va(unsigned long lpid, unsigned long gpa,
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unsigned long page_size);
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extern void radix__flush_tlb_lpid(unsigned long lpid);
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#endif
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@ -282,9 +282,61 @@ void radix__flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
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}
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EXPORT_SYMBOL(radix__flush_tlb_range);
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static int radix_get_mmu_psize(int page_size)
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{
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int psize;
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if (page_size == (1UL << mmu_psize_defs[mmu_virtual_psize].shift))
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psize = mmu_virtual_psize;
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else if (page_size == (1UL << mmu_psize_defs[MMU_PAGE_2M].shift))
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psize = MMU_PAGE_2M;
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else if (page_size == (1UL << mmu_psize_defs[MMU_PAGE_1G].shift))
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psize = MMU_PAGE_1G;
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else
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return -1;
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return psize;
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}
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void radix__tlb_flush(struct mmu_gather *tlb)
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{
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struct mm_struct *mm = tlb->mm;
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radix__flush_tlb_mm(mm);
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}
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void radix__flush_tlb_lpid_va(unsigned long lpid, unsigned long gpa,
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unsigned long page_size)
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{
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unsigned long rb,rs,prs,r;
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unsigned long ap;
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unsigned long ric = RIC_FLUSH_TLB;
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ap = mmu_get_ap(radix_get_mmu_psize(page_size));
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rb = gpa & ~(PPC_BITMASK(52, 63));
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rb |= ap << PPC_BITLSHIFT(58);
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rs = lpid & ((1UL << 32) - 1);
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prs = 0; /* process scoped */
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r = 1; /* raidx format */
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asm volatile("ptesync": : :"memory");
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asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
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: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
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asm volatile("eieio; tlbsync; ptesync": : :"memory");
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}
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EXPORT_SYMBOL(radix__flush_tlb_lpid_va);
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void radix__flush_tlb_lpid(unsigned long lpid)
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{
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unsigned long rb,rs,prs,r;
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unsigned long ric = RIC_FLUSH_ALL;
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rb = 0x2 << PPC_BITLSHIFT(53); /* IS = 2 */
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rs = lpid & ((1UL << 32) - 1);
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prs = 0; /* partition scoped */
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r = 1; /* raidx format */
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asm volatile("ptesync": : :"memory");
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asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
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: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
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asm volatile("eieio; tlbsync; ptesync": : :"memory");
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}
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EXPORT_SYMBOL(radix__flush_tlb_lpid);
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