csky: Kernel booting
This patch add boot code. Thx boot params is all in dtb and it's the only way to let kernel get bootloader param information. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Guo Ren
parent
7c768f8451
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9143a9359d
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/* SPDX-License-Identifier: GPL-2.0 */
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/page.h>
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#include <abi/entry.h>
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__HEAD
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ENTRY(_start)
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/* set super user mode */
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lrw a3, DEFAULT_PSR_VALUE
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mtcr a3, psr
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psrset ee
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SETUP_MMU a3
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/* set stack point */
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lrw a3, init_thread_union + THREAD_SIZE
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mov sp, a3
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jmpi csky_start
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END(_start)
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#ifdef CONFIG_SMP
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.align 10
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ENTRY(_start_smp_secondary)
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/* Invalid I/Dcache BTB BHT */
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movi a3, 7
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lsli a3, 16
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addi a3, (1<<4) | 3
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mtcr a3, cr17
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tlbi.alls
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/* setup PAGEMASK */
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movi a3, 0
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mtcr a3, cr<6, 15>
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/* setup MEL0/MEL1 */
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grs a0, _start_smp_pc
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_start_smp_pc:
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bmaski a1, 13
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andn a0, a1
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movi a1, 0x00000006
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movi a2, 0x00001006
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or a1, a0
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or a2, a0
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mtcr a1, cr<2, 15>
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mtcr a2, cr<3, 15>
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/* setup MEH */
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mtcr a0, cr<4, 15>
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/* write TLB */
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bgeni a3, 28
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mtcr a3, cr<8, 15>
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SETUP_MMU a3
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/* enable MMU */
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movi a3, 1
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mtcr a3, cr18
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jmpi _goto_mmu_on
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_goto_mmu_on:
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lrw a3, DEFAULT_PSR_VALUE
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mtcr a3, psr
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psrset ee
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/* set stack point */
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lrw a3, secondary_stack
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ld.w a3, (a3, 0)
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mov sp, a3
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jmpi csky_start_secondary
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END(_start_smp_secondary)
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#endif
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@ -0,0 +1,162 @@
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// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
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#include <linux/console.h>
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#include <linux/memblock.h>
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#include <linux/bootmem.h>
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#include <linux/initrd.h>
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#include <linux/of.h>
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#include <linux/of_fdt.h>
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#include <linux/start_kernel.h>
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#include <linux/dma-contiguous.h>
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#include <linux/screen_info.h>
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#include <asm/sections.h>
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#include <asm/mmu_context.h>
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#include <asm/pgalloc.h>
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#ifdef CONFIG_DUMMY_CONSOLE
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struct screen_info screen_info = {
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.orig_video_lines = 30,
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.orig_video_cols = 80,
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.orig_video_mode = 0,
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.orig_video_ega_bx = 0,
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.orig_video_isVGA = 1,
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.orig_video_points = 8
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};
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#endif
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phys_addr_t __init_memblock memblock_end_of_REG0(void)
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{
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return (memblock.memory.regions[0].base +
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memblock.memory.regions[0].size);
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}
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phys_addr_t __init_memblock memblock_start_of_REG1(void)
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{
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return memblock.memory.regions[1].base;
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}
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size_t __init_memblock memblock_size_of_REG1(void)
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{
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return memblock.memory.regions[1].size;
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}
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static void __init csky_memblock_init(void)
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{
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unsigned long zone_size[MAX_NR_ZONES];
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unsigned long zhole_size[MAX_NR_ZONES];
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signed long size;
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memblock_reserve(__pa(_stext), _end - _stext);
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#ifdef CONFIG_BLK_DEV_INITRD
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memblock_reserve(__pa(initrd_start), initrd_end - initrd_start);
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#endif
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early_init_fdt_reserve_self();
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early_init_fdt_scan_reserved_mem();
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memblock_dump_all();
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memset(zone_size, 0, sizeof(zone_size));
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memset(zhole_size, 0, sizeof(zhole_size));
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min_low_pfn = PFN_UP(memblock_start_of_DRAM());
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max_pfn = PFN_DOWN(memblock_end_of_DRAM());
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max_low_pfn = PFN_UP(memblock_end_of_REG0());
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if (max_low_pfn == 0)
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max_low_pfn = max_pfn;
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size = max_pfn - min_low_pfn;
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if (memblock.memory.cnt > 1) {
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zone_size[ZONE_NORMAL] =
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PFN_DOWN(memblock_start_of_REG1()) - min_low_pfn;
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zhole_size[ZONE_NORMAL] =
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PFN_DOWN(memblock_start_of_REG1()) - max_low_pfn;
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} else {
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if (size <= PFN_DOWN(LOWMEM_LIMIT - PHYS_OFFSET_OFFSET))
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zone_size[ZONE_NORMAL] = max_pfn - min_low_pfn;
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else {
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zone_size[ZONE_NORMAL] =
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PFN_DOWN(LOWMEM_LIMIT - PHYS_OFFSET_OFFSET);
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max_low_pfn = min_low_pfn + zone_size[ZONE_NORMAL];
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}
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}
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#ifdef CONFIG_HIGHMEM
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size = 0;
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if (memblock.memory.cnt > 1) {
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size = PFN_DOWN(memblock_size_of_REG1());
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highstart_pfn = PFN_DOWN(memblock_start_of_REG1());
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} else {
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size = max_pfn - min_low_pfn -
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PFN_DOWN(LOWMEM_LIMIT - PHYS_OFFSET_OFFSET);
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highstart_pfn = min_low_pfn +
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PFN_DOWN(LOWMEM_LIMIT - PHYS_OFFSET_OFFSET);
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}
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if (size > 0)
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zone_size[ZONE_HIGHMEM] = size;
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highend_pfn = max_pfn;
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#endif
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memblock_set_current_limit(PFN_PHYS(max_low_pfn));
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dma_contiguous_reserve(0);
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free_area_init_node(0, zone_size, min_low_pfn, zhole_size);
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}
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void __init setup_arch(char **cmdline_p)
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{
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*cmdline_p = boot_command_line;
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console_verbose();
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pr_info("Phys. mem: %ldMB\n",
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(unsigned long) memblock_phys_mem_size()/1024/1024);
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init_mm.start_code = (unsigned long) _stext;
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init_mm.end_code = (unsigned long) _etext;
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init_mm.end_data = (unsigned long) _edata;
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init_mm.brk = (unsigned long) _end;
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parse_early_param();
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csky_memblock_init();
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unflatten_and_copy_device_tree();
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#ifdef CONFIG_SMP
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setup_smp();
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#endif
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sparse_init();
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#ifdef CONFIG_HIGHMEM
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kmap_init();
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#endif
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#if defined(CONFIG_VT) && defined(CONFIG_DUMMY_CONSOLE)
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conswitchp = &dummy_con;
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#endif
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}
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asmlinkage __visible void __init csky_start(unsigned int unused, void *param)
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{
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/* Clean up bss section */
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memset(__bss_start, 0, __bss_stop - __bss_start);
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pre_trap_init();
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pre_mmu_init();
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if (param == NULL)
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early_init_dt_scan(__dtb_start);
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else
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early_init_dt_scan(param);
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start_kernel();
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asm volatile("br .\n");
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}
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@ -0,0 +1,66 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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#include <asm/vmlinux.lds.h>
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#include <asm/page.h>
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OUTPUT_ARCH(csky)
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ENTRY(_start)
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#ifndef __cskyBE__
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jiffies = jiffies_64;
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#else
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jiffies = jiffies_64 + 4;
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#endif
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#define VBR_BASE \
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. = ALIGN(1024); \
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vec_base = .; \
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. += 512;
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SECTIONS
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{
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. = PAGE_OFFSET + PHYS_OFFSET_OFFSET;
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_stext = .;
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__init_begin = .;
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HEAD_TEXT_SECTION
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INIT_TEXT_SECTION(PAGE_SIZE)
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INIT_DATA_SECTION(PAGE_SIZE)
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PERCPU_SECTION(L1_CACHE_BYTES)
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. = ALIGN(PAGE_SIZE);
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__init_end = .;
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.text : AT(ADDR(.text) - LOAD_OFFSET) {
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_text = .;
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IRQENTRY_TEXT
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SOFTIRQENTRY_TEXT
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TEXT_TEXT
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SCHED_TEXT
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CPUIDLE_TEXT
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LOCK_TEXT
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KPROBES_TEXT
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*(.fixup)
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*(.gnu.warning)
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} = 0
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_etext = .;
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/* __init_begin __init_end must be page aligned for free_initmem */
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. = ALIGN(PAGE_SIZE);
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_sdata = .;
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RO_DATA_SECTION(PAGE_SIZE)
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RW_DATA_SECTION(L1_CACHE_BYTES, PAGE_SIZE, THREAD_SIZE)
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_edata = .;
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NOTES
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EXCEPTION_TABLE(L1_CACHE_BYTES)
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BSS_SECTION(L1_CACHE_BYTES, PAGE_SIZE, L1_CACHE_BYTES)
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VBR_BASE
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_end = . ;
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STABS_DEBUG
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DWARF_DEBUG
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DISCARDS
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}
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