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MIPS: Netlogic: move cpu_ready array to boot area 

Move the nlm_cpu_ready[] array used by the cpu wakeup code to the
boot area, along with rest of the boot parameter code.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5425/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Jayachandran C 2013-06-10 06:41:04 +00:00 committed by Ralf Baechle
parent 53c832197f
commit 919f9abb37
8 changed files with 22 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
arch/mips/include/asm/netlogic/common.h
View File

@ -39,11 +39,17 @@
* Common SMP definitions
*/
#define RESET_VEC_PHYS 0x1fc00000
#define RESET_VEC_SIZE 8192 /* 8KB reset code and data */
#define RESET_DATA_PHYS (RESET_VEC_PHYS + (1<<10))
/* Offsets of parameters in the RESET_DATA_PHYS area */
#define BOOT_THREAD_MODE 0
#define BOOT_NMI_LOCK 4
#define BOOT_NMI_HANDLER 8
/* CPU ready flags for each CPU */
#define BOOT_CPU_READY 2048
#ifndef __ASSEMBLY__
#include <linux/cpumask.h>
#include <linux/spinlock.h>

6
arch/mips/netlogic/common/reset.S
View File

@ -216,8 +216,10 @@ EXPORT(nlm_boot_siblings)
ori t1, ST0_KX
#endif
mtc0 t1, CP0_STATUS
/* mark CPU ready */
PTR_LA t1, nlm_cpu_ready
/* mark CPU ready, careful here, previous mtcr trashed registers */
li t3, CKSEG1ADDR(RESET_DATA_PHYS)
ADDIU t1, t3, BOOT_CPU_READY
sll v1, v0, 2
PTR_ADDU t1, v1
li t2, 1

6
arch/mips/netlogic/common/smp.c
View File

@ -145,7 +145,6 @@ void nlm_cpus_done(void)
* Boot all other cpus in the system, initialize them, and bring them into
* the boot function
*/
int nlm_cpu_ready[NR_CPUS];
unsigned long nlm_next_gp;
unsigned long nlm_next_sp;
static cpumask_t phys_cpu_present_mask;
@ -168,6 +167,7 @@ void __init nlm_smp_setup(void)
{
unsigned int boot_cpu;
int num_cpus, i, ncore;
volatile u32 *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY);
char buf[64];
boot_cpu = hard_smp_processor_id();
@ -181,10 +181,10 @@ void __init nlm_smp_setup(void)
num_cpus = 1;
for (i = 0; i < NR_CPUS; i++) {
/*
* nlm_cpu_ready array is not set for the boot_cpu,
* cpu_ready array is not set for the boot_cpu,
* it is only set for ASPs (see smpboot.S)
*/
if (nlm_cpu_ready[i]) {
if (cpu_ready[i]) {
cpumask_set_cpu(i, &phys_cpu_present_mask);
__cpu_number_map[i] = num_cpus;
__cpu_logical_map[num_cpus] = i;

5
arch/mips/netlogic/common/smpboot.S
View File

@ -109,8 +109,9 @@ NESTED(nlm_rmiboot_preboot, 16, sp)
andi t2, t0, 0x3 /* thread num */
sll t0, 2 /* offset in cpu array */
PTR_LA t1, nlm_cpu_ready /* mark CPU ready */
PTR_ADDU t1, t0
li t3, CKSEG1ADDR(RESET_DATA_PHYS)
ADDIU t1, t3, BOOT_CPU_READY
ADDU t1, t0
li t3, 1
sw t3, 0(t1)

1
arch/mips/netlogic/xlp/setup.c
View File

@ -108,6 +108,7 @@ void __init prom_init(void)
/* Update reset entry point with CPU init code */
reset_vec = (void *)CKSEG1ADDR(RESET_VEC_PHYS);
memset(reset_vec, 0, RESET_VEC_SIZE);
memcpy(reset_vec, (void *)nlm_reset_entry,
(nlm_reset_entry_end - nlm_reset_entry));

3
arch/mips/netlogic/xlp/wakeup.c
View File

@ -82,6 +82,7 @@ static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask)
struct nlm_soc_info *nodep;
uint64_t syspcibase;
uint32_t syscoremask;
volatile uint32_t *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY);
int core, n, cpu, count, val;
for (n = 0; n < NLM_NR_NODES; n++) {
@ -125,7 +126,7 @@ static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask)
/* spin until the first hw thread sets its ready */
count = 0x20000000;
do {
val = *(volatile int *)&nlm_cpu_ready[cpu];
val = cpu_ready[cpu];
} while (val == 0 && --count > 0);
}
}

1
arch/mips/netlogic/xlr/setup.c
View File

@ -211,6 +211,7 @@ void __init prom_init(void)
/* Update reset entry point with CPU init code */
reset_vec = (void *)CKSEG1ADDR(RESET_VEC_PHYS);
memset(reset_vec, 0, RESET_VEC_SIZE);
memcpy(reset_vec, (void *)nlm_reset_entry,
(nlm_reset_entry_end - nlm_reset_entry));

3
arch/mips/netlogic/xlr/wakeup.c
View File

@ -53,6 +53,7 @@ int __cpuinit xlr_wakeup_secondary_cpus(void)
{
struct nlm_soc_info *nodep;
unsigned int i, j, boot_cpu;
volatile u32 *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY);
/*
* In case of RMI boot, hit with NMI to get the cores
@ -71,7 +72,7 @@ int __cpuinit xlr_wakeup_secondary_cpus(void)
nodep->coremask = 1;
for (i = 1; i < NLM_CORES_PER_NODE; i++) {
for (j = 1000000; j > 0; j--) {
if (nlm_cpu_ready[i * NLM_THREADS_PER_CORE])
if (cpu_ready[i * NLM_THREADS_PER_CORE])
break;
udelay(10);
}