ARM: SoC fixes for 3.13-rc
Much smaller batch of fixes this week. Biggest one is a revert of an OMAP display change that removed some non-DT pinmux code that was still needed for 3.13 to get DSI displays to work. There's also a fix that resolves some misdescribed GPIO controller resources on shmobile. The rest are mostly smaller fixes, a couple of MAINTAINERS updates, etc. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJStx0EAAoJEIwa5zzehBx3G+gP/3qH83dbelntB3R7Ve3KbT41 YT0q4G8s4Kper+qSXK2eJRTcEUfZBhtXw2GytnEjwdj6xRtTYmdzUIE/7awwzxQx EkcwyCKiMLhVqjBgYg0fr11RBmbvQxKV0L2iIHoV5N/VJa/I7DN4N1J0PwB/7tuQ OVpy3UOuutvtV3k4/G4tminixx1Y6JjPy7vEs8oiQoc7MRrMwe4zC2pgRF5eVfFG uNfRk1IEpvoFM+ir+ZmKJYVsEGXlC/bLwO7KPql6801n7987uQni9YoyUy+7cLGp CVCSaD7iGVPde8ijfUN84C8IezjfkA/wA9cxaGBj9lD7EdcvXEdtvDiFXpQcZDYY NZX9p7+ZzTNzKSRIPKET8Ky3GNqDGCoaCoV9YTpUGwMHXmoK66QJpNy1boW0fZ2B yy3gT0fxJYRKMTiFdV+y77BFpLDNkDGnjuVQEovKC8mX2YfqjR0sOTFjHBhPWk8P gZ2Lzq1V/j0gd6/YxNStVngQK6/CiA9/qBUeBgiIU6vAzPcpk4HcwapFCcUeU4mU l8Iga63cBu3iSobSNTcF7EB1iHwOQOTH7txtD1RtPsWxZgXG74kwmtWC336aEhlJ fixoZIQvzPdQLqtZIMm87jJHXYsBZJnnqCTmFTgfn26Wb79qnS4WMt2tahCLGrkO RGDjdfaXw46WbJZ25kcJ =6Nj7 -----END PGP SIGNATURE----- Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC fixes from Olof Johansson: "Much smaller batch of fixes this week. Biggest one is a revert of an OMAP display change that removed some non-DT pinmux code that was still needed for 3.13 to get DSI displays to work. There's also a fix that resolves some misdescribed GPIO controller resources on shmobile. The rest are mostly smaller fixes, a couple of MAINTAINERS updates, etc" * tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: Revert "ARM: OMAP2+: Remove legacy mux code for display.c" MAINTAINERS: Add keystone clock drivers MAINTAINERS: Add keystone git tree information ARM: s3c64xx: dt: Fix boot failure due to double clock initialization ARM: shmobile: r8a7790: Fix GPIO resources in DTS irqchip: renesas-intc-irqpin: Fix register bitfield shift calculation ARM: shmobile: lager: phy fixup needs CONFIG_PHYLIB
This commit is contained in:
Linus Torvalds
commit
93579aeec2
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@ -1008,6 +1008,8 @@ M: Santosh Shilimkar <santosh.shilimkar@ti.com>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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S: Maintained
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F: arch/arm/mach-keystone/
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F: drivers/clk/keystone/
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T: git git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone.git
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ARM/LOGICPD PXA270 MACHINE SUPPORT
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M: Lennert Buytenhek <kernel@wantstofly.org>
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@ -87,9 +87,9 @@
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interrupts = <1 9 0xf04>;
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};
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gpio0: gpio@ffc40000 {
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gpio0: gpio@e6050000 {
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compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
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reg = <0 0xffc40000 0 0x2c>;
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reg = <0 0xe6050000 0 0x50>;
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interrupt-parent = <&gic>;
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interrupts = <0 4 0x4>;
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#gpio-cells = <2>;
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@ -99,9 +99,9 @@
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interrupt-controller;
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};
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gpio1: gpio@ffc41000 {
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gpio1: gpio@e6051000 {
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compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
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reg = <0 0xffc41000 0 0x2c>;
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reg = <0 0xe6051000 0 0x50>;
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interrupt-parent = <&gic>;
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interrupts = <0 5 0x4>;
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#gpio-cells = <2>;
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@ -111,9 +111,9 @@
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interrupt-controller;
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};
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gpio2: gpio@ffc42000 {
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gpio2: gpio@e6052000 {
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compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
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reg = <0 0xffc42000 0 0x2c>;
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reg = <0 0xe6052000 0 0x50>;
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interrupt-parent = <&gic>;
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interrupts = <0 6 0x4>;
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#gpio-cells = <2>;
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@ -123,9 +123,9 @@
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interrupt-controller;
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};
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gpio3: gpio@ffc43000 {
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gpio3: gpio@e6053000 {
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compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
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reg = <0 0xffc43000 0 0x2c>;
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reg = <0 0xe6053000 0 0x50>;
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interrupt-parent = <&gic>;
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interrupts = <0 7 0x4>;
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#gpio-cells = <2>;
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@ -135,9 +135,9 @@
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interrupt-controller;
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};
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gpio4: gpio@ffc44000 {
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gpio4: gpio@e6054000 {
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compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
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reg = <0 0xffc44000 0 0x2c>;
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reg = <0 0xe6054000 0 0x50>;
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interrupt-parent = <&gic>;
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interrupts = <0 8 0x4>;
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#gpio-cells = <2>;
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@ -147,9 +147,9 @@
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interrupt-controller;
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};
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gpio5: gpio@ffc45000 {
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gpio5: gpio@e6055000 {
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compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
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reg = <0 0xffc45000 0 0x2c>;
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reg = <0 0xe6055000 0 0x50>;
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interrupt-parent = <&gic>;
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interrupts = <0 9 0x4>;
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#gpio-cells = <2>;
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@ -101,13 +101,51 @@ static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initconst = {
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{ "dss_hdmi", "omapdss_hdmi", -1 },
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};
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static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
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{
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u32 enable_mask, enable_shift;
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u32 pipd_mask, pipd_shift;
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u32 reg;
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if (dsi_id == 0) {
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enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
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enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT;
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pipd_mask = OMAP4_DSI1_PIPD_MASK;
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pipd_shift = OMAP4_DSI1_PIPD_SHIFT;
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} else if (dsi_id == 1) {
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enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
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enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT;
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pipd_mask = OMAP4_DSI2_PIPD_MASK;
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pipd_shift = OMAP4_DSI2_PIPD_SHIFT;
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} else {
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return -ENODEV;
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}
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reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
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reg &= ~enable_mask;
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reg &= ~pipd_mask;
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reg |= (lanes << enable_shift) & enable_mask;
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reg |= (lanes << pipd_shift) & pipd_mask;
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omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
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return 0;
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}
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static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
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{
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if (cpu_is_omap44xx())
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return omap4_dsi_mux_pads(dsi_id, lane_mask);
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return 0;
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}
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static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
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{
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if (cpu_is_omap44xx())
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omap4_dsi_mux_pads(dsi_id, 0);
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}
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static int omap_dss_set_min_bus_tput(struct device *dev, unsigned long tput)
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@ -8,8 +8,6 @@
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* published by the Free Software Foundation.
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*/
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#include <linux/clk-provider.h>
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#include <linux/irqchip.h>
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#include <linux/of_platform.h>
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#include <asm/mach/arch.h>
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@ -48,15 +46,9 @@ static void __init s3c64xx_dt_map_io(void)
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panic("SoC is not S3C64xx!");
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}
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static void __init s3c64xx_dt_init_irq(void)
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{
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of_clk_init(NULL);
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samsung_wdt_reset_of_init();
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irqchip_init();
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};
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static void __init s3c64xx_dt_init_machine(void)
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{
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samsung_wdt_reset_of_init();
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of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
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}
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@ -79,7 +71,6 @@ DT_MACHINE_START(S3C6400_DT, "Samsung S3C64xx (Flattened Device Tree)")
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/* Maintainer: Tomasz Figa <tomasz.figa@gmail.com> */
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.dt_compat = s3c64xx_dt_compat,
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.map_io = s3c64xx_dt_map_io,
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.init_irq = s3c64xx_dt_init_irq,
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.init_machine = s3c64xx_dt_init_machine,
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.restart = s3c64xx_dt_restart,
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MACHINE_END
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@ -245,7 +245,9 @@ static void __init lager_init(void)
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{
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lager_add_standard_devices();
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phy_register_fixup_for_id("r8a7790-ether-ff:01", lager_ksz8041_fixup);
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if (IS_ENABLED(CONFIG_PHYLIB))
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phy_register_fixup_for_id("r8a7790-ether-ff:01",
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lager_ksz8041_fixup);
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}
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static const char * const lager_boards_compat_dt[] __initconst = {
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@ -149,8 +149,9 @@ static void intc_irqpin_read_modify_write(struct intc_irqpin_priv *p,
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static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p,
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int irq, int do_mask)
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{
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int bitfield_width = 4; /* PRIO assumed to have fixed bitfield width */
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int shift = (7 - irq) * bitfield_width; /* PRIO assumed to be 32-bit */
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/* The PRIO register is assumed to be 32-bit with fixed 4-bit fields. */
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int bitfield_width = 4;
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int shift = 32 - (irq + 1) * bitfield_width;
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intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_PRIO,
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shift, bitfield_width,
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@ -159,8 +160,9 @@ static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p,
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static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value)
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{
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/* The SENSE register is assumed to be 32-bit. */
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int bitfield_width = p->config.sense_bitfield_width;
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int shift = (7 - irq) * bitfield_width; /* SENSE assumed to be 32-bit */
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int shift = 32 - (irq + 1) * bitfield_width;
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dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value);
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