Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 fixes from Thomas Gleixner: "A couple of fixes addressing the following issues: - The last polishing for the TLB code, removing the last BUG_ON() and the debug file along with tidying up the lazy TLB code. - Prevent triple fault on 1st Gen. 486 caused by stupidly calling the early IDT setup after the first function which causes a fault which should be caught by the exception table. - Limit the mmap of /dev/mem to valid addresses - Prevent late microcode loading on Broadwell X - Remove a redundant assignment in the cache info code" * 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/mm: Limit mmap() of /dev/mem to valid physical addresses x86/mm: Remove debug/x86/tlb_defer_switch_to_init_mm x86/mm: Tidy up "x86/mm: Flush more aggressively in lazy TLB mode" x86/mm/64: Remove the last VM_BUG_ON() from the TLB code x86/microcode/intel: Disable late loading on model 79 x86/idt: Initialize early IDT before cr4_init_shadow() x86/cpu/intel_cacheinfo: Remove redundant assignment to 'this_leaf'
This commit is contained in:
commit
936fd00549
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@ -110,6 +110,10 @@ build_mmio_write(__writeq, "q", unsigned long, "r", )
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#endif
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#endif
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#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
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extern int valid_phys_addr_range(phys_addr_t addr, size_t size);
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extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
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/**
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/**
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* virt_to_phys - map virtual addresses to physical
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* virt_to_phys - map virtual addresses to physical
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* @address: address to remap
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* @address: address to remap
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@ -82,12 +82,21 @@ static inline u64 inc_mm_tlb_gen(struct mm_struct *mm)
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#define __flush_tlb_single(addr) __native_flush_tlb_single(addr)
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#define __flush_tlb_single(addr) __native_flush_tlb_single(addr)
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#endif
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#endif
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/*
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static inline bool tlb_defer_switch_to_init_mm(void)
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* If tlb_use_lazy_mode is true, then we try to avoid switching CR3 to point
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{
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* to init_mm when we switch to a kernel thread (e.g. the idle thread). If
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/*
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* it's false, then we immediately switch CR3 when entering a kernel thread.
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* If we have PCID, then switching to init_mm is reasonably
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* fast. If we don't have PCID, then switching to init_mm is
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* quite slow, so we try to defer it in the hopes that we can
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* avoid it entirely. The latter approach runs the risk of
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* receiving otherwise unnecessary IPIs.
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*
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* This choice is just a heuristic. The tlb code can handle this
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* function returning true or false regardless of whether we have
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* PCID.
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*/
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*/
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DECLARE_STATIC_KEY_TRUE(tlb_use_lazy_mode);
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return !static_cpu_has(X86_FEATURE_PCID);
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}
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/*
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/*
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* 6 because 6 should be plenty and struct tlb_state will fit in
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* 6 because 6 should be plenty and struct tlb_state will fit in
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@ -831,7 +831,6 @@ static int __cache_amd_cpumap_setup(unsigned int cpu, int index,
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} else if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
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} else if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
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unsigned int apicid, nshared, first, last;
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unsigned int apicid, nshared, first, last;
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this_leaf = this_cpu_ci->info_list + index;
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nshared = base->eax.split.num_threads_sharing + 1;
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nshared = base->eax.split.num_threads_sharing + 1;
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apicid = cpu_data(cpu).apicid;
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apicid = cpu_data(cpu).apicid;
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first = apicid - (apicid % nshared);
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first = apicid - (apicid % nshared);
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@ -34,6 +34,7 @@
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#include <linux/mm.h>
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#include <linux/mm.h>
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#include <asm/microcode_intel.h>
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#include <asm/microcode_intel.h>
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#include <asm/intel-family.h>
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#include <asm/processor.h>
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#include <asm/processor.h>
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#include <asm/tlbflush.h>
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#include <asm/tlbflush.h>
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#include <asm/setup.h>
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#include <asm/setup.h>
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@ -918,6 +919,18 @@ static int get_ucode_fw(void *to, const void *from, size_t n)
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return 0;
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return 0;
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}
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}
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static bool is_blacklisted(unsigned int cpu)
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{
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struct cpuinfo_x86 *c = &cpu_data(cpu);
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if (c->x86 == 6 && c->x86_model == INTEL_FAM6_BROADWELL_X) {
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pr_err_once("late loading on model 79 is disabled.\n");
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return true;
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}
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return false;
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}
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static enum ucode_state request_microcode_fw(int cpu, struct device *device,
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static enum ucode_state request_microcode_fw(int cpu, struct device *device,
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bool refresh_fw)
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bool refresh_fw)
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{
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{
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@ -926,6 +939,9 @@ static enum ucode_state request_microcode_fw(int cpu, struct device *device,
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const struct firmware *firmware;
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const struct firmware *firmware;
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enum ucode_state ret;
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enum ucode_state ret;
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if (is_blacklisted(cpu))
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return UCODE_NFOUND;
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sprintf(name, "intel-ucode/%02x-%02x-%02x",
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sprintf(name, "intel-ucode/%02x-%02x-%02x",
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c->x86, c->x86_model, c->x86_mask);
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c->x86, c->x86_model, c->x86_mask);
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@ -950,6 +966,9 @@ static int get_ucode_user(void *to, const void *from, size_t n)
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static enum ucode_state
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static enum ucode_state
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request_microcode_user(int cpu, const void __user *buf, size_t size)
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request_microcode_user(int cpu, const void __user *buf, size_t size)
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{
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{
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if (is_blacklisted(cpu))
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return UCODE_NFOUND;
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return generic_load_microcode(cpu, (void *)buf, size, &get_ucode_user);
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return generic_load_microcode(cpu, (void *)buf, size, &get_ucode_user);
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}
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}
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@ -30,10 +30,11 @@ static void __init i386_default_early_setup(void)
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asmlinkage __visible void __init i386_start_kernel(void)
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asmlinkage __visible void __init i386_start_kernel(void)
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{
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{
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cr4_init_shadow();
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/* Make sure IDT is set up before any exception happens */
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idt_setup_early_handler();
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idt_setup_early_handler();
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cr4_init_shadow();
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sanitize_boot_params(&boot_params);
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sanitize_boot_params(&boot_params);
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x86_early_init_platform_quirks();
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x86_early_init_platform_quirks();
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@ -174,3 +174,15 @@ const char *arch_vma_name(struct vm_area_struct *vma)
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return "[mpx]";
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return "[mpx]";
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return NULL;
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return NULL;
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}
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}
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int valid_phys_addr_range(phys_addr_t addr, size_t count)
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{
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return addr + count <= __pa(high_memory);
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}
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int valid_mmap_phys_addr_range(unsigned long pfn, size_t count)
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{
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phys_addr_t addr = (phys_addr_t)pfn << PAGE_SHIFT;
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return valid_phys_addr_range(addr, count);
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}
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@ -30,7 +30,6 @@
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atomic64_t last_mm_ctx_id = ATOMIC64_INIT(1);
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atomic64_t last_mm_ctx_id = ATOMIC64_INIT(1);
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DEFINE_STATIC_KEY_TRUE(tlb_use_lazy_mode);
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static void choose_new_asid(struct mm_struct *next, u64 next_tlb_gen,
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static void choose_new_asid(struct mm_struct *next, u64 next_tlb_gen,
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u16 *new_asid, bool *need_flush)
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u16 *new_asid, bool *need_flush)
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this_cpu_write(cpu_tlbstate.is_lazy, false);
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this_cpu_write(cpu_tlbstate.is_lazy, false);
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if (real_prev == next) {
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if (real_prev == next) {
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VM_BUG_ON(this_cpu_read(cpu_tlbstate.ctxs[prev_asid].ctx_id) !=
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VM_WARN_ON(this_cpu_read(cpu_tlbstate.ctxs[prev_asid].ctx_id) !=
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next->context.ctx_id);
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next->context.ctx_id);
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/*
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/*
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@ -213,6 +212,9 @@ void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next,
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}
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}
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/*
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/*
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* Please ignore the name of this function. It should be called
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* switch_to_kernel_thread().
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*
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* enter_lazy_tlb() is a hint from the scheduler that we are entering a
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* enter_lazy_tlb() is a hint from the scheduler that we are entering a
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* kernel thread or other context without an mm. Acceptable implementations
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* kernel thread or other context without an mm. Acceptable implementations
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* include doing nothing whatsoever, switching to init_mm, or various clever
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* include doing nothing whatsoever, switching to init_mm, or various clever
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if (this_cpu_read(cpu_tlbstate.loaded_mm) == &init_mm)
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if (this_cpu_read(cpu_tlbstate.loaded_mm) == &init_mm)
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return;
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return;
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if (static_branch_unlikely(&tlb_use_lazy_mode)) {
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if (tlb_defer_switch_to_init_mm()) {
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/*
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/*
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* There's a significant optimization that may be possible
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* There's a significant optimization that may be possible
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* here. We have accurate enough TLB flush tracking that we
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* here. We have accurate enough TLB flush tracking that we
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return 0;
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return 0;
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}
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}
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late_initcall(create_tlb_single_page_flush_ceiling);
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late_initcall(create_tlb_single_page_flush_ceiling);
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static ssize_t tlblazy_read_file(struct file *file, char __user *user_buf,
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size_t count, loff_t *ppos)
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{
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char buf[2];
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buf[0] = static_branch_likely(&tlb_use_lazy_mode) ? '1' : '0';
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buf[1] = '\n';
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return simple_read_from_buffer(user_buf, count, ppos, buf, 2);
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}
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static ssize_t tlblazy_write_file(struct file *file,
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const char __user *user_buf, size_t count, loff_t *ppos)
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{
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bool val;
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if (kstrtobool_from_user(user_buf, count, &val))
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return -EINVAL;
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if (val)
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static_branch_enable(&tlb_use_lazy_mode);
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else
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static_branch_disable(&tlb_use_lazy_mode);
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return count;
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}
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static const struct file_operations fops_tlblazy = {
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.read = tlblazy_read_file,
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.write = tlblazy_write_file,
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.llseek = default_llseek,
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};
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static int __init init_tlb_use_lazy_mode(void)
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{
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if (boot_cpu_has(X86_FEATURE_PCID)) {
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/*
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* Heuristic: with PCID on, switching to and from
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* init_mm is reasonably fast, but remote flush IPIs
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* as expensive as ever, so turn off lazy TLB mode.
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*
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* We can't do this in setup_pcid() because static keys
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* haven't been initialized yet, and it would blow up
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* badly.
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*/
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static_branch_disable(&tlb_use_lazy_mode);
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}
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debugfs_create_file("tlb_use_lazy_mode", S_IRUSR | S_IWUSR,
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arch_debugfs_dir, NULL, &fops_tlblazy);
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return 0;
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}
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late_initcall(init_tlb_use_lazy_mode);
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