clk: qcom: gcc: Add missing UFS clocks for SM8150
commit37c72e4cae
upstream. Add the missing ufs card and ufs phy clocks for SM8150. They were missed in earlier addition of clock driver. Fixes:2a1d7eb854
("clk: qcom: gcc: Add global clock controller driver for SM8150") Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lkml.kernel.org/r/20200513065420.32735-2-vkoul@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -2871,6 +2871,45 @@ static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = {
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},
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};
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/* external clocks so add BRANCH_HALT_SKIP */
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static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = {
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.halt_check = BRANCH_HALT_SKIP,
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.clkr = {
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.enable_reg = 0x7501c,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_ufs_card_rx_symbol_0_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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/* external clocks so add BRANCH_HALT_SKIP */
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static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = {
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.halt_check = BRANCH_HALT_SKIP,
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.clkr = {
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.enable_reg = 0x750ac,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_ufs_card_rx_symbol_1_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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/* external clocks so add BRANCH_HALT_SKIP */
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static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = {
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.halt_check = BRANCH_HALT_SKIP,
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.clkr = {
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.enable_reg = 0x75018,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_ufs_card_tx_symbol_0_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gcc_ufs_card_unipro_core_clk = {
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.halt_reg = 0x75058,
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.halt_check = BRANCH_HALT,
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@ -3051,6 +3090,45 @@ static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {
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},
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};
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/* external clocks so add BRANCH_HALT_SKIP */
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static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
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.halt_check = BRANCH_HALT_SKIP,
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.clkr = {
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.enable_reg = 0x7701c,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_ufs_phy_rx_symbol_0_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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/* external clocks so add BRANCH_HALT_SKIP */
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static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
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.halt_check = BRANCH_HALT_SKIP,
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.clkr = {
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.enable_reg = 0x770ac,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_ufs_phy_rx_symbol_1_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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/* external clocks so add BRANCH_HALT_SKIP */
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static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
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.halt_check = BRANCH_HALT_SKIP,
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.clkr = {
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.enable_reg = 0x77018,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_ufs_phy_tx_symbol_0_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
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.halt_reg = 0x77058,
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.halt_check = BRANCH_HALT,
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@ -3505,6 +3583,9 @@ static struct clk_regmap *gcc_sm8150_clocks[] = {
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[GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr,
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[GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK] =
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&gcc_ufs_card_phy_aux_hw_ctl_clk.clkr,
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[GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr,
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[GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr,
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[GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr,
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[GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr,
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[GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] =
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&gcc_ufs_card_unipro_core_clk_src.clkr,
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@ -3522,6 +3603,9 @@ static struct clk_regmap *gcc_sm8150_clocks[] = {
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[GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
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[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
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[GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,
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[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
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[GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
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[GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
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[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
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[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
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&gcc_ufs_phy_unipro_core_clk_src.clkr,
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