RISC-V: Add the directive for alignment of stvec's value
The stvec's value must be 4 byte alignment by specification definition. These directives avoid to stvec be set the non-alignment value. Signed-off-by: Zong Li <zong@andestech.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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@ -94,6 +94,7 @@ relocate:
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or a0, a0, a1
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or a0, a0, a1
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sfence.vma
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sfence.vma
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csrw sptbr, a0
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csrw sptbr, a0
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.align 2
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1:
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1:
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/* Set trap vector to spin forever to help debug */
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/* Set trap vector to spin forever to help debug */
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la a0, .Lsecondary_park
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la a0, .Lsecondary_park
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@ -143,6 +144,7 @@ relocate:
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tail smp_callin
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tail smp_callin
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#endif
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#endif
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.align 2
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.Lsecondary_park:
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.Lsecondary_park:
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/* We lack SMP support or have too many harts, so park this hart */
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/* We lack SMP support or have too many harts, so park this hart */
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wfi
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wfi
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