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drm/nouveau/ltc: s/ltcg/ltc/ + cleanup

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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2014-08-10 04:10:28 +10:00
parent f392ec4b1d
commit 95484b5726
17 changed files with 362 additions and 235 deletions
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6
drivers/gpu/drm/nouveau/Makefile
View File

@ -153,8 +153,10 @@ nouveau-y += core/subdev/instmem/base.o
nouveau-y += core/subdev/instmem/nv04.o
nouveau-y += core/subdev/instmem/nv40.o
nouveau-y += core/subdev/instmem/nv50.o
nouveau-y += core/subdev/ltcg/gf100.o
nouveau-y += core/subdev/ltcg/gm107.o
nouveau-y += core/subdev/ltc/base.o
nouveau-y += core/subdev/ltc/gf100.o
nouveau-y += core/subdev/ltc/gk104.o
nouveau-y += core/subdev/ltc/gm107.o
nouveau-y += core/subdev/mc/base.o
nouveau-y += core/subdev/mc/nv04.o
nouveau-y += core/subdev/mc/nv40.o

2
drivers/gpu/drm/nouveau/core/engine/device/base.c
View File

@ -214,7 +214,7 @@ static const u64 disable_map[] = {
[NVDEV_SUBDEV_BUS] = NV_DEVICE_V0_DISABLE_CORE,
[NVDEV_SUBDEV_TIMER] = NV_DEVICE_V0_DISABLE_CORE,
[NVDEV_SUBDEV_FB] = NV_DEVICE_V0_DISABLE_CORE,
[NVDEV_SUBDEV_LTCG] = NV_DEVICE_V0_DISABLE_CORE,
[NVDEV_SUBDEV_LTC] = NV_DEVICE_V0_DISABLE_CORE,
[NVDEV_SUBDEV_IBUS] = NV_DEVICE_V0_DISABLE_CORE,
[NVDEV_SUBDEV_INSTMEM] = NV_DEVICE_V0_DISABLE_CORE,
[NVDEV_SUBDEV_VM] = NV_DEVICE_V0_DISABLE_CORE,

4
drivers/gpu/drm/nouveau/core/engine/device/gm100.c
View File

@ -33,7 +33,7 @@
#include <subdev/mc.h>
#include <subdev/timer.h>
#include <subdev/fb.h>
#include <subdev/ltcg.h>
#include <subdev/ltc.h>
#include <subdev/ibus.h>
#include <subdev/instmem.h>
#include <subdev/vm.h>
@ -72,7 +72,7 @@ gm100_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = gm107_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTCG ] = gm107_ltcg_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;

20
drivers/gpu/drm/nouveau/core/engine/device/nvc0.c
View File

@ -33,7 +33,7 @@
#include <subdev/mc.h>
#include <subdev/timer.h>
#include <subdev/fb.h>
#include <subdev/ltcg.h>
#include <subdev/ltc.h>
#include <subdev/ibus.h>
#include <subdev/instmem.h>
#include <subdev/vm.h>
@ -70,7 +70,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
@ -102,7 +102,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
@ -134,7 +134,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
@ -165,7 +165,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
@ -197,7 +197,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
@ -229,7 +229,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
@ -260,7 +260,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
@ -292,7 +292,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
@ -323,7 +323,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;

14
drivers/gpu/drm/nouveau/core/engine/device/nve0.c
View File

@ -33,7 +33,7 @@
#include <subdev/mc.h>
#include <subdev/timer.h>
#include <subdev/fb.h>
#include <subdev/ltcg.h>
#include <subdev/ltc.h>
#include <subdev/ibus.h>
#include <subdev/instmem.h>
#include <subdev/vm.h>
@ -70,7 +70,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
@ -103,7 +103,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
@ -136,7 +136,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
@ -187,7 +187,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
@ -220,7 +220,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
@ -253,7 +253,7 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTCG ] = gf100_ltcg_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;

2
drivers/gpu/drm/nouveau/core/include/core/device.h
View File

@ -29,7 +29,7 @@ enum nv_subdev_type {
NVDEV_SUBDEV_BUS,
NVDEV_SUBDEV_TIMER,
NVDEV_SUBDEV_FB,
NVDEV_SUBDEV_LTCG,
NVDEV_SUBDEV_LTC,
NVDEV_SUBDEV_IBUS,
NVDEV_SUBDEV_INSTMEM,
NVDEV_SUBDEV_VM,

28
drivers/gpu/drm/nouveau/core/include/subdev/ltc.h Normal file
View File

@ -0,0 +1,28 @@
#ifndef __NOUVEAU_LTC_H__
#define __NOUVEAU_LTC_H__
#include <core/subdev.h>
#include <core/device.h>
struct nouveau_mm_node;
struct nouveau_ltc {
struct nouveau_subdev base;
int (*tags_alloc)(struct nouveau_ltc *, u32 count,
struct nouveau_mm_node **);
void (*tags_free)(struct nouveau_ltc *, struct nouveau_mm_node **);
void (*tags_clear)(struct nouveau_ltc *, u32 first, u32 count);
};
static inline struct nouveau_ltc *
nouveau_ltc(void *obj)
{
return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_LTC];
}
extern struct nouveau_oclass *gf100_ltc_oclass;
extern struct nouveau_oclass *gk104_ltc_oclass;
extern struct nouveau_oclass *gm107_ltc_oclass;
#endif

41
drivers/gpu/drm/nouveau/core/include/subdev/ltcg.h
View File

@ -1,41 +0,0 @@
#ifndef __NOUVEAU_LTCG_H__
#define __NOUVEAU_LTCG_H__
#include <core/subdev.h>
#include <core/device.h>
struct nouveau_mm_node;
struct nouveau_ltcg {
struct nouveau_subdev base;
int (*tags_alloc)(struct nouveau_ltcg *, u32 count,
struct nouveau_mm_node **);
void (*tags_free)(struct nouveau_ltcg *, struct nouveau_mm_node **);
void (*tags_clear)(struct nouveau_ltcg *, u32 first, u32 count);
};
static inline struct nouveau_ltcg *
nouveau_ltcg(void *obj)
{
return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_LTCG];
}
#define nouveau_ltcg_create(p,e,o,d) \
nouveau_subdev_create_((p), (e), (o), 0, "PLTCG", "level2", \
sizeof(**d), (void **)d)
#define nouveau_ltcg_destroy(p) \
nouveau_subdev_destroy(&(p)->base)
#define nouveau_ltcg_init(p) \
nouveau_subdev_init(&(p)->base)
#define nouveau_ltcg_fini(p,s) \
nouveau_subdev_fini(&(p)->base, (s))
#define _nouveau_ltcg_dtor _nouveau_subdev_dtor
#define _nouveau_ltcg_init _nouveau_subdev_init
#define _nouveau_ltcg_fini _nouveau_subdev_fini
extern struct nouveau_oclass *gf100_ltcg_oclass;
extern struct nouveau_oclass *gm107_ltcg_oclass;
#endif

10
drivers/gpu/drm/nouveau/core/subdev/fb/ramnvc0.c
View File

@ -26,7 +26,7 @@
#include <subdev/bios/pll.h>
#include <subdev/bios/rammap.h>
#include <subdev/bios/timing.h>
#include <subdev/ltcg.h>
#include <subdev/ltc.h>
#include <subdev/clock.h>
#include <subdev/clock/pll.h>
@ -425,7 +425,7 @@ extern const u8 nvc0_pte_storage_type_map[256];
void
nvc0_ram_put(struct nouveau_fb *pfb, struct nouveau_mem **pmem)
{
struct nouveau_ltcg *ltcg = nouveau_ltcg(pfb);
struct nouveau_ltc *ltc = nouveau_ltc(pfb);
struct nouveau_mem *mem = *pmem;
*pmem = NULL;
@ -434,7 +434,7 @@ nvc0_ram_put(struct nouveau_fb *pfb, struct nouveau_mem **pmem)
mutex_lock(&pfb->base.mutex);
if (mem->tag)
ltcg->tags_free(ltcg, &mem->tag);
ltc->tags_free(ltc, &mem->tag);
__nv50_ram_put(pfb, mem);
mutex_unlock(&pfb->base.mutex);
@ -468,12 +468,12 @@ nvc0_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin,
mutex_lock(&pfb->base.mutex);
if (comp) {
struct nouveau_ltcg *ltcg = nouveau_ltcg(pfb);
struct nouveau_ltc *ltc = nouveau_ltc(pfb);
/* compression only works with lpages */
if (align == (1 << (17 - 12))) {
int n = size >> 5;
ltcg->tags_alloc(ltcg, n, &mem->tag);
ltc->tags_alloc(ltc, n, &mem->tag);
}
if (unlikely(!mem->tag))

80
drivers/gpu/drm/nouveau/core/subdev/ltc/base.c Normal file
View File

@ -0,0 +1,80 @@
/*
* Copyright 2014 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#include "priv.h"
static int
nvkm_ltc_tags_alloc(struct nouveau_ltc *ltc, u32 n,
struct nouveau_mm_node **pnode)
{
struct nvkm_ltc_priv *priv = (void *)ltc;
int ret;
ret = nouveau_mm_head(&priv->tags, 1, n, n, 1, pnode);
if (ret)
*pnode = NULL;
return ret;
}
static void
nvkm_ltc_tags_free(struct nouveau_ltc *ltc, struct nouveau_mm_node **pnode)
{
struct nvkm_ltc_priv *priv = (void *)ltc;
nouveau_mm_free(&priv->tags, pnode);
}
static void
nvkm_ltc_tags_clear(struct nouveau_ltc *ltc, u32 first, u32 count)
{
const struct nvkm_ltc_impl *impl = (void *)nv_oclass(ltc);
struct nvkm_ltc_priv *priv = (void *)ltc;
const u32 limit = first + count - 1;
BUG_ON((first > limit) || (limit >= priv->num_tags));
impl->cbc_clear(priv, first, limit);
impl->cbc_wait(priv);
}
int
nvkm_ltc_create_(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, int length, void **pobject)
{
const struct nvkm_ltc_impl *impl = (void *)oclass;
struct nvkm_ltc_priv *priv;
int ret;
ret = nouveau_subdev_create_(parent, engine, oclass, 0, "PLTCG",
"l2c", length, pobject);
priv = *pobject;
if (ret)
return ret;
priv->base.base.intr = impl->intr;
priv->base.tags_alloc = nvkm_ltc_tags_alloc;
priv->base.tags_free = nvkm_ltc_tags_free;
priv->base.tags_clear = nvkm_ltc_tags_clear;
return 0;
}

145
drivers/gpu/drm/nouveau/core/subdev/ltcg/gf100.c → drivers/gpu/drm/nouveau/core/subdev/ltc/gf100.c
View File

@ -25,10 +25,28 @@
#include <subdev/fb.h>
#include <subdev/timer.h>
#include "gf100.h"
#include "priv.h"
void
gf100_ltc_cbc_clear(struct nvkm_ltc_priv *priv, u32 start, u32 limit)
{
nv_wr32(priv, 0x17e8cc, start);
nv_wr32(priv, 0x17e8d0, limit);
nv_wr32(priv, 0x17e8c8, 0x00000004);
}
void
gf100_ltc_cbc_wait(struct nvkm_ltc_priv *priv)
{
int c, s;
for (c = 0; c < priv->ltc_nr; c++) {
for (s = 0; s < priv->lts_nr; s++)
nv_wait(priv, 0x1410c8 + c * 0x2000 + s * 0x400, ~0, 0);
}
}
static void
gf100_ltcg_lts_isr(struct gf100_ltcg_priv *priv, int ltc, int lts)
gf100_ltc_lts_isr(struct nvkm_ltc_priv *priv, int ltc, int lts)
{
u32 base = 0x141000 + (ltc * 0x2000) + (lts * 0x400);
u32 stat = nv_rd32(priv, base + 0x020);
@ -39,17 +57,17 @@ gf100_ltcg_lts_isr(struct gf100_ltcg_priv *priv, int ltc, int lts)
}
}
static void
gf100_ltcg_intr(struct nouveau_subdev *subdev)
void
gf100_ltc_intr(struct nouveau_subdev *subdev)
{
struct gf100_ltcg_priv *priv = (void *)subdev;
struct nvkm_ltc_priv *priv = (void *)subdev;
u32 mask;
mask = nv_rd32(priv, 0x00017c);
while (mask) {
u32 lts, ltc = __ffs(mask);
for (lts = 0; lts < priv->lts_nr; lts++)
gf100_ltcg_lts_isr(priv, ltc, lts);
gf100_ltc_lts_isr(priv, ltc, lts);
mask &= ~(1 << ltc);
}
@ -59,52 +77,38 @@ gf100_ltcg_intr(struct nouveau_subdev *subdev)
nv_mask(priv, 0x000640, 0x02000000, 0x00000000);
}
int
gf100_ltcg_tags_alloc(struct nouveau_ltcg *ltcg, u32 n,
struct nouveau_mm_node **pnode)
static int
gf100_ltc_init(struct nouveau_object *object)
{
struct gf100_ltcg_priv *priv = (struct gf100_ltcg_priv *)ltcg;
struct nvkm_ltc_priv *priv = (void *)object;
int ret;
ret = nouveau_mm_head(&priv->tags, 1, n, n, 1, pnode);
ret = nvkm_ltc_init(priv);
if (ret)
*pnode = NULL;
return ret;
return ret;
nv_mask(priv, 0x17e820, 0x00100000, 0x00000000); /* INTR_EN &= ~0x10 */
nv_wr32(priv, 0x17e8d8, priv->ltc_nr);
nv_wr32(priv, 0x17e8d4, priv->tag_base);
return 0;
}
void
gf100_ltcg_tags_free(struct nouveau_ltcg *ltcg, struct nouveau_mm_node **pnode)
gf100_ltc_dtor(struct nouveau_object *object)
{
struct gf100_ltcg_priv *priv = (struct gf100_ltcg_priv *)ltcg;
struct nouveau_fb *pfb = nouveau_fb(object);
struct nvkm_ltc_priv *priv = (void *)object;
nouveau_mm_free(&priv->tags, pnode);
}
nouveau_mm_fini(&priv->tags);
nouveau_mm_free(&pfb->vram, &priv->tag_ram);
static void
gf100_ltcg_tags_clear(struct nouveau_ltcg *ltcg, u32 first, u32 count)
{
struct gf100_ltcg_priv *priv = (struct gf100_ltcg_priv *)ltcg;
u32 last = first + count - 1;
int p, i;
BUG_ON((first > last) || (last >= priv->num_tags));
nv_wr32(priv, 0x17e8cc, first);
nv_wr32(priv, 0x17e8d0, last);
nv_wr32(priv, 0x17e8c8, 0x4); /* trigger clear */
/* wait until it's finished with clearing */
for (p = 0; p < priv->ltc_nr; ++p) {
for (i = 0; i < priv->lts_nr; ++i)
nv_wait(priv, 0x1410c8 + p * 0x2000 + i * 0x400, ~0, 0);
}
nvkm_ltc_destroy(priv);
}
/* TODO: Figure out tag memory details and drop the over-cautious allocation.
*/
int
gf100_ltcg_init_tag_ram(struct nouveau_fb *pfb, struct gf100_ltcg_priv *priv)
gf100_ltc_init_tag_ram(struct nouveau_fb *pfb, struct nvkm_ltc_priv *priv)
{
u32 tag_size, tag_margin, tag_align;
int ret;
@ -142,22 +146,22 @@ gf100_ltcg_init_tag_ram(struct nouveau_fb *pfb, struct gf100_ltcg_priv *priv)
priv->tag_base = tag_base;
}
ret = nouveau_mm_init(&priv->tags, 0, priv->num_tags, 1);
ret = nouveau_mm_init(&priv->tags, 0, priv->num_tags, 1);
return ret;
}
static int
gf100_ltcg_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
int
gf100_ltc_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct gf100_ltcg_priv *priv;
struct nouveau_fb *pfb = nouveau_fb(parent);
struct nvkm_ltc_priv *priv;
u32 parts, mask;
int ret, i;
ret = nouveau_ltcg_create(parent, engine, oclass, &priv);
ret = nvkm_ltc_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@ -170,57 +174,24 @@ gf100_ltcg_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
}
priv->lts_nr = nv_rd32(priv, 0x17e8dc) >> 28;
ret = gf100_ltcg_init_tag_ram(pfb, priv);
ret = gf100_ltc_init_tag_ram(pfb, priv);
if (ret)
return ret;
priv->base.tags_alloc = gf100_ltcg_tags_alloc;
priv->base.tags_free = gf100_ltcg_tags_free;
priv->base.tags_clear = gf100_ltcg_tags_clear;
nv_subdev(priv)->intr = gf100_ltcg_intr;
return 0;
}
void
gf100_ltcg_dtor(struct nouveau_object *object)
{
struct nouveau_ltcg *ltcg = (struct nouveau_ltcg *)object;
struct gf100_ltcg_priv *priv = (struct gf100_ltcg_priv *)ltcg;
struct nouveau_fb *pfb = nouveau_fb(ltcg->base.base.parent);
nouveau_mm_fini(&priv->tags);
nouveau_mm_free(&pfb->vram, &priv->tag_ram);
nouveau_ltcg_destroy(ltcg);
}
static int
gf100_ltcg_init(struct nouveau_object *object)
{
struct nouveau_ltcg *ltcg = (struct nouveau_ltcg *)object;
struct gf100_ltcg_priv *priv = (struct gf100_ltcg_priv *)ltcg;
int ret;
ret = nouveau_ltcg_init(ltcg);
if (ret)
return ret;
nv_mask(priv, 0x17e820, 0x00100000, 0x00000000); /* INTR_EN &= ~0x10 */
nv_wr32(priv, 0x17e8d8, priv->ltc_nr);
if (nv_device(ltcg)->card_type >= NV_E0)
nv_wr32(priv, 0x17e000, priv->ltc_nr);
nv_wr32(priv, 0x17e8d4, priv->tag_base);
nv_subdev(priv)->intr = gf100_ltc_intr;
return 0;
}
struct nouveau_oclass *
gf100_ltcg_oclass = &(struct nouveau_oclass) {
.handle = NV_SUBDEV(LTCG, 0xc0),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = gf100_ltcg_ctor,
.dtor = gf100_ltcg_dtor,
.init = gf100_ltcg_init,
.fini = _nouveau_ltcg_fini,
gf100_ltc_oclass = &(struct nvkm_ltc_impl) {
.base.handle = NV_SUBDEV(LTC, 0xc0),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = gf100_ltc_ctor,
.dtor = gf100_ltc_dtor,
.init = gf100_ltc_init,
.fini = _nvkm_ltc_fini,
},
};
.intr = gf100_ltc_intr,
.cbc_clear = gf100_ltc_cbc_clear,
.cbc_wait = gf100_ltc_cbc_wait,
}.base;

55
drivers/gpu/drm/nouveau/core/subdev/ltc/gk104.c Normal file
View File

@ -0,0 +1,55 @@
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "priv.h"
static int
gk104_ltc_init(struct nouveau_object *object)
{
struct nvkm_ltc_priv *priv = (void *)object;
int ret;
ret = nvkm_ltc_init(priv);
if (ret)
return ret;
nv_wr32(priv, 0x17e8d8, priv->ltc_nr);
nv_wr32(priv, 0x17e000, priv->ltc_nr);
nv_wr32(priv, 0x17e8d4, priv->tag_base);
return 0;
}
struct nouveau_oclass *
gk104_ltc_oclass = &(struct nvkm_ltc_impl) {
.base.handle = NV_SUBDEV(LTC, 0xe4),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = gf100_ltc_ctor,
.dtor = gf100_ltc_dtor,
.init = gk104_ltc_init,
.fini = _nvkm_ltc_fini,
},
.intr = gf100_ltc_intr,
.cbc_clear = gf100_ltc_cbc_clear,
.cbc_wait = gf100_ltc_cbc_wait,
}.base;

101
drivers/gpu/drm/nouveau/core/subdev/ltcg/gm107.c → drivers/gpu/drm/nouveau/core/subdev/ltc/gm107.c
View File

@ -25,10 +25,28 @@
#include <subdev/fb.h>
#include <subdev/timer.h>
#include "gf100.h"
#include "priv.h"
static void
gm107_ltcg_lts_isr(struct gf100_ltcg_priv *priv, int ltc, int lts)
gm107_ltc_cbc_clear(struct nvkm_ltc_priv *priv, u32 start, u32 limit)
{
nv_wr32(priv, 0x17e270, start);
nv_wr32(priv, 0x17e274, limit);
nv_wr32(priv, 0x17e26c, 0x00000004);
}
static void
gm107_ltc_cbc_wait(struct nvkm_ltc_priv *priv)
{
int c, s;
for (c = 0; c < priv->ltc_nr; c++) {
for (s = 0; s < priv->lts_nr; s++)
nv_wait(priv, 0x14046c + c * 0x2000 + s * 0x200, ~0, 0);
}
}
static void
gm107_ltc_lts_isr(struct nvkm_ltc_priv *priv, int ltc, int lts)
{
u32 base = 0x140000 + (ltc * 0x2000) + (lts * 0x400);
u32 stat = nv_rd32(priv, base + 0x00c);
@ -40,16 +58,16 @@ gm107_ltcg_lts_isr(struct gf100_ltcg_priv *priv, int ltc, int lts)
}
static void
gm107_ltcg_intr(struct nouveau_subdev *subdev)
gm107_ltc_intr(struct nouveau_subdev *subdev)
{
struct gf100_ltcg_priv *priv = (void *)subdev;
struct nvkm_ltc_priv *priv = (void *)subdev;
u32 mask;
mask = nv_rd32(priv, 0x00017c);
while (mask) {
u32 lts, ltc = __ffs(mask);
for (lts = 0; lts < priv->lts_nr; lts++)
gm107_ltcg_lts_isr(priv, ltc, lts);
gm107_ltc_lts_isr(priv, ltc, lts);
mask &= ~(1 << ltc);
}
@ -59,37 +77,32 @@ gm107_ltcg_intr(struct nouveau_subdev *subdev)
nv_mask(priv, 0x000640, 0x02000000, 0x00000000);
}
static void
gm107_ltcg_tags_clear(struct nouveau_ltcg *ltcg, u32 first, u32 count)
static int
gm107_ltc_init(struct nouveau_object *object)
{
struct gf100_ltcg_priv *priv = (struct gf100_ltcg_priv *)ltcg;
u32 last = first + count - 1;
int p, i;
struct nvkm_ltc_priv *priv = (void *)object;
int ret;
BUG_ON((first > last) || (last >= priv->num_tags));
ret = nvkm_ltc_init(priv);
if (ret)
return ret;
nv_wr32(priv, 0x17e270, first);
nv_wr32(priv, 0x17e274, last);
nv_wr32(priv, 0x17e26c, 0x4); /* trigger clear */
/* wait until it's finished with clearing */
for (p = 0; p < priv->ltc_nr; ++p) {
for (i = 0; i < priv->lts_nr; ++i)
nv_wait(priv, 0x14046c + p * 0x2000 + i * 0x200, ~0, 0);
}
nv_wr32(priv, 0x17e27c, priv->ltc_nr);
nv_wr32(priv, 0x17e278, priv->tag_base);
return 0;
}
static int
gm107_ltcg_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
gm107_ltc_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct gf100_ltcg_priv *priv;
struct nouveau_fb *pfb = nouveau_fb(parent);
struct nvkm_ltc_priv *priv;
u32 parts, mask;
int ret, i;
ret = nouveau_ltcg_create(parent, engine, oclass, &priv);
ret = nvkm_ltc_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@ -102,41 +115,23 @@ gm107_ltcg_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
}
priv->lts_nr = nv_rd32(priv, 0x17e280) >> 28;
ret = gf100_ltcg_init_tag_ram(pfb, priv);
ret = gf100_ltc_init_tag_ram(pfb, priv);
if (ret)
return ret;
priv->base.tags_alloc = gf100_ltcg_tags_alloc;
priv->base.tags_free = gf100_ltcg_tags_free;
priv->base.tags_clear = gm107_ltcg_tags_clear;
nv_subdev(priv)->intr = gm107_ltcg_intr;
return 0;
}
static int
gm107_ltcg_init(struct nouveau_object *object)
{
struct nouveau_ltcg *ltcg = (struct nouveau_ltcg *)object;
struct gf100_ltcg_priv *priv = (struct gf100_ltcg_priv *)ltcg;
int ret;
ret = nouveau_ltcg_init(ltcg);
if (ret)
return ret;
nv_wr32(priv, 0x17e27c, priv->ltc_nr);
nv_wr32(priv, 0x17e278, priv->tag_base);
return 0;
}
struct nouveau_oclass *
gm107_ltcg_oclass = &(struct nouveau_oclass) {
.handle = NV_SUBDEV(LTCG, 0xff),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = gm107_ltcg_ctor,
.dtor = gf100_ltcg_dtor,
.init = gm107_ltcg_init,
.fini = _nouveau_ltcg_fini,
gm107_ltc_oclass = &(struct nvkm_ltc_impl) {
.base.handle = NV_SUBDEV(LTC, 0xff),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = gm107_ltc_ctor,
.dtor = gf100_ltc_dtor,
.init = gm107_ltc_init,
.fini = _nvkm_ltc_fini,
},
};
.intr = gm107_ltc_intr,
.cbc_clear = gm107_ltc_cbc_clear,
.cbc_wait = gm107_ltc_cbc_wait,
}.base;

58
drivers/gpu/drm/nouveau/core/subdev/ltc/priv.h Normal file
View File

@ -0,0 +1,58 @@
#ifndef __NVKM_LTC_PRIV_H__
#define __NVKM_LTC_PRIV_H__
#include <subdev/ltc.h>
#include <subdev/fb.h>
struct nvkm_ltc_priv {
struct nouveau_ltc base;
u32 ltc_nr;
u32 lts_nr;
u32 num_tags;
u32 tag_base;
struct nouveau_mm tags;
struct nouveau_mm_node *tag_ram;
};
#define nvkm_ltc_create(p,e,o,d) \
nvkm_ltc_create_((p), (e), (o), sizeof(**d), (void **)d)
#define nvkm_ltc_destroy(p) ({ \
struct nvkm_ltc_priv *_priv = (p); \
_nvkm_ltc_dtor(nv_object(_priv)); \
})
#define nvkm_ltc_init(p) ({ \
struct nvkm_ltc_priv *_priv = (p); \
_nvkm_ltc_init(nv_object(_priv)); \
})
#define nvkm_ltc_fini(p,s) ({ \
struct nvkm_ltc_priv *_priv = (p); \
_nvkm_ltc_fini(nv_object(_priv), (s)); \
})
int nvkm_ltc_create_(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, int, void **);
#define _nvkm_ltc_dtor _nouveau_subdev_dtor
#define _nvkm_ltc_init _nouveau_subdev_init
#define _nvkm_ltc_fini _nouveau_subdev_fini
int gf100_ltc_ctor(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, void *, u32,
struct nouveau_object **);
void gf100_ltc_dtor(struct nouveau_object *);
int gf100_ltc_init_tag_ram(struct nouveau_fb *, struct nvkm_ltc_priv *);
int gf100_ltc_tags_alloc(struct nouveau_ltc *, u32, struct nouveau_mm_node **);
void gf100_ltc_tags_free(struct nouveau_ltc *, struct nouveau_mm_node **);
struct nvkm_ltc_impl {
struct nouveau_oclass base;
void (*intr)(struct nouveau_subdev *);
void (*cbc_clear)(struct nvkm_ltc_priv *, u32 start, u32 limit);
void (*cbc_wait)(struct nvkm_ltc_priv *);
};
void gf100_ltc_intr(struct nouveau_subdev *);
void gf100_ltc_cbc_clear(struct nvkm_ltc_priv *, u32, u32);
void gf100_ltc_cbc_wait(struct nvkm_ltc_priv *);
#endif

21
drivers/gpu/drm/nouveau/core/subdev/ltcg/gf100.h
View File

@ -1,21 +0,0 @@
#ifndef __NVKM_LTCG_PRIV_GF100_H__
#define __NVKM_LTCG_PRIV_GF100_H__
#include <subdev/ltcg.h>
struct gf100_ltcg_priv {
struct nouveau_ltcg base;
u32 ltc_nr;
u32 lts_nr;
u32 num_tags;
u32 tag_base;
struct nouveau_mm tags;
struct nouveau_mm_node *tag_ram;
};
void gf100_ltcg_dtor(struct nouveau_object *);
int gf100_ltcg_init_tag_ram(struct nouveau_fb *, struct gf100_ltcg_priv *);
int gf100_ltcg_tags_alloc(struct nouveau_ltcg *, u32, struct nouveau_mm_node **);
void gf100_ltcg_tags_free(struct nouveau_ltcg *, struct nouveau_mm_node **);
#endif

2
drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c
View File

@ -41,7 +41,7 @@ nvc0_mc_intr[] = {
{ 0x00200000, NVDEV_SUBDEV_GPIO }, /* PMGR->GPIO */
{ 0x00200000, NVDEV_SUBDEV_I2C }, /* PMGR->I2C/AUX */
{ 0x01000000, NVDEV_SUBDEV_PWR },
{ 0x02000000, NVDEV_SUBDEV_LTCG },
{ 0x02000000, NVDEV_SUBDEV_LTC },
{ 0x08000000, NVDEV_SUBDEV_FB },
{ 0x10000000, NVDEV_SUBDEV_BUS },
{ 0x40000000, NVDEV_SUBDEV_IBUS },

8
drivers/gpu/drm/nouveau/core/subdev/vm/nvc0.c
View File

@ -28,7 +28,7 @@
#include <subdev/timer.h>
#include <subdev/fb.h>
#include <subdev/vm.h>
#include <subdev/ltcg.h>
#include <subdev/ltc.h>
#include <subdev/bar.h>
struct nvc0_vmmgr_priv {
@ -116,12 +116,12 @@ nvc0_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
pte <<= 3;
if (mem->tag) {
struct nouveau_ltcg *ltcg =
nouveau_ltcg(vma->vm->vmm->base.base.parent);
struct nouveau_ltc *ltc =
nouveau_ltc(vma->vm->vmm->base.base.parent);
u32 tag = mem->tag->offset + (delta >> 17);
phys |= (u64)tag << (32 + 12);
next |= (u64)1 << (32 + 12);
ltcg->tags_clear(ltcg, tag, cnt);
ltc->tags_clear(ltc, tag, cnt);
}
while (cnt--) {