irqchip/mbigen: Create irq domain for each mbigen device
For peripheral devices which connect to mbigen,mbigen is a interrupt controller. So, we create irq domain for each mbigen device and add mbigen irq domain into irq hierarchy structure. Signed-off-by: Ma Jun <majun258@huawei.com> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
This commit is contained in:
Ma Jun
Marc Zyngier
parent
717c3dbc11
commit
9650c60ebf
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@ -16,13 +16,39 @@
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/interrupt.h>
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#include <linux/irqchip.h>
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#include <linux/module.h>
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#include <linux/msi.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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/* Interrupt numbers per mbigen node supported */
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#define IRQS_PER_MBIGEN_NODE 128
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/* 64 irqs (Pin0-pin63) are reserved for each mbigen chip */
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#define RESERVED_IRQ_PER_MBIGEN_CHIP 64
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/* The maximum IRQ pin number of mbigen chip(start from 0) */
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#define MAXIMUM_IRQ_PIN_NUM 1407
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/**
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* In mbigen vector register
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* bit[21:12]: event id value
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* bit[11:0]: device id
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*/
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#define IRQ_EVENT_ID_SHIFT 12
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#define IRQ_EVENT_ID_MASK 0x3ff
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/* register range of each mbigen node */
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#define MBIGEN_NODE_OFFSET 0x1000
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/* offset of vector register in mbigen node */
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#define REG_MBIGEN_VEC_OFFSET 0x200
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/**
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* struct mbigen_device - holds the information of mbigen device.
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*
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@ -34,10 +60,107 @@ struct mbigen_device {
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void __iomem *base;
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};
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static inline unsigned int get_mbigen_vec_reg(irq_hw_number_t hwirq)
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{
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unsigned int nid, pin;
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hwirq -= RESERVED_IRQ_PER_MBIGEN_CHIP;
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nid = hwirq / IRQS_PER_MBIGEN_NODE + 1;
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pin = hwirq % IRQS_PER_MBIGEN_NODE;
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return pin * 4 + nid * MBIGEN_NODE_OFFSET
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+ REG_MBIGEN_VEC_OFFSET;
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}
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static struct irq_chip mbigen_irq_chip = {
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.name = "mbigen-v2",
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};
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static void mbigen_write_msg(struct msi_desc *desc, struct msi_msg *msg)
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{
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struct irq_data *d = irq_get_irq_data(desc->irq);
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void __iomem *base = d->chip_data;
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u32 val;
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base += get_mbigen_vec_reg(d->hwirq);
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val = readl_relaxed(base);
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val &= ~(IRQ_EVENT_ID_MASK << IRQ_EVENT_ID_SHIFT);
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val |= (msg->data << IRQ_EVENT_ID_SHIFT);
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/* The address of doorbell is encoded in mbigen register by default
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* So,we don't need to program the doorbell address at here
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*/
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writel_relaxed(val, base);
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}
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static int mbigen_domain_translate(struct irq_domain *d,
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struct irq_fwspec *fwspec,
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unsigned long *hwirq,
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unsigned int *type)
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{
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if (is_of_node(fwspec->fwnode)) {
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if (fwspec->param_count != 2)
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return -EINVAL;
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if ((fwspec->param[0] > MAXIMUM_IRQ_PIN_NUM) ||
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(fwspec->param[0] < RESERVED_IRQ_PER_MBIGEN_CHIP))
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return -EINVAL;
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else
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*hwirq = fwspec->param[0];
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/* If there is no valid irq type, just use the default type */
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if ((fwspec->param[1] == IRQ_TYPE_EDGE_RISING) ||
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(fwspec->param[1] == IRQ_TYPE_LEVEL_HIGH))
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*type = fwspec->param[1];
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else
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return -EINVAL;
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return 0;
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}
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return -EINVAL;
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}
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static int mbigen_irq_domain_alloc(struct irq_domain *domain,
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unsigned int virq,
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unsigned int nr_irqs,
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void *args)
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{
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struct irq_fwspec *fwspec = args;
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irq_hw_number_t hwirq;
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unsigned int type;
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struct mbigen_device *mgn_chip;
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int i, err;
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err = mbigen_domain_translate(domain, fwspec, &hwirq, &type);
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if (err)
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return err;
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err = platform_msi_domain_alloc(domain, virq, nr_irqs);
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if (err)
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return err;
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mgn_chip = platform_msi_get_host_data(domain);
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for (i = 0; i < nr_irqs; i++)
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irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
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&mbigen_irq_chip, mgn_chip->base);
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return 0;
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}
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static struct irq_domain_ops mbigen_domain_ops = {
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.translate = mbigen_domain_translate,
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.alloc = mbigen_irq_domain_alloc,
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.free = irq_domain_free_irqs_common,
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};
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static int mbigen_device_probe(struct platform_device *pdev)
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{
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struct mbigen_device *mgn_chip;
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struct resource *res;
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struct irq_domain *domain;
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u32 num_pins;
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mgn_chip = devm_kzalloc(&pdev->dev, sizeof(*mgn_chip), GFP_KERNEL);
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if (!mgn_chip)
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@ -50,8 +173,23 @@ static int mbigen_device_probe(struct platform_device *pdev)
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if (IS_ERR(mgn_chip->base))
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return PTR_ERR(mgn_chip->base);
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if (of_property_read_u32(pdev->dev.of_node, "num-pins", &num_pins) < 0) {
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dev_err(&pdev->dev, "No num-pins property\n");
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return -EINVAL;
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}
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domain = platform_msi_create_device_domain(&pdev->dev, num_pins,
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mbigen_write_msg,
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&mbigen_domain_ops,
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mgn_chip);
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if (!domain)
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return -ENOMEM;
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platform_set_drvdata(pdev, mgn_chip);
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dev_info(&pdev->dev, "Allocated %d MSIs\n", num_pins);
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return 0;
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}
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