arm64: tegra: Add SOR power-domain for Tegra210
Add node for SOR power-domain for Tegra210 and populate the SOR power-domain phandle for DPAUX, DSI, MIPI-CAL and SOR and nodes that are dependent on this power-domain. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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@ -34,6 +34,7 @@
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clock-names = "dpaux", "parent";
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clock-names = "dpaux", "parent";
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resets = <&tegra_car 207>;
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resets = <&tegra_car 207>;
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reset-names = "dpaux";
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reset-names = "dpaux";
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power-domains = <&pd_sor>;
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status = "disabled";
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status = "disabled";
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state_dpaux1_aux: pinmux-aux {
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state_dpaux1_aux: pinmux-aux {
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@ -108,6 +109,7 @@
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clock-names = "dsi", "lp", "parent";
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clock-names = "dsi", "lp", "parent";
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resets = <&tegra_car 48>;
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resets = <&tegra_car 48>;
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reset-names = "dsi";
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reset-names = "dsi";
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power-domains = <&pd_sor>;
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nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */
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nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */
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status = "disabled";
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status = "disabled";
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@ -137,6 +139,7 @@
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clock-names = "dsi", "lp", "parent";
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clock-names = "dsi", "lp", "parent";
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resets = <&tegra_car 82>;
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resets = <&tegra_car 82>;
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reset-names = "dsi";
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reset-names = "dsi";
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power-domains = <&pd_sor>;
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nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */
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nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */
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status = "disabled";
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status = "disabled";
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@ -178,6 +181,7 @@
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pinctrl-1 = <&state_dpaux_i2c>;
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pinctrl-1 = <&state_dpaux_i2c>;
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pinctrl-2 = <&state_dpaux_off>;
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pinctrl-2 = <&state_dpaux_off>;
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pinctrl-names = "aux", "i2c", "off";
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pinctrl-names = "aux", "i2c", "off";
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power-domains = <&pd_sor>;
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status = "disabled";
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status = "disabled";
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};
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};
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@ -197,6 +201,7 @@
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pinctrl-1 = <&state_dpaux1_i2c>;
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pinctrl-1 = <&state_dpaux1_i2c>;
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pinctrl-2 = <&state_dpaux1_off>;
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pinctrl-2 = <&state_dpaux1_off>;
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pinctrl-names = "aux", "i2c", "off";
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pinctrl-names = "aux", "i2c", "off";
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power-domains = <&pd_sor>;
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status = "disabled";
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status = "disabled";
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};
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};
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@ -209,6 +214,7 @@
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clock-names = "dpaux", "parent";
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clock-names = "dpaux", "parent";
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resets = <&tegra_car 181>;
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resets = <&tegra_car 181>;
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reset-names = "dpaux";
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reset-names = "dpaux";
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power-domains = <&pd_sor>;
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status = "disabled";
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status = "disabled";
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state_dpaux_aux: pinmux-aux {
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state_dpaux_aux: pinmux-aux {
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@ -648,6 +654,26 @@
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#power-domain-cells = <0>;
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#power-domain-cells = <0>;
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};
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};
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pd_sor: sor {
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clocks = <&tegra_car TEGRA210_CLK_SOR0>,
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<&tegra_car TEGRA210_CLK_SOR1>,
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<&tegra_car TEGRA210_CLK_CSI>,
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<&tegra_car TEGRA210_CLK_DSIA>,
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<&tegra_car TEGRA210_CLK_DSIB>,
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<&tegra_car TEGRA210_CLK_DPAUX>,
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<&tegra_car TEGRA210_CLK_DPAUX1>,
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<&tegra_car TEGRA210_CLK_MIPI_CAL>;
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resets = <&tegra_car TEGRA210_CLK_SOR0>,
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<&tegra_car TEGRA210_CLK_SOR1>,
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<&tegra_car TEGRA210_CLK_CSI>,
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<&tegra_car TEGRA210_CLK_DSIA>,
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<&tegra_car TEGRA210_CLK_DSIB>,
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<&tegra_car TEGRA210_CLK_DPAUX>,
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<&tegra_car TEGRA210_CLK_DPAUX1>,
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<&tegra_car TEGRA210_CLK_MIPI_CAL>;
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#power-domain-cells = <0>;
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};
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pd_xusbss: xusba {
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pd_xusbss: xusba {
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clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
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clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
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resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
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resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
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@ -942,6 +968,7 @@
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reg = <0x0 0x700e3000 0x0 0x100>;
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reg = <0x0 0x700e3000 0x0 0x100>;
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clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>;
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clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>;
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clock-names = "mipi-cal";
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clock-names = "mipi-cal";
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power-domains = <&pd_sor>;
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#nvidia,mipi-calibrate-cells = <1>;
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#nvidia,mipi-calibrate-cells = <1>;
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};
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};
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