Merge HEAD from master.kernel.org:/home/rmk/linux-2.6-arm.git
This commit is contained in:
Linus Torvalds
commit
97c169a21b
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@ -635,10 +635,6 @@ config PM
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and the Battery Powered Linux mini-HOWTO, available from
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<http://www.tldp.org/docs.html#howto>.
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Note that, even if you say N here, Linux on the x86 architecture
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will issue the hlt instruction if nothing is to be done, thereby
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sending the processor to sleep and saving power.
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config APM
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tristate "Advanced Power Management Emulation"
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depends on PM
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@ -650,12 +646,6 @@ config APM
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battery status information, and user-space programs will receive
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notification of APM "events" (e.g. battery status change).
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If you select "Y" here, you can disable actual use of the APM
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BIOS by passing the "apm=off" option to the kernel at boot time.
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Note that the APM support is almost completely disabled for
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machines with more than one CPU.
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In order to use APM, you will need supporting software. For location
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and more information, read <file:Documentation/pm.txt> and the
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Battery Powered Linux mini-HOWTO, available from
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@ -665,39 +655,12 @@ config APM
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manpage ("man 8 hdparm") for that), and it doesn't turn off
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VESA-compliant "green" monitors.
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This driver does not support the TI 4000M TravelMate and the ACER
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486/DX4/75 because they don't have compliant BIOSes. Many "green"
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desktop machines also don't have compliant BIOSes, and this driver
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may cause those machines to panic during the boot phase.
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Generally, if you don't have a battery in your machine, there isn't
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much point in using this driver and you should say N. If you get
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random kernel OOPSes or reboots that don't seem to be related to
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anything, try disabling/enabling this option (or disabling/enabling
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APM in your BIOS).
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Some other things you should try when experiencing seemingly random,
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"weird" problems:
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1) make sure that you have enough swap space and that it is
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enabled.
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2) pass the "no-hlt" option to the kernel
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3) switch on floating point emulation in the kernel and pass
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the "no387" option to the kernel
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4) pass the "floppy=nodma" option to the kernel
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5) pass the "mem=4M" option to the kernel (thereby disabling
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all but the first 4 MB of RAM)
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6) make sure that the CPU is not over clocked.
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7) read the sig11 FAQ at <http://www.bitwizard.nl/sig11/>
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8) disable the cache from your BIOS settings
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9) install a fan for the video card or exchange video RAM
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10) install a better fan for the CPU
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11) exchange RAM chips
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12) exchange the motherboard.
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To compile this driver as a module, choose M here: the
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module will be called apm.
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endmenu
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source "net/Kconfig"
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@ -1,6 +1,9 @@
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config ICST525
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bool
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config ARM_GIC
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bool
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config ICST307
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bool
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@ -4,6 +4,7 @@
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obj-y += rtctime.o
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obj-$(CONFIG_ARM_AMBA) += amba.o
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obj-$(CONFIG_ARM_GIC) += gic.o
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obj-$(CONFIG_ICST525) += icst525.o
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obj-$(CONFIG_ICST307) += icst307.o
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obj-$(CONFIG_SA1111) += sa1111.o
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@ -0,0 +1,166 @@
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/*
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* linux/arch/arm/common/gic.c
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*
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* Copyright (C) 2002 ARM Limited, All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Interrupt architecture for the GIC:
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*
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* o There is one Interrupt Distributor, which receives interrupts
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* from system devices and sends them to the Interrupt Controllers.
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*
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* o There is one CPU Interface per CPU, which sends interrupts sent
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* by the Distributor, and interrupts generated locally, to the
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* associated CPU.
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*
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* Note that IRQs 0-31 are special - they are local to each CPU.
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* As such, the enable set/clear, pending set/clear and active bit
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* registers are banked per-cpu for these sources.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/smp.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#include <asm/mach/irq.h>
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#include <asm/hardware/gic.h>
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static void __iomem *gic_dist_base;
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static void __iomem *gic_cpu_base;
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/*
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* Routines to acknowledge, disable and enable interrupts
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*
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* Linux assumes that when we're done with an interrupt we need to
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* unmask it, in the same way we need to unmask an interrupt when
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* we first enable it.
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*
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* The GIC has a seperate notion of "end of interrupt" to re-enable
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* an interrupt after handling, in order to support hardware
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* prioritisation.
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*
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* We can make the GIC behave in the way that Linux expects by making
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* our "acknowledge" routine disable the interrupt, then mark it as
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* complete.
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*/
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static void gic_ack_irq(unsigned int irq)
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{
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u32 mask = 1 << (irq % 32);
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writel(mask, gic_dist_base + GIC_DIST_ENABLE_CLEAR + (irq / 32) * 4);
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writel(irq, gic_cpu_base + GIC_CPU_EOI);
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}
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static void gic_mask_irq(unsigned int irq)
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{
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u32 mask = 1 << (irq % 32);
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writel(mask, gic_dist_base + GIC_DIST_ENABLE_CLEAR + (irq / 32) * 4);
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}
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static void gic_unmask_irq(unsigned int irq)
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{
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u32 mask = 1 << (irq % 32);
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writel(mask, gic_dist_base + GIC_DIST_ENABLE_SET + (irq / 32) * 4);
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}
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static void gic_set_cpu(struct irqdesc *desc, unsigned int irq, unsigned int cpu)
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{
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void __iomem *reg = gic_dist_base + GIC_DIST_TARGET + (irq & ~3);
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unsigned int shift = (irq % 4) * 8;
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u32 val;
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val = readl(reg) & ~(0xff << shift);
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val |= 1 << (cpu + shift);
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writel(val, reg);
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}
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static struct irqchip gic_chip = {
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.ack = gic_ack_irq,
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.mask = gic_mask_irq,
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.unmask = gic_unmask_irq,
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#ifdef CONFIG_SMP
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.set_cpu = gic_set_cpu,
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#endif
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};
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void __init gic_dist_init(void __iomem *base)
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{
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unsigned int max_irq, i;
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u32 cpumask = 1 << smp_processor_id();
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cpumask |= cpumask << 8;
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cpumask |= cpumask << 16;
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gic_dist_base = base;
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writel(0, base + GIC_DIST_CTRL);
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/*
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* Find out how many interrupts are supported.
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*/
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max_irq = readl(base + GIC_DIST_CTR) & 0x1f;
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max_irq = (max_irq + 1) * 32;
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/*
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* The GIC only supports up to 1020 interrupt sources.
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* Limit this to either the architected maximum, or the
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* platform maximum.
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*/
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if (max_irq > max(1020, NR_IRQS))
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max_irq = max(1020, NR_IRQS);
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/*
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* Set all global interrupts to be level triggered, active low.
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*/
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for (i = 32; i < max_irq; i += 16)
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writel(0, base + GIC_DIST_CONFIG + i * 4 / 16);
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/*
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* Set all global interrupts to this CPU only.
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*/
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for (i = 32; i < max_irq; i += 4)
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writel(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
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/*
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* Set priority on all interrupts.
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*/
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for (i = 0; i < max_irq; i += 4)
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writel(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
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/*
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* Disable all interrupts.
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*/
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for (i = 0; i < max_irq; i += 32)
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writel(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
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/*
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* Setup the Linux IRQ subsystem.
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*/
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for (i = 29; i < max_irq; i++) {
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set_irq_chip(i, &gic_chip);
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set_irq_handler(i, do_level_IRQ);
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set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
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}
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writel(1, base + GIC_DIST_CTRL);
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}
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void __cpuinit gic_cpu_init(void __iomem *base)
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{
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gic_cpu_base = base;
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writel(0xf0, base + GIC_CPU_PRIMASK);
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writel(1, base + GIC_CPU_CTRL);
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}
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#ifdef CONFIG_SMP
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void gic_raise_softirq(cpumask_t cpumask, unsigned int irq)
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{
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unsigned long map = *cpus_addr(cpumask);
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writel(map << 16 | irq, gic_dist_base + GIC_DIST_SOFTINT);
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}
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#endif
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@ -97,7 +97,7 @@ extern int adfs_dir_update(struct super_block *sb, struct object_info *obj);
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extern struct inode_operations adfs_file_inode_operations;
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extern struct file_operations adfs_file_operations;
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extern inline __u32 signed_asl(__u32 val, signed int shift)
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static inline __u32 signed_asl(__u32 val, signed int shift)
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{
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if (shift >= 0)
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val <<= shift;
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@ -112,7 +112,7 @@ extern inline __u32 signed_asl(__u32 val, signed int shift)
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*
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* The root directory ID should always be looked up in the map [3.4]
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*/
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extern inline int
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static inline int
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__adfs_block_map(struct super_block *sb, unsigned int object_id,
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unsigned int block)
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{
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@ -0,0 +1,41 @@
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/*
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* linux/include/asm-arm/hardware/gic.h
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*
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* Copyright (C) 2002 ARM Limited, All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARM_HARDWARE_GIC_H
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#define __ASM_ARM_HARDWARE_GIC_H
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#include <linux/compiler.h>
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#define GIC_CPU_CTRL 0x00
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#define GIC_CPU_PRIMASK 0x04
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#define GIC_CPU_BINPOINT 0x08
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#define GIC_CPU_INTACK 0x0c
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#define GIC_CPU_EOI 0x10
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#define GIC_CPU_RUNNINGPRI 0x14
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#define GIC_CPU_HIGHPRI 0x18
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#define GIC_DIST_CTRL 0x000
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#define GIC_DIST_CTR 0x004
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#define GIC_DIST_ENABLE_SET 0x100
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#define GIC_DIST_ENABLE_CLEAR 0x180
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#define GIC_DIST_PENDING_SET 0x200
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#define GIC_DIST_PENDING_CLEAR 0x280
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#define GIC_DIST_ACTIVE_BIT 0x300
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#define GIC_DIST_PRI 0x400
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#define GIC_DIST_TARGET 0x800
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#define GIC_DIST_CONFIG 0xc00
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#define GIC_DIST_SOFTINT 0xf00
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#ifndef __ASSEMBLY__
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void gic_dist_init(void __iomem *base);
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void gic_cpu_init(void __iomem *base);
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void gic_raise_softirq(cpumask_t cpumask, unsigned int irq);
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#endif
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#endif
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