Third batch of cleanup/soc for 3.20:
- several fixes and adjustments following the last cleanup batch - removal of some unused Kconfig options - slight PM and pm_idle rework to ease future rework - removal of unneeded mach/system_rev.h -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQEcBAABAgAGBQJUxjj9AAoJEAf03oE53VmQGEAH/3nLneCOQeyuq60adx+Lxcdn Q9sMMzrw4B6bQnJee7+PQD3/QU7fmF8qNKlMKYAlILFHGNQplASi4uAfRTykUA0j RQHpS9n20ODVfX+yePJ/o8h2r1BkT2wUIDXxaZCj2RoPmEz1aiFDNa2pPsUfprRd gpbh+ZU43LRowYwH9UHPV55PQ0ZwMq3ry2DOYY5Al1+bKQ8TFvAdDMUu3rGZU7A4 dMYiQCQ6Fv0EI1NY0IHSf/u/jujlPE2H0TSR38w8lYfIPzBx2tHkLSupuxKh7R1N QYibgZXWR0PqHOXMpOHYBqJFj5c3f/aOZ/dO4RJha+S7YHNQnIFzLsm122njgKQ= =KgUm -----END PGP SIGNATURE----- Merge tag 'at91-cleanup3' into at91-3.20-soc
This commit is contained in:
commit
980657d8cd
|
@ -0,0 +1,124 @@
|
|||
ARM Atmel SoCs (aka AT91)
|
||||
=========================
|
||||
|
||||
|
||||
Introduction
|
||||
------------
|
||||
This document gives useful information about the ARM Atmel SoCs that are
|
||||
currently supported in Linux Mainline (you know, the one on kernel.org).
|
||||
|
||||
It is important to note that the Atmel | SMART ARM-based MPU product line is
|
||||
historically named "AT91" or "at91" throughout the Linux kernel development
|
||||
process even if this product prefix has completely disappeared from the
|
||||
official Atmel product name. Anyway, files, directories, git trees,
|
||||
git branches/tags and email subject always contain this "at91" sub-string.
|
||||
|
||||
|
||||
AT91 SoCs
|
||||
---------
|
||||
Documentation and detailled datasheet for each product are available on
|
||||
the Atmel website: http://www.atmel.com.
|
||||
|
||||
Flavors:
|
||||
* ARM 920 based SoC
|
||||
- at91rm9200
|
||||
+ Datasheet
|
||||
http://www.atmel.com/Images/doc1768.pdf
|
||||
|
||||
* ARM 926 based SoCs
|
||||
- at91sam9260
|
||||
+ Datasheet
|
||||
http://www.atmel.com/Images/doc6221.pdf
|
||||
|
||||
- at91sam9xe
|
||||
+ Datasheet
|
||||
http://www.atmel.com/Images/Atmel-6254-32-bit-ARM926EJ-S-Embedded-Microprocessor-SAM9XE_Datasheet.pdf
|
||||
|
||||
- at91sam9261
|
||||
+ Datasheet
|
||||
http://www.atmel.com/Images/doc6062.pdf
|
||||
|
||||
- at91sam9263
|
||||
+ Datasheet
|
||||
http://www.atmel.com/Images/Atmel_6249_32-bit-ARM926EJ-S-Microcontroller_SAM9263_Datasheet.pdf
|
||||
|
||||
- at91sam9rl
|
||||
+ Datasheet
|
||||
http://www.atmel.com/Images/doc6289.pdf
|
||||
|
||||
- at91sam9g20
|
||||
+ Datasheet
|
||||
http://www.atmel.com/Images/doc6384.pdf
|
||||
|
||||
- at91sam9g45 family
|
||||
- at91sam9g45
|
||||
- at91sam9g46
|
||||
- at91sam9m10
|
||||
- at91sam9m11 (device superset)
|
||||
+ Datasheet
|
||||
http://www.atmel.com/Images/Atmel-6437-32-bit-ARM926-Embedded-Microprocessor-SAM9M11_Datasheet.pdf
|
||||
|
||||
- at91sam9x5 family (aka "The 5 series")
|
||||
- at91sam9g15
|
||||
- at91sam9g25
|
||||
- at91sam9g35
|
||||
- at91sam9x25
|
||||
- at91sam9x35
|
||||
+ Datasheet (can be considered as covering the whole family)
|
||||
http://www.atmel.com/Images/Atmel_11055_32-bit-ARM926EJ-S-Microcontroller_SAM9X35_Datasheet.pdf
|
||||
|
||||
- at91sam9n12
|
||||
+ Datasheet
|
||||
http://www.atmel.com/Images/Atmel_11063_32-bit-ARM926EJ-S-Microcontroller_SAM9N12CN11CN12_Datasheet.pdf
|
||||
|
||||
* ARM Cortex-A5 based SoCs
|
||||
- sama5d3 family
|
||||
- sama5d31
|
||||
- sama5d33
|
||||
- sama5d34
|
||||
- sama5d35
|
||||
- sama5d36 (device superset)
|
||||
+ Datasheet
|
||||
http://www.atmel.com/Images/Atmel-11121-32-bit-Cortex-A5-Microcontroller-SAMA5D3_Datasheet.pdf
|
||||
|
||||
* ARM Cortex-A5 + NEON based SoCs
|
||||
- sama5d4 family
|
||||
- sama5d41
|
||||
- sama5d42
|
||||
- sama5d43
|
||||
- sama5d44 (device superset)
|
||||
+ Datasheet
|
||||
http://www.atmel.com/Images/Atmel-11238-32-bit-Cortex-A5-Microcontroller-SAMA5D4_Datasheet.pdf
|
||||
|
||||
|
||||
Linux kernel information
|
||||
------------------------
|
||||
Linux kernel mach directory: arch/arm/mach-at91
|
||||
MAINTAINERS entry is: "ARM/ATMEL AT91RM9200 AND AT91SAM ARM ARCHITECTURES"
|
||||
|
||||
|
||||
Device Tree for AT91 SoCs and boards
|
||||
------------------------------------
|
||||
All AT91 SoCs are converted to Device Tree. Since Linux 3.19, these products
|
||||
must use this method to boot the Linux kernel.
|
||||
|
||||
Work In Progress statement:
|
||||
Device Tree files and Device Tree bindings that apply to AT91 SoCs and boards are
|
||||
considered as "Unstable". To be completely clear, any at91 binding can change at
|
||||
any time. So, be sure to use a Device Tree Binary and a Kernel Image generated from
|
||||
the same source tree.
|
||||
Please refer to the Documentation/devicetree/bindings/ABI.txt file for a
|
||||
definition of a "Stable" binding/ABI.
|
||||
This statement will be removed by AT91 MAINTAINERS when appropriate.
|
||||
|
||||
Naming conventions and best practice:
|
||||
- SoCs Device Tree Source Include files are named after the official name of
|
||||
the product (at91sam9g20.dtsi or sama5d33.dtsi for instance).
|
||||
- Device Tree Source Include files (.dtsi) are used to collect common nodes that can be
|
||||
shared across SoCs or boards (sama5d3.dtsi or at91sam9x5cm.dtsi for instance).
|
||||
When collecting nodes for a particular peripheral or topic, the identifier have to
|
||||
be placed at the end of the file name, separated with a "_" (at91sam9x5_can.dtsi
|
||||
or sama5d3_gmac.dtsi for example).
|
||||
- board Device Tree Source files (.dts) are prefixed by the string "at91-" so
|
||||
that they can be identified easily. Note that some files are historical exceptions
|
||||
to this rule (sama5d3[13456]ek.dts, usb_a9g20.dts or animeo_ip.dts for example).
|
|
@ -24,6 +24,7 @@ compatible: must be one of:
|
|||
o "atmel,at91sam9g45"
|
||||
o "atmel,at91sam9n12"
|
||||
o "atmel,at91sam9rl"
|
||||
o "atmel,at91sam9xe"
|
||||
* "atmel,sama5" for SoCs using a Cortex-A5, shall be extended with the specific
|
||||
SoC family:
|
||||
o "atmel,sama5d3" shall be extended with the specific SoC compatible:
|
||||
|
@ -136,3 +137,19 @@ Example:
|
|||
compatible = "atmel,at91sam9260-rstc";
|
||||
reg = <0xfffffd00 0x10>;
|
||||
};
|
||||
|
||||
Special Function Registers (SFR)
|
||||
|
||||
Special Function Registers (SFR) manage specific aspects of the integrated
|
||||
memory, bridge implementations, processor and other functionality not controlled
|
||||
elsewhere.
|
||||
|
||||
required properties:
|
||||
- compatible: Should be "atmel,<chip>-sfr", "syscon".
|
||||
<chip> can be "sama5d3" or "sama5d4".
|
||||
- reg: Should contain registers location and length
|
||||
|
||||
sfr@f0038000 {
|
||||
compatible = "atmel,sama5d3-sfr", "syscon";
|
||||
reg = <0xf0038000 0x60>;
|
||||
};
|
||||
|
|
|
@ -877,6 +877,7 @@ F: arch/arm/boot/dts/at91*.dts
|
|||
F: arch/arm/boot/dts/at91*.dtsi
|
||||
F: arch/arm/boot/dts/sama*.dts
|
||||
F: arch/arm/boot/dts/sama*.dtsi
|
||||
F: arch/arm/include/debug/at91.S
|
||||
|
||||
ARM/ATMEL AT91 Clock Support
|
||||
M: Boris Brezillon <boris.brezillon@free-electrons.com>
|
||||
|
|
|
@ -115,16 +115,22 @@ choice
|
|||
0x80024000 | 0xf0024000 | UART9
|
||||
|
||||
config AT91_DEBUG_LL_DBGU0
|
||||
bool "Kernel low-level debugging on rm9200, 9260/9g20, 9261/9g10 and 9rl"
|
||||
depends on HAVE_AT91_DBGU0
|
||||
bool "Kernel low-level debugging on rm9200, 9260/9g20, 9261/9g10, 9rl, 9x5, 9n12"
|
||||
select DEBUG_AT91_UART
|
||||
depends on ARCH_AT91
|
||||
depends on SOC_AT91RM9200 || SOC_AT91SAM9
|
||||
|
||||
config AT91_DEBUG_LL_DBGU1
|
||||
bool "Kernel low-level debugging on 9263 and 9g45"
|
||||
depends on HAVE_AT91_DBGU1
|
||||
bool "Kernel low-level debugging on 9263, 9g45 and sama5d3"
|
||||
select DEBUG_AT91_UART
|
||||
depends on ARCH_AT91
|
||||
depends on SOC_AT91SAM9 || SOC_SAMA5
|
||||
|
||||
config AT91_DEBUG_LL_DBGU2
|
||||
bool "Kernel low-level debugging on sama5d4"
|
||||
depends on HAVE_AT91_DBGU2
|
||||
select DEBUG_AT91_UART
|
||||
depends on ARCH_AT91
|
||||
depends on SOC_SAMA5
|
||||
|
||||
config DEBUG_BCM2835
|
||||
bool "Kernel low-level debugging on BCM2835 PL011 UART"
|
||||
|
@ -1109,6 +1115,10 @@ choice
|
|||
|
||||
endchoice
|
||||
|
||||
config DEBUG_AT91_UART
|
||||
bool
|
||||
depends on ARCH_AT91
|
||||
|
||||
config DEBUG_EXYNOS_UART
|
||||
bool
|
||||
|
||||
|
@ -1165,6 +1175,7 @@ config DEBUG_LL_INCLUDE
|
|||
string
|
||||
default "debug/sa1100.S" if DEBUG_SA1100
|
||||
default "debug/8250.S" if DEBUG_LL_UART_8250 || DEBUG_UART_8250
|
||||
default "debug/at91.S" if DEBUG_AT91_UART
|
||||
default "debug/asm9260.S" if DEBUG_ASM9260_UART
|
||||
default "debug/clps711x.S" if DEBUG_CLPS711X_UART1 || DEBUG_CLPS711X_UART2
|
||||
default "debug/meson.S" if DEBUG_MESON_UARTAO
|
||||
|
|
|
@ -66,6 +66,11 @@
|
|||
};
|
||||
};
|
||||
|
||||
sram: sram@00200000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x00200000 0x4000>;
|
||||
};
|
||||
|
||||
ahb {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
|
@ -356,6 +361,13 @@
|
|||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
};
|
||||
|
||||
rtc: rtc@fffffe00 {
|
||||
compatible = "atmel,at91rm9200-rtc";
|
||||
reg = <0xfffffe00 0x40>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tcb0: timer@fffa0000 {
|
||||
compatible = "atmel,at91rm9200-tcb";
|
||||
reg = <0xfffa0000 0x100>;
|
||||
|
|
|
@ -77,6 +77,10 @@
|
|||
dbgu: serial@fffff200 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
rtc: rtc@fffffe00 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
usb0: ohci@00300000 {
|
||||
|
|
|
@ -69,6 +69,11 @@
|
|||
};
|
||||
};
|
||||
|
||||
sram0: sram@002ff000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x002ff000 0x2000>;
|
||||
};
|
||||
|
||||
ahb {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
|
|
|
@ -60,6 +60,11 @@
|
|||
};
|
||||
};
|
||||
|
||||
sram: sram@00300000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x00300000 0x28000>;
|
||||
};
|
||||
|
||||
ahb {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
|
|
|
@ -62,6 +62,16 @@
|
|||
};
|
||||
};
|
||||
|
||||
sram0: sram@00300000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x00300000 0x14000>;
|
||||
};
|
||||
|
||||
sram1: sram@00500000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x00300000 0x4000>;
|
||||
};
|
||||
|
||||
ahb {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
|
@ -294,7 +304,7 @@
|
|||
reg = <17>;
|
||||
};
|
||||
|
||||
ac91_clk: ac97_clk {
|
||||
ac97_clk: ac97_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <18>;
|
||||
};
|
||||
|
|
|
@ -16,6 +16,15 @@
|
|||
reg = <0x20000000 0x08000000>;
|
||||
};
|
||||
|
||||
sram0: sram@002ff000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sram1: sram@002fc000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x002fc000 0x8000>;
|
||||
};
|
||||
|
||||
ahb {
|
||||
apb {
|
||||
i2c0: i2c@fffac000 {
|
||||
|
|
|
@ -74,6 +74,11 @@
|
|||
};
|
||||
};
|
||||
|
||||
sram: sram@00300000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x00300000 0x10000>;
|
||||
};
|
||||
|
||||
ahb {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
|
@ -1287,7 +1292,6 @@
|
|||
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
|
||||
reg = <0x00700000 0x100000>;
|
||||
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
|
||||
//TODO
|
||||
clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
|
||||
clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
|
||||
status = "disabled";
|
||||
|
@ -1297,7 +1301,6 @@
|
|||
compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
|
||||
reg = <0x00800000 0x100000>;
|
||||
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
|
||||
//TODO
|
||||
clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
|
||||
clock-names = "usb_clk", "ehci_clk", "hclk", "uhpck";
|
||||
status = "disabled";
|
||||
|
|
|
@ -64,6 +64,11 @@
|
|||
};
|
||||
};
|
||||
|
||||
sram: sram@00300000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x00300000 0x8000>;
|
||||
};
|
||||
|
||||
ahb {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
|
@ -893,6 +898,13 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
rtc@fffffeb0 {
|
||||
compatible = "atmel,at91rm9200-rtc";
|
||||
reg = <0xfffffeb0 0x40>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm0: pwm@f8034000 {
|
||||
compatible = "atmel,at91sam9rl-pwm";
|
||||
reg = <0xf8034000 0x300>;
|
||||
|
|
|
@ -70,6 +70,11 @@
|
|||
};
|
||||
};
|
||||
|
||||
sram: sram@00300000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x00300000 0x10000>;
|
||||
};
|
||||
|
||||
ahb {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
|
|
|
@ -72,6 +72,11 @@
|
|||
};
|
||||
};
|
||||
|
||||
sram: sram@00300000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x00300000 0x8000>;
|
||||
};
|
||||
|
||||
ahb {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
|
|
|
@ -0,0 +1,60 @@
|
|||
/*
|
||||
* at91sam9xe.dtsi - Device Tree Include file for AT91SAM9XE family SoC
|
||||
*
|
||||
* Copyright (C) 2015 Atmel,
|
||||
* 2015 Alexandre Belloni <alexandre.Belloni@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "at91sam9260.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Atmel AT91SAM9XE family SoC";
|
||||
compatible = "atmel,at91sam9xe", "atmel,at91sam9260";
|
||||
|
||||
sram0: sram@002ff000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sram1: sram@00300000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x00300000 0x4000>;
|
||||
};
|
||||
};
|
|
@ -6,7 +6,7 @@
|
|||
* Licensed under GPLv2.
|
||||
*/
|
||||
/dts-v1/;
|
||||
#include "at91sam9260.dtsi"
|
||||
#include "at91sam9xe.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Ethernut 5";
|
||||
|
|
|
@ -78,6 +78,11 @@
|
|||
};
|
||||
};
|
||||
|
||||
sram: sram@00300000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x00300000 0x20000>;
|
||||
};
|
||||
|
||||
ahb {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
|
@ -214,7 +219,20 @@
|
|||
compatible = "atmel,at91sam9g45-isi";
|
||||
reg = <0xf0034000 0x4000>;
|
||||
interrupts = <37 IRQ_TYPE_LEVEL_HIGH 5>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_isi_data_0_7>;
|
||||
clocks = <&isi_clk>;
|
||||
clock-names = "isi_clk";
|
||||
status = "disabled";
|
||||
port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
sfr: sfr@f0038000 {
|
||||
compatible = "atmel,sama5d3-sfr", "syscon";
|
||||
reg = <0xf0038000 0x60>;
|
||||
};
|
||||
|
||||
mmc1: mmc@f8000000 {
|
||||
|
@ -545,7 +563,7 @@
|
|||
};
|
||||
|
||||
isi {
|
||||
pinctrl_isi: isi-0 {
|
||||
pinctrl_isi_data_0_7: isi-0-data-0-7 {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 16 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */
|
||||
AT91_PIOA 17 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */
|
||||
|
@ -557,13 +575,19 @@
|
|||
AT91_PIOA 23 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */
|
||||
AT91_PIOC 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC30 periph C ISI_PCK, conflicts with UTXD0 */
|
||||
AT91_PIOA 31 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */
|
||||
AT91_PIOA 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */
|
||||
AT91_PIOC 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */
|
||||
AT91_PIOA 30 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */
|
||||
};
|
||||
|
||||
pinctrl_isi_data_8_9: isi-0-data-8-9 {
|
||||
atmel,pins =
|
||||
<AT91_PIOC 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */
|
||||
AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */
|
||||
};
|
||||
pinctrl_isi_pck_as_mck: isi_pck_as_mck-0 {
|
||||
|
||||
pinctrl_isi_data_10_11: isi-0-data-10-11 {
|
||||
atmel,pins =
|
||||
<AT91_PIOD 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD31 periph B ISI_MCK */
|
||||
<AT91_PIOC 27 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC27 periph C ISI_PD10, conflicts with SPI1_NPCS2, TWCK1 */
|
||||
AT91_PIOC 26 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC26 periph C ISI_PD11, conflicts with SPI1_NPCS1, TWD1 */
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
@ -122,6 +122,7 @@
|
|||
d2 {
|
||||
label = "d2";
|
||||
gpios = <&pioE 25 GPIO_ACTIVE_LOW>; /* PE25, conflicts with A25, RXD2 */
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
@ -52,6 +52,29 @@
|
|||
};
|
||||
};
|
||||
|
||||
i2c1: i2c@f0018000 {
|
||||
ov2640: camera@0x30 {
|
||||
compatible = "ovti,ov2640";
|
||||
reg = <0x30>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pck1_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>;
|
||||
resetb-gpios = <&pioE 24 GPIO_ACTIVE_LOW>;
|
||||
pwdn-gpios = <&pioE 29 GPIO_ACTIVE_HIGH>;
|
||||
/* use pck1 for the master clock of ov2640 */
|
||||
clocks = <&pck1>;
|
||||
clock-names = "xvclk";
|
||||
assigned-clocks = <&pck1>;
|
||||
assigned-clock-rates = <25000000>;
|
||||
|
||||
port {
|
||||
ov2640_0: endpoint {
|
||||
remote-endpoint = <&isi_0>;
|
||||
bus-width = <8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
usart1: serial@f0020000 {
|
||||
dmas = <0>, <0>; /* Do not use DMA for usart1 */
|
||||
pinctrl-names = "default";
|
||||
|
@ -60,8 +83,12 @@
|
|||
};
|
||||
|
||||
isi: isi@f0034000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_isi &pinctrl_isi_pck_as_mck &pinctrl_isi_power &pinctrl_isi_reset>;
|
||||
port {
|
||||
isi_0: endpoint {
|
||||
remote-endpoint = <&ov2640_0>;
|
||||
bus-width = <8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mmc1: mmc@f8000000 {
|
||||
|
@ -117,12 +144,17 @@
|
|||
<AT91_PIOD 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD30 periph B */
|
||||
};
|
||||
|
||||
pinctrl_isi_reset: isi_reset-0 {
|
||||
pinctrl_pck1_as_isi_mck: pck1_as_isi_mck-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOD 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD31 periph B ISI_MCK */
|
||||
};
|
||||
|
||||
pinctrl_sensor_reset: sensor_reset-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOE 24 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; /* PE24 gpio */
|
||||
};
|
||||
|
||||
pinctrl_isi_power: isi_power-0 {
|
||||
pinctrl_sensor_power: sensor_power-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOE 29 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; /* PE29 gpio */
|
||||
};
|
||||
|
|
|
@ -103,6 +103,11 @@
|
|||
};
|
||||
};
|
||||
|
||||
ns_sram: sram@00210000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x00210000 0x10000>;
|
||||
};
|
||||
|
||||
ahb {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
|
@ -870,6 +875,11 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
sfr: sfr@f8028000 {
|
||||
compatible = "atmel,sama5d4-sfr", "syscon";
|
||||
reg = <0xf8028000 0x60>;
|
||||
};
|
||||
|
||||
mmc1: mmc@fc000000 {
|
||||
compatible = "atmel,hsmci";
|
||||
reg = <0xfc000000 0x600>;
|
||||
|
|
|
@ -1,6 +1,4 @@
|
|||
/*
|
||||
* arch/arm/mach-at91/include/mach/debug-macro.S
|
||||
*
|
||||
* Copyright (C) 2003-2005 SAN People
|
||||
*
|
||||
* Debugging macro include header
|
||||
|
@ -11,18 +9,23 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/at91_dbgu.h>
|
||||
|
||||
#if defined(CONFIG_AT91_DEBUG_LL_DBGU0)
|
||||
#define AT91_DBGU AT91_BASE_DBGU0
|
||||
#define AT91_DBGU 0xfffff200 /* AT91_BASE_DBGU0 */
|
||||
#elif defined(CONFIG_AT91_DEBUG_LL_DBGU1)
|
||||
#define AT91_DBGU AT91_BASE_DBGU1
|
||||
#define AT91_DBGU 0xffffee00 /* AT91_BASE_DBGU1 */
|
||||
#else
|
||||
/* On sama5d4, use USART3 as low level serial console */
|
||||
#define AT91_DBGU SAMA5D4_BASE_USART3
|
||||
#define AT91_DBGU 0xfc00c000 /* SAMA5D4_BASE_USART3 */
|
||||
#endif
|
||||
|
||||
/* Keep in sync with mach-at91/include/mach/hardware.h */
|
||||
#define AT91_IO_P2V(x) ((x) - 0x01000000)
|
||||
|
||||
#define AT91_DBGU_SR (0x14) /* Status Register */
|
||||
#define AT91_DBGU_THR (0x1c) /* Transmitter Holding Register */
|
||||
#define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */
|
||||
#define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */
|
||||
|
||||
.macro addruart, rp, rv, tmp
|
||||
ldr \rp, =AT91_DBGU @ System peripherals (phys address)
|
||||
ldr \rv, =AT91_IO_P2V(AT91_DBGU) @ System peripherals (virt address)
|
|
@ -6,15 +6,6 @@ config HAVE_AT91_UTMI
|
|||
config HAVE_AT91_USB_CLK
|
||||
bool
|
||||
|
||||
config HAVE_AT91_DBGU0
|
||||
bool
|
||||
|
||||
config HAVE_AT91_DBGU1
|
||||
bool
|
||||
|
||||
config HAVE_AT91_DBGU2
|
||||
bool
|
||||
|
||||
config COMMON_CLK_AT91
|
||||
bool
|
||||
select COMMON_CLK
|
||||
|
@ -70,7 +61,6 @@ config SOC_SAMA5D3
|
|||
bool "SAMA5D3 family"
|
||||
select SOC_SAMA5
|
||||
select HAVE_FB_ATMEL
|
||||
select HAVE_AT91_DBGU1
|
||||
select HAVE_AT91_UTMI
|
||||
select HAVE_AT91_SMD
|
||||
select HAVE_AT91_USB_CLK
|
||||
|
@ -81,7 +71,6 @@ config SOC_SAMA5D3
|
|||
config SOC_SAMA5D4
|
||||
bool "SAMA5D4 family"
|
||||
select SOC_SAMA5
|
||||
select HAVE_AT91_DBGU2
|
||||
select CLKSRC_MMIO
|
||||
select CACHE_L2X0
|
||||
select CACHE_PL310
|
||||
|
@ -101,12 +90,10 @@ config SOC_AT91RM9200
|
|||
select COMMON_CLK_AT91
|
||||
select CPU_ARM920T
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select HAVE_AT91_DBGU0
|
||||
select HAVE_AT91_USB_CLK
|
||||
|
||||
config SOC_AT91SAM9260
|
||||
bool "AT91SAM9260, AT91SAM9XE or AT91SAM9G20"
|
||||
select HAVE_AT91_DBGU0
|
||||
select SOC_AT91SAM9
|
||||
select HAVE_AT91_USB_CLK
|
||||
help
|
||||
|
@ -115,7 +102,6 @@ config SOC_AT91SAM9260
|
|||
|
||||
config SOC_AT91SAM9261
|
||||
bool "AT91SAM9261 or AT91SAM9G10"
|
||||
select HAVE_AT91_DBGU0
|
||||
select HAVE_FB_ATMEL
|
||||
select SOC_AT91SAM9
|
||||
select HAVE_AT91_USB_CLK
|
||||
|
@ -124,21 +110,18 @@ config SOC_AT91SAM9261
|
|||
|
||||
config SOC_AT91SAM9263
|
||||
bool "AT91SAM9263"
|
||||
select HAVE_AT91_DBGU1
|
||||
select HAVE_FB_ATMEL
|
||||
select SOC_AT91SAM9
|
||||
select HAVE_AT91_USB_CLK
|
||||
|
||||
config SOC_AT91SAM9RL
|
||||
bool "AT91SAM9RL"
|
||||
select HAVE_AT91_DBGU0
|
||||
select HAVE_FB_ATMEL
|
||||
select SOC_AT91SAM9
|
||||
select HAVE_AT91_UTMI
|
||||
|
||||
config SOC_AT91SAM9G45
|
||||
bool "AT91SAM9G45 or AT91SAM9M10 families"
|
||||
select HAVE_AT91_DBGU1
|
||||
select HAVE_FB_ATMEL
|
||||
select SOC_AT91SAM9
|
||||
select HAVE_AT91_UTMI
|
||||
|
@ -149,7 +132,6 @@ config SOC_AT91SAM9G45
|
|||
|
||||
config SOC_AT91SAM9X5
|
||||
bool "AT91SAM9x5 family"
|
||||
select HAVE_AT91_DBGU0
|
||||
select HAVE_FB_ATMEL
|
||||
select SOC_AT91SAM9
|
||||
select HAVE_AT91_UTMI
|
||||
|
@ -164,7 +146,6 @@ config SOC_AT91SAM9X5
|
|||
|
||||
config SOC_AT91SAM9N12
|
||||
bool "AT91SAM9N12 family"
|
||||
select HAVE_AT91_DBGU0
|
||||
select HAVE_FB_ATMEL
|
||||
select SOC_AT91SAM9
|
||||
select HAVE_AT91_USB_CLK
|
||||
|
@ -174,18 +155,11 @@ config SOC_AT91SAM9N12
|
|||
# ----------------------------------------------------------
|
||||
endif # SOC_SAM_V4_V5
|
||||
|
||||
config MACH_AT91RM9200_DT
|
||||
def_bool SOC_AT91RM9200
|
||||
|
||||
config MACH_AT91SAM9_DT
|
||||
def_bool SOC_AT91SAM9
|
||||
|
||||
# ----------------------------------------------------------
|
||||
|
||||
comment "AT91 Feature Selections"
|
||||
|
||||
config AT91_SLOW_CLOCK
|
||||
bool "Suspend-to-RAM disables main oscillator"
|
||||
select SRAM
|
||||
depends on SUSPEND
|
||||
help
|
||||
Select this if you want Suspend-to-RAM to save the most power
|
||||
|
|
|
@ -2,7 +2,7 @@
|
|||
# Makefile for the linux kernel.
|
||||
#
|
||||
|
||||
obj-y := setup.o sysirq_mask.o
|
||||
obj-y := setup.o
|
||||
|
||||
obj-$(CONFIG_SOC_AT91SAM9) += sam9_smc.o
|
||||
|
||||
|
@ -19,8 +19,8 @@ obj-$(CONFIG_SOC_SAMA5D3) += sama5d3.o
|
|||
obj-$(CONFIG_SOC_SAMA5D4) += sama5d4.o
|
||||
|
||||
# AT91SAM board with device-tree
|
||||
obj-$(CONFIG_MACH_AT91RM9200_DT) += board-dt-rm9200.o
|
||||
obj-$(CONFIG_MACH_AT91SAM9_DT) += board-dt-sam9.o
|
||||
obj-$(CONFIG_SOC_AT91RM9200) += board-dt-rm9200.o
|
||||
obj-$(CONFIG_SOC_AT91SAM9) += board-dt-sam9.o
|
||||
|
||||
# SAMA5 board with device-tree
|
||||
obj-$(CONFIG_SOC_SAMA5) += board-dt-sama5.o
|
||||
|
|
|
@ -21,14 +21,6 @@
|
|||
#include "soc.h"
|
||||
#include "generic.h"
|
||||
|
||||
static void at91rm9200_idle(void)
|
||||
{
|
||||
/*
|
||||
* Disable the processor clock. The processor will be automatically
|
||||
* re-enabled by an interrupt or by a reset.
|
||||
*/
|
||||
at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
|
||||
}
|
||||
|
||||
static void at91rm9200_restart(enum reboot_mode reboot_mode, const char *cmd)
|
||||
{
|
||||
|
@ -42,11 +34,6 @@ static void at91rm9200_restart(enum reboot_mode reboot_mode, const char *cmd)
|
|||
/* --------------------------------------------------------------------
|
||||
* AT91RM9200 processor initialization
|
||||
* -------------------------------------------------------------------- */
|
||||
static void __init at91rm9200_map_io(void)
|
||||
{
|
||||
/* Map peripherals */
|
||||
at91_init_sram(0, AT91RM9200_SRAM_BASE, AT91RM9200_SRAM_SIZE);
|
||||
}
|
||||
|
||||
static void __init at91rm9200_initialize(void)
|
||||
{
|
||||
|
@ -54,8 +41,6 @@ static void __init at91rm9200_initialize(void)
|
|||
arm_pm_restart = at91rm9200_restart;
|
||||
}
|
||||
|
||||
|
||||
AT91_SOC_START(at91rm9200)
|
||||
.map_io = at91rm9200_map_io,
|
||||
.init = at91rm9200_initialize,
|
||||
AT91_SOC_END
|
||||
|
|
|
@ -22,40 +22,5 @@
|
|||
* AT91SAM9260 processor initialization
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
static void __init at91sam9xe_map_io(void)
|
||||
{
|
||||
unsigned long sram_size;
|
||||
|
||||
switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
|
||||
case AT91_CIDR_SRAMSIZ_32K:
|
||||
sram_size = 2 * SZ_16K;
|
||||
break;
|
||||
case AT91_CIDR_SRAMSIZ_16K:
|
||||
default:
|
||||
sram_size = SZ_16K;
|
||||
}
|
||||
|
||||
at91_init_sram(0, AT91SAM9XE_SRAM_BASE, sram_size);
|
||||
}
|
||||
|
||||
static void __init at91sam9260_map_io(void)
|
||||
{
|
||||
if (cpu_is_at91sam9xe())
|
||||
at91sam9xe_map_io();
|
||||
else if (cpu_is_at91sam9g20())
|
||||
at91_init_sram(0, AT91SAM9G20_SRAM_BASE, AT91SAM9G20_SRAM_SIZE);
|
||||
else
|
||||
at91_init_sram(0, AT91SAM9260_SRAM_BASE, AT91SAM9260_SRAM_SIZE);
|
||||
}
|
||||
|
||||
static void __init at91sam9260_initialize(void)
|
||||
{
|
||||
arm_pm_idle = at91sam9_idle;
|
||||
|
||||
at91_sysirq_mask_rtt(AT91SAM9260_BASE_RTT);
|
||||
}
|
||||
|
||||
AT91_SOC_START(at91sam9260)
|
||||
.map_io = at91sam9260_map_io,
|
||||
.init = at91sam9260_initialize,
|
||||
AT91_SOC_END
|
||||
|
|
|
@ -21,22 +21,5 @@
|
|||
* AT91SAM9261 processor initialization
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
static void __init at91sam9261_map_io(void)
|
||||
{
|
||||
if (cpu_is_at91sam9g10())
|
||||
at91_init_sram(0, AT91SAM9G10_SRAM_BASE, AT91SAM9G10_SRAM_SIZE);
|
||||
else
|
||||
at91_init_sram(0, AT91SAM9261_SRAM_BASE, AT91SAM9261_SRAM_SIZE);
|
||||
}
|
||||
|
||||
static void __init at91sam9261_initialize(void)
|
||||
{
|
||||
arm_pm_idle = at91sam9_idle;
|
||||
|
||||
at91_sysirq_mask_rtt(AT91SAM9261_BASE_RTT);
|
||||
}
|
||||
|
||||
AT91_SOC_START(at91sam9261)
|
||||
.map_io = at91sam9261_map_io,
|
||||
.init = at91sam9261_initialize,
|
||||
AT91_SOC_END
|
||||
|
|
|
@ -20,21 +20,5 @@
|
|||
* AT91SAM9263 processor initialization
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
static void __init at91sam9263_map_io(void)
|
||||
{
|
||||
at91_init_sram(0, AT91SAM9263_SRAM0_BASE, AT91SAM9263_SRAM0_SIZE);
|
||||
at91_init_sram(1, AT91SAM9263_SRAM1_BASE, AT91SAM9263_SRAM1_SIZE);
|
||||
}
|
||||
|
||||
static void __init at91sam9263_initialize(void)
|
||||
{
|
||||
arm_pm_idle = at91sam9_idle;
|
||||
|
||||
at91_sysirq_mask_rtt(AT91SAM9263_BASE_RTT0);
|
||||
at91_sysirq_mask_rtt(AT91SAM9263_BASE_RTT1);
|
||||
}
|
||||
|
||||
AT91_SOC_START(at91sam9263)
|
||||
.map_io = at91sam9263_map_io,
|
||||
.init = at91sam9263_initialize,
|
||||
AT91_SOC_END
|
||||
|
|
|
@ -11,7 +11,6 @@
|
|||
*/
|
||||
|
||||
#include <asm/system_misc.h>
|
||||
#include <asm/irq.h>
|
||||
#include <mach/hardware.h>
|
||||
|
||||
#include "soc.h"
|
||||
|
@ -21,20 +20,5 @@
|
|||
* AT91SAM9G45 processor initialization
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
static void __init at91sam9g45_map_io(void)
|
||||
{
|
||||
at91_init_sram(0, AT91SAM9G45_SRAM_BASE, AT91SAM9G45_SRAM_SIZE);
|
||||
}
|
||||
|
||||
static void __init at91sam9g45_initialize(void)
|
||||
{
|
||||
arm_pm_idle = at91sam9_idle;
|
||||
|
||||
at91_sysirq_mask_rtc(AT91SAM9G45_BASE_RTC);
|
||||
at91_sysirq_mask_rtt(AT91SAM9G45_BASE_RTT);
|
||||
}
|
||||
|
||||
AT91_SOC_START(at91sam9g45)
|
||||
.map_io = at91sam9g45_map_io,
|
||||
.init = at91sam9g45_initialize,
|
||||
AT91_SOC_END
|
||||
|
|
|
@ -16,17 +16,5 @@
|
|||
* AT91SAM9N12 processor initialization
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
static void __init at91sam9n12_map_io(void)
|
||||
{
|
||||
at91_init_sram(0, AT91SAM9N12_SRAM_BASE, AT91SAM9N12_SRAM_SIZE);
|
||||
}
|
||||
|
||||
static void __init at91sam9n12_initialize(void)
|
||||
{
|
||||
at91_sysirq_mask_rtc(AT91SAM9N12_BASE_RTC);
|
||||
}
|
||||
|
||||
AT91_SOC_START(at91sam9n12)
|
||||
.map_io = at91sam9n12_map_io,
|
||||
.init = at91sam9n12_initialize,
|
||||
AT91_SOC_END
|
||||
|
|
|
@ -10,7 +10,6 @@
|
|||
*/
|
||||
|
||||
#include <asm/system_misc.h>
|
||||
#include <asm/irq.h>
|
||||
#include <mach/cpu.h>
|
||||
#include <mach/at91_dbgu.h>
|
||||
#include <mach/hardware.h>
|
||||
|
@ -22,32 +21,5 @@
|
|||
* AT91SAM9RL processor initialization
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
static void __init at91sam9rl_map_io(void)
|
||||
{
|
||||
unsigned long sram_size;
|
||||
|
||||
switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
|
||||
case AT91_CIDR_SRAMSIZ_32K:
|
||||
sram_size = 2 * SZ_16K;
|
||||
break;
|
||||
case AT91_CIDR_SRAMSIZ_16K:
|
||||
default:
|
||||
sram_size = SZ_16K;
|
||||
}
|
||||
|
||||
/* Map SRAM */
|
||||
at91_init_sram(0, AT91SAM9RL_SRAM_BASE, sram_size);
|
||||
}
|
||||
|
||||
static void __init at91sam9rl_initialize(void)
|
||||
{
|
||||
arm_pm_idle = at91sam9_idle;
|
||||
|
||||
at91_sysirq_mask_rtc(AT91SAM9RL_BASE_RTC);
|
||||
at91_sysirq_mask_rtt(AT91SAM9RL_BASE_RTT);
|
||||
}
|
||||
|
||||
AT91_SOC_START(at91sam9rl)
|
||||
.map_io = at91sam9rl_map_io,
|
||||
.init = at91sam9rl_initialize,
|
||||
AT91_SOC_END
|
||||
|
|
|
@ -16,21 +16,5 @@
|
|||
* AT91SAM9x5 processor initialization
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
static void __init at91sam9x5_map_io(void)
|
||||
{
|
||||
at91_init_sram(0, AT91SAM9X5_SRAM_BASE, AT91SAM9X5_SRAM_SIZE);
|
||||
}
|
||||
|
||||
static void __init at91sam9x5_initialize(void)
|
||||
{
|
||||
at91_sysirq_mask_rtc(AT91SAM9X5_BASE_RTC);
|
||||
}
|
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* Interrupt initialization
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
AT91_SOC_START(at91sam9x5)
|
||||
.map_io = at91sam9x5_map_io,
|
||||
.init = at91sam9x5_initialize,
|
||||
AT91_SOC_END
|
||||
|
|
|
@ -14,6 +14,7 @@
|
|||
#include <linux/gpio.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/clk-provider.h>
|
||||
|
||||
#include <asm/setup.h>
|
||||
|
@ -30,7 +31,16 @@ static void __init at91rm9200_dt_timer_init(void)
|
|||
at91rm9200_timer_init();
|
||||
}
|
||||
|
||||
static const char *at91rm9200_dt_board_compat[] __initdata = {
|
||||
static void __init rm9200_dt_device_init(void)
|
||||
{
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
|
||||
at91_rm9200_pm_init();
|
||||
}
|
||||
|
||||
|
||||
|
||||
static const char *at91rm9200_dt_board_compat[] __initconst = {
|
||||
"atmel,at91rm9200",
|
||||
NULL
|
||||
};
|
||||
|
@ -38,6 +48,7 @@ static const char *at91rm9200_dt_board_compat[] __initdata = {
|
|||
DT_MACHINE_START(at91rm9200_dt, "Atmel AT91RM9200 (Device Tree)")
|
||||
.init_time = at91rm9200_dt_timer_init,
|
||||
.map_io = at91_map_io,
|
||||
.init_early = at91rm9200_dt_initialize,
|
||||
.init_early = at91_dt_initialize,
|
||||
.init_machine = rm9200_dt_device_init,
|
||||
.dt_compat = at91rm9200_dt_board_compat,
|
||||
MACHINE_END
|
||||
|
|
|
@ -13,8 +13,10 @@
|
|||
#include <linux/gpio.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/clk-provider.h>
|
||||
|
||||
#include <asm/system_misc.h>
|
||||
#include <asm/setup.h>
|
||||
#include <asm/irq.h>
|
||||
#include <asm/mach/arch.h>
|
||||
|
@ -23,7 +25,15 @@
|
|||
|
||||
#include "generic.h"
|
||||
|
||||
static const char *at91_dt_board_compat[] __initdata = {
|
||||
static void __init sam9_dt_device_init(void)
|
||||
{
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
|
||||
arm_pm_idle = at91sam9_idle;
|
||||
at91_sam9260_pm_init();
|
||||
}
|
||||
|
||||
static const char *at91_dt_board_compat[] __initconst = {
|
||||
"atmel,at91sam9",
|
||||
NULL
|
||||
};
|
||||
|
@ -32,5 +42,49 @@ DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM (Device Tree)")
|
|||
/* Maintainer: Atmel */
|
||||
.map_io = at91_map_io,
|
||||
.init_early = at91_dt_initialize,
|
||||
.init_machine = sam9_dt_device_init,
|
||||
.dt_compat = at91_dt_board_compat,
|
||||
MACHINE_END
|
||||
|
||||
static void __init sam9g45_dt_device_init(void)
|
||||
{
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
|
||||
arm_pm_idle = at91sam9_idle;
|
||||
at91_sam9g45_pm_init();
|
||||
}
|
||||
|
||||
static const char *at91_9g45_board_compat[] __initconst = {
|
||||
"atmel,at91sam9g45",
|
||||
NULL
|
||||
};
|
||||
|
||||
DT_MACHINE_START(at91sam9g45_dt, "Atmel AT91SAM9G45")
|
||||
/* Maintainer: Atmel */
|
||||
.map_io = at91_map_io,
|
||||
.init_early = at91_dt_initialize,
|
||||
.init_machine = sam9g45_dt_device_init,
|
||||
.dt_compat = at91_9g45_board_compat,
|
||||
MACHINE_END
|
||||
|
||||
static void __init sam9x5_dt_device_init(void)
|
||||
{
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
|
||||
arm_pm_idle = at91sam9_idle;
|
||||
at91_sam9x5_pm_init();
|
||||
}
|
||||
|
||||
static const char *at91_9x5_board_compat[] __initconst = {
|
||||
"atmel,at91sam9x5",
|
||||
"atmel,at91sam9n12",
|
||||
NULL
|
||||
};
|
||||
|
||||
DT_MACHINE_START(at91sam9x5_dt, "Atmel AT91SAM9")
|
||||
/* Maintainer: Atmel */
|
||||
.map_io = at91_map_io,
|
||||
.init_early = at91_dt_initialize,
|
||||
.init_machine = sam9x5_dt_device_init,
|
||||
.dt_compat = at91_9x5_board_compat,
|
||||
MACHINE_END
|
||||
|
|
|
@ -47,6 +47,7 @@ static void __init sama5_dt_device_init(void)
|
|||
}
|
||||
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
at91_sam9x5_pm_init();
|
||||
}
|
||||
|
||||
static const char *sama5_dt_board_compat[] __initconst = {
|
||||
|
|
|
@ -17,24 +17,31 @@
|
|||
/* Map io */
|
||||
extern void __init at91_map_io(void);
|
||||
extern void __init at91_alt_map_io(void);
|
||||
extern void __init at91_init_sram(int bank, unsigned long base,
|
||||
unsigned int length);
|
||||
|
||||
/* Processors */
|
||||
extern void __init at91rm9200_set_type(int type);
|
||||
extern void __init at91rm9200_dt_initialize(void);
|
||||
extern void __init at91_dt_initialize(void);
|
||||
|
||||
/* Interrupts */
|
||||
extern void __init at91_sysirq_mask_rtc(u32 rtc_base);
|
||||
extern void __init at91_sysirq_mask_rtt(u32 rtt_base);
|
||||
|
||||
/* Timer */
|
||||
extern void at91rm9200_timer_init(void);
|
||||
|
||||
/* idle */
|
||||
extern void at91rm9200_idle(void);
|
||||
extern void at91sam9_idle(void);
|
||||
|
||||
/* Matrix */
|
||||
extern void at91_ioremap_matrix(u32 base_addr);
|
||||
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
extern void __init at91_rm9200_pm_init(void);
|
||||
extern void __init at91_sam9260_pm_init(void);
|
||||
extern void __init at91_sam9g45_pm_init(void);
|
||||
extern void __init at91_sam9x5_pm_init(void);
|
||||
#else
|
||||
void __init at91_rm9200_pm_init(void) { }
|
||||
void __init at91_sam9260_pm_init(void) { }
|
||||
void __init at91_sam9g45_pm_init(void) { }
|
||||
void __init at91_sam9x5_pm_init(void) { }
|
||||
#endif
|
||||
|
||||
#endif /* _AT91_GENERIC_H */
|
||||
|
|
|
@ -1,80 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-at91/include/mach/at91_pio.h
|
||||
*
|
||||
* Copyright (C) 2005 Ivan Kokshaysky
|
||||
* Copyright (C) SAN People
|
||||
*
|
||||
* Parallel I/O Controller (PIO) - System peripherals registers.
|
||||
* Based on AT91RM9200 datasheet revision E.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef AT91_PIO_H
|
||||
#define AT91_PIO_H
|
||||
|
||||
#define PIO_PER 0x00 /* Enable Register */
|
||||
#define PIO_PDR 0x04 /* Disable Register */
|
||||
#define PIO_PSR 0x08 /* Status Register */
|
||||
#define PIO_OER 0x10 /* Output Enable Register */
|
||||
#define PIO_ODR 0x14 /* Output Disable Register */
|
||||
#define PIO_OSR 0x18 /* Output Status Register */
|
||||
#define PIO_IFER 0x20 /* Glitch Input Filter Enable */
|
||||
#define PIO_IFDR 0x24 /* Glitch Input Filter Disable */
|
||||
#define PIO_IFSR 0x28 /* Glitch Input Filter Status */
|
||||
#define PIO_SODR 0x30 /* Set Output Data Register */
|
||||
#define PIO_CODR 0x34 /* Clear Output Data Register */
|
||||
#define PIO_ODSR 0x38 /* Output Data Status Register */
|
||||
#define PIO_PDSR 0x3c /* Pin Data Status Register */
|
||||
#define PIO_IER 0x40 /* Interrupt Enable Register */
|
||||
#define PIO_IDR 0x44 /* Interrupt Disable Register */
|
||||
#define PIO_IMR 0x48 /* Interrupt Mask Register */
|
||||
#define PIO_ISR 0x4c /* Interrupt Status Register */
|
||||
#define PIO_MDER 0x50 /* Multi-driver Enable Register */
|
||||
#define PIO_MDDR 0x54 /* Multi-driver Disable Register */
|
||||
#define PIO_MDSR 0x58 /* Multi-driver Status Register */
|
||||
#define PIO_PUDR 0x60 /* Pull-up Disable Register */
|
||||
#define PIO_PUER 0x64 /* Pull-up Enable Register */
|
||||
#define PIO_PUSR 0x68 /* Pull-up Status Register */
|
||||
#define PIO_ASR 0x70 /* Peripheral A Select Register */
|
||||
#define PIO_ABCDSR1 0x70 /* Peripheral ABCD Select Register 1 [some sam9 only] */
|
||||
#define PIO_BSR 0x74 /* Peripheral B Select Register */
|
||||
#define PIO_ABCDSR2 0x74 /* Peripheral ABCD Select Register 2 [some sam9 only] */
|
||||
#define PIO_ABSR 0x78 /* AB Status Register */
|
||||
#define PIO_IFSCDR 0x80 /* Input Filter Slow Clock Disable Register */
|
||||
#define PIO_IFSCER 0x84 /* Input Filter Slow Clock Enable Register */
|
||||
#define PIO_IFSCSR 0x88 /* Input Filter Slow Clock Status Register */
|
||||
#define PIO_SCDR 0x8c /* Slow Clock Divider Debouncing Register */
|
||||
#define PIO_SCDR_DIV (0x3fff << 0) /* Slow Clock Divider Mask */
|
||||
#define PIO_PPDDR 0x90 /* Pad Pull-down Disable Register */
|
||||
#define PIO_PPDER 0x94 /* Pad Pull-down Enable Register */
|
||||
#define PIO_PPDSR 0x98 /* Pad Pull-down Status Register */
|
||||
#define PIO_OWER 0xa0 /* Output Write Enable Register */
|
||||
#define PIO_OWDR 0xa4 /* Output Write Disable Register */
|
||||
#define PIO_OWSR 0xa8 /* Output Write Status Register */
|
||||
#define PIO_AIMER 0xb0 /* Additional Interrupt Modes Enable Register */
|
||||
#define PIO_AIMDR 0xb4 /* Additional Interrupt Modes Disable Register */
|
||||
#define PIO_AIMMR 0xb8 /* Additional Interrupt Modes Mask Register */
|
||||
#define PIO_ESR 0xc0 /* Edge Select Register */
|
||||
#define PIO_LSR 0xc4 /* Level Select Register */
|
||||
#define PIO_ELSR 0xc8 /* Edge/Level Status Register */
|
||||
#define PIO_FELLSR 0xd0 /* Falling Edge/Low Level Select Register */
|
||||
#define PIO_REHLSR 0xd4 /* Rising Edge/ High Level Select Register */
|
||||
#define PIO_FRLHSR 0xd8 /* Fall/Rise - Low/High Status Register */
|
||||
#define PIO_SCHMITT 0x100 /* Schmitt Trigger Register */
|
||||
|
||||
#define ABCDSR_PERIPH_A 0x0
|
||||
#define ABCDSR_PERIPH_B 0x1
|
||||
#define ABCDSR_PERIPH_C 0x2
|
||||
#define ABCDSR_PERIPH_D 0x3
|
||||
|
||||
#define SAMA5D3_PIO_DRIVER1 0x118 /*PIO Driver 1 register offset*/
|
||||
#define SAMA5D3_PIO_DRIVER2 0x11C /*PIO Driver 2 register offset*/
|
||||
|
||||
#define AT91SAM9X5_PIO_DRIVER1 0x114 /*PIO Driver 1 register offset*/
|
||||
#define AT91SAM9X5_PIO_DRIVER2 0x118 /*PIO Driver 2 register offset*/
|
||||
|
||||
#endif
|
|
@ -1,35 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-at91/include/mach/at91_rtt.h
|
||||
*
|
||||
* Copyright (C) 2007 Andrew Victor
|
||||
* Copyright (C) 2007 Atmel Corporation.
|
||||
*
|
||||
* Real-time Timer (RTT) - System peripherals regsters.
|
||||
* Based on AT91SAM9261 datasheet revision D.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef AT91_RTT_H
|
||||
#define AT91_RTT_H
|
||||
|
||||
#define AT91_RTT_MR 0x00 /* Real-time Mode Register */
|
||||
#define AT91_RTT_RTPRES (0xffff << 0) /* Real-time Timer Prescaler Value */
|
||||
#define AT91_RTT_ALMIEN (1 << 16) /* Alarm Interrupt Enable */
|
||||
#define AT91_RTT_RTTINCIEN (1 << 17) /* Real Time Timer Increment Interrupt Enable */
|
||||
#define AT91_RTT_RTTRST (1 << 18) /* Real Time Timer Restart */
|
||||
|
||||
#define AT91_RTT_AR 0x04 /* Real-time Alarm Register */
|
||||
#define AT91_RTT_ALMV (0xffffffff) /* Alarm Value */
|
||||
|
||||
#define AT91_RTT_VR 0x08 /* Real-time Value Register */
|
||||
#define AT91_RTT_CRTV (0xffffffff) /* Current Real-time Value */
|
||||
|
||||
#define AT91_RTT_SR 0x0c /* Real-time Status Register */
|
||||
#define AT91_RTT_ALMS (1 << 0) /* Real-time Alarm Status */
|
||||
#define AT91_RTT_RTTINC (1 << 1) /* Real-time Timer Increment */
|
||||
|
||||
#endif
|
|
@ -1,26 +0,0 @@
|
|||
/*
|
||||
* arch/arm/mach-at91/include/mach/memory.h
|
||||
*
|
||||
* Copyright (C) 2004 SAN People
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_MEMORY_H
|
||||
#define __ASM_ARCH_MEMORY_H
|
||||
|
||||
#include <mach/hardware.h>
|
||||
|
||||
#endif
|
|
@ -1,27 +0,0 @@
|
|||
/*
|
||||
* Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
||||
*
|
||||
* Under GPLv2 only
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_SYSTEM_REV_H__
|
||||
#define __ARCH_SYSTEM_REV_H__
|
||||
|
||||
#include <asm/system_info.h>
|
||||
|
||||
/*
|
||||
* board revision encoding
|
||||
* mach specific
|
||||
* the 16-31 bit are reserved for at91 generic information
|
||||
*
|
||||
* bit 31:
|
||||
* 0 => nand 8 bit
|
||||
* 1 => nand 16 bit
|
||||
*/
|
||||
#define BOARD_HAVE_NAND_16BIT (1 << 31)
|
||||
static inline int board_have_nand_16bit(void)
|
||||
{
|
||||
return (system_rev & BOARD_HAVE_NAND_16BIT) ? 1 : 0;
|
||||
}
|
||||
|
||||
#endif /* __ARCH_SYSTEM_REV_H__ */
|
|
@ -14,9 +14,12 @@
|
|||
#include <linux/suspend.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/proc_fs.h>
|
||||
#include <linux/genalloc.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/sysfs.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/clk/at91_pmc.h>
|
||||
|
@ -32,6 +35,11 @@
|
|||
#include "generic.h"
|
||||
#include "pm.h"
|
||||
|
||||
static struct {
|
||||
unsigned long uhp_udp_mask;
|
||||
int memctrl;
|
||||
} at91_pm_data;
|
||||
|
||||
static void (*at91_pm_standby)(void);
|
||||
|
||||
static int at91_pm_valid_state(suspend_state_t state)
|
||||
|
@ -71,17 +79,9 @@ static int at91_pm_verify_clocks(void)
|
|||
scsr = at91_pmc_read(AT91_PMC_SCSR);
|
||||
|
||||
/* USB must not be using PLLB */
|
||||
if (cpu_is_at91rm9200()) {
|
||||
if ((scsr & (AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP)) != 0) {
|
||||
pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
|
||||
return 0;
|
||||
}
|
||||
} else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263()
|
||||
|| cpu_is_at91sam9g20() || cpu_is_at91sam9g10()) {
|
||||
if ((scsr & (AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP)) != 0) {
|
||||
pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
|
||||
return 0;
|
||||
}
|
||||
if ((scsr & at91_pm_data.uhp_udp_mask) != 0) {
|
||||
pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* PCK0..PCK3 must be disabled, or configured to use clk32k */
|
||||
|
@ -149,18 +149,13 @@ static int at91_pm_enter(suspend_state_t state)
|
|||
* turning off the main oscillator; reverse on wakeup.
|
||||
*/
|
||||
if (slow_clock) {
|
||||
int memctrl = AT91_MEMCTRL_SDRAMC;
|
||||
|
||||
if (cpu_is_at91rm9200())
|
||||
memctrl = AT91_MEMCTRL_MC;
|
||||
else if (cpu_is_at91sam9g45())
|
||||
memctrl = AT91_MEMCTRL_DDRSDR;
|
||||
#ifdef CONFIG_AT91_SLOW_CLOCK
|
||||
/* copy slow_clock handler to SRAM, and call it */
|
||||
memcpy(slow_clock, at91_slow_clock, at91_slow_clock_sz);
|
||||
#endif
|
||||
slow_clock(at91_pmc_base, at91_ramc_base[0],
|
||||
at91_ramc_base[1], memctrl);
|
||||
at91_ramc_base[1],
|
||||
at91_pm_data.memctrl);
|
||||
break;
|
||||
} else {
|
||||
pr_info("AT91: PM - no slow clock mode enabled ...\n");
|
||||
|
@ -229,23 +224,92 @@ void at91_pm_set_standby(void (*at91_standby)(void))
|
|||
}
|
||||
}
|
||||
|
||||
static int __init at91_pm_init(void)
|
||||
#ifdef CONFIG_AT91_SLOW_CLOCK
|
||||
static void __init at91_pm_sram_init(void)
|
||||
{
|
||||
struct gen_pool *sram_pool;
|
||||
phys_addr_t sram_pbase;
|
||||
unsigned long sram_base;
|
||||
struct device_node *node;
|
||||
struct platform_device *pdev;
|
||||
|
||||
node = of_find_compatible_node(NULL, NULL, "mmio-sram");
|
||||
if (!node) {
|
||||
pr_warn("%s: failed to find sram node!\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
pdev = of_find_device_by_node(node);
|
||||
if (!pdev) {
|
||||
pr_warn("%s: failed to find sram device!\n", __func__);
|
||||
goto put_node;
|
||||
}
|
||||
|
||||
sram_pool = dev_get_gen_pool(&pdev->dev);
|
||||
if (!sram_pool) {
|
||||
pr_warn("%s: sram pool unavailable!\n", __func__);
|
||||
goto put_node;
|
||||
}
|
||||
|
||||
sram_base = gen_pool_alloc(sram_pool, at91_slow_clock_sz);
|
||||
if (!sram_base) {
|
||||
pr_warn("%s: unable to alloc ocram!\n", __func__);
|
||||
goto put_node;
|
||||
}
|
||||
|
||||
sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base);
|
||||
slow_clock = __arm_ioremap_exec(sram_pbase, at91_slow_clock_sz, false);
|
||||
|
||||
put_node:
|
||||
of_node_put(node);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
static void __init at91_pm_init(void)
|
||||
{
|
||||
#ifdef CONFIG_AT91_SLOW_CLOCK
|
||||
slow_clock = (void *) (AT91_IO_VIRT_BASE - at91_slow_clock_sz);
|
||||
at91_pm_sram_init();
|
||||
#endif
|
||||
|
||||
pr_info("AT91: Power Management%s\n", (slow_clock ? " (with slow clock mode)" : ""));
|
||||
|
||||
/* AT91RM9200 SDRAM low-power mode cannot be used with self-refresh. */
|
||||
if (cpu_is_at91rm9200())
|
||||
at91_ramc_write(0, AT91RM9200_SDRAMC_LPR, 0);
|
||||
|
||||
if (at91_cpuidle_device.dev.platform_data)
|
||||
platform_device_register(&at91_cpuidle_device);
|
||||
|
||||
suspend_set_ops(&at91_pm_ops);
|
||||
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(at91_pm_init);
|
||||
|
||||
void __init at91_rm9200_pm_init(void)
|
||||
{
|
||||
/*
|
||||
* AT91RM9200 SDRAM low-power mode cannot be used with self-refresh.
|
||||
*/
|
||||
at91_ramc_write(0, AT91RM9200_SDRAMC_LPR, 0);
|
||||
|
||||
at91_pm_data.uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP;
|
||||
at91_pm_data.memctrl = AT91_MEMCTRL_MC;
|
||||
|
||||
at91_pm_init();
|
||||
}
|
||||
|
||||
void __init at91_sam9260_pm_init(void)
|
||||
{
|
||||
at91_pm_data.memctrl = AT91_MEMCTRL_SDRAMC;
|
||||
at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
|
||||
return at91_pm_init();
|
||||
}
|
||||
|
||||
void __init at91_sam9g45_pm_init(void)
|
||||
{
|
||||
at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP;
|
||||
at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
|
||||
return at91_pm_init();
|
||||
}
|
||||
|
||||
void __init at91_sam9x5_pm_init(void)
|
||||
{
|
||||
at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
|
||||
at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
|
||||
return at91_pm_init();
|
||||
}
|
||||
|
|
|
@ -17,15 +17,6 @@
|
|||
#include <mach/hardware.h>
|
||||
#include <mach/at91_ramc.h>
|
||||
|
||||
|
||||
#ifdef CONFIG_SOC_AT91SAM9263
|
||||
/*
|
||||
* FIXME either or both the SDRAM controllers (EB0, EB1) might be in use;
|
||||
* handle those cases both here and in the Suspend-To-RAM support.
|
||||
*/
|
||||
#warning Assuming EB1 SDRAM controller is *NOT* used
|
||||
#endif
|
||||
|
||||
/*
|
||||
* When SLOWDOWN_MASTER_CLOCK is defined we will also slow down the Master
|
||||
* clock during suspend by adjusting its prescalar and divisor.
|
||||
|
|
|
@ -25,17 +25,5 @@
|
|||
* AT91SAM9x5 processor initialization
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
static void __init sama5d3_map_io(void)
|
||||
{
|
||||
at91_init_sram(0, SAMA5D3_SRAM_BASE, SAMA5D3_SRAM_SIZE);
|
||||
}
|
||||
|
||||
static void __init sama5d3_initialize(void)
|
||||
{
|
||||
at91_sysirq_mask_rtc(SAMA5D3_BASE_RTC);
|
||||
}
|
||||
|
||||
AT91_SOC_START(sama5d3)
|
||||
.map_io = sama5d3_map_io,
|
||||
.init = sama5d3_initialize,
|
||||
AT91_SOC_END
|
||||
|
|
|
@ -56,7 +56,6 @@ static struct map_desc at91_io_desc[] __initdata = {
|
|||
static void __init sama5d4_map_io(void)
|
||||
{
|
||||
iotable_init(at91_io_desc, ARRAY_SIZE(at91_io_desc));
|
||||
at91_init_sram(0, SAMA5D4_NS_SRAM_BASE, SAMA5D4_NS_SRAM_SIZE);
|
||||
}
|
||||
|
||||
AT91_SOC_START(sama5d4)
|
||||
|
|
|
@ -31,40 +31,9 @@ struct at91_init_soc __initdata at91_boot_soc;
|
|||
struct at91_socinfo at91_soc_initdata;
|
||||
EXPORT_SYMBOL(at91_soc_initdata);
|
||||
|
||||
void __init at91rm9200_set_type(int type)
|
||||
{
|
||||
if (type == ARCH_REVISON_9200_PQFP)
|
||||
at91_soc_initdata.subtype = AT91_SOC_RM9200_PQFP;
|
||||
else
|
||||
at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
|
||||
|
||||
pr_info("filled in soc subtype: %s\n",
|
||||
at91_get_soc_subtype(&at91_soc_initdata));
|
||||
}
|
||||
|
||||
void __iomem *at91_ramc_base[2];
|
||||
EXPORT_SYMBOL_GPL(at91_ramc_base);
|
||||
|
||||
static struct map_desc sram_desc[2] __initdata;
|
||||
|
||||
void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
|
||||
{
|
||||
struct map_desc *desc = &sram_desc[bank];
|
||||
|
||||
desc->virtual = (unsigned long)AT91_IO_VIRT_BASE - length;
|
||||
if (bank > 0)
|
||||
desc->virtual -= sram_desc[bank - 1].length;
|
||||
|
||||
desc->pfn = __phys_to_pfn(base);
|
||||
desc->length = length;
|
||||
desc->type = MT_MEMORY_RWX_NONCACHED;
|
||||
|
||||
pr_info("sram at 0x%lx of 0x%x mapped at 0x%lx\n",
|
||||
base, length, desc->virtual);
|
||||
|
||||
iotable_init(desc, 1);
|
||||
}
|
||||
|
||||
static struct map_desc at91_io_desc __initdata __maybe_unused = {
|
||||
.virtual = (unsigned long)AT91_VA_BASE_SYS,
|
||||
.pfn = __phys_to_pfn(AT91_BASE_SYS),
|
||||
|
@ -429,13 +398,6 @@ static void at91_dt_ramc(void)
|
|||
at91_pm_set_standby(standby);
|
||||
}
|
||||
|
||||
void __init at91rm9200_dt_initialize(void)
|
||||
{
|
||||
at91_dt_ramc();
|
||||
|
||||
at91_boot_soc.init();
|
||||
}
|
||||
|
||||
void __init at91_dt_initialize(void)
|
||||
{
|
||||
at91_dt_ramc();
|
||||
|
|
|
@ -1,75 +0,0 @@
|
|||
/*
|
||||
* sysirq_mask.c - System-interrupt masking
|
||||
*
|
||||
* Copyright (C) 2013 Johan Hovold <jhovold@gmail.com>
|
||||
*
|
||||
* Functions to disable system interrupts from backup-powered peripherals.
|
||||
*
|
||||
* The RTC and RTT-peripherals are generally powered by backup power (VDDBU)
|
||||
* and are not reset on wake-up, user, watchdog or software reset. This means
|
||||
* that their interrupts may be enabled during early boot (e.g. after a user
|
||||
* reset).
|
||||
*
|
||||
* As the RTC and RTT share the system-interrupt line with the PIT, an
|
||||
* interrupt occurring before a handler has been installed would lead to the
|
||||
* system interrupt being disabled and prevent the system from booting.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <mach/at91_rtt.h>
|
||||
|
||||
#include "generic.h"
|
||||
|
||||
#define AT91_RTC_IDR 0x24 /* Interrupt Disable Register */
|
||||
#define AT91_RTC_IMR 0x28 /* Interrupt Mask Register */
|
||||
#define AT91_RTC_IRQ_MASK 0x1f /* Available IRQs mask */
|
||||
|
||||
void __init at91_sysirq_mask_rtc(u32 rtc_base)
|
||||
{
|
||||
void __iomem *base;
|
||||
|
||||
base = ioremap(rtc_base, 64);
|
||||
if (!base)
|
||||
return;
|
||||
|
||||
/*
|
||||
* sam9x5 SoCs have the following errata:
|
||||
* "RTC: Interrupt Mask Register cannot be used
|
||||
* Interrupt Mask Register read always returns 0."
|
||||
*
|
||||
* Hence we're not relying on IMR values to disable
|
||||
* interrupts.
|
||||
*/
|
||||
writel_relaxed(AT91_RTC_IRQ_MASK, base + AT91_RTC_IDR);
|
||||
(void)readl_relaxed(base + AT91_RTC_IMR); /* flush */
|
||||
|
||||
iounmap(base);
|
||||
}
|
||||
|
||||
void __init at91_sysirq_mask_rtt(u32 rtt_base)
|
||||
{
|
||||
void __iomem *base;
|
||||
void __iomem *reg;
|
||||
u32 mode;
|
||||
|
||||
base = ioremap(rtt_base, 16);
|
||||
if (!base)
|
||||
return;
|
||||
|
||||
reg = base + AT91_RTT_MR;
|
||||
|
||||
mode = readl_relaxed(reg);
|
||||
if (mode & (AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN)) {
|
||||
pr_info("AT91: Disabling rtt irq\n");
|
||||
mode &= ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN);
|
||||
writel_relaxed(mode, reg);
|
||||
(void)readl_relaxed(reg); /* flush */
|
||||
}
|
||||
|
||||
iounmap(base);
|
||||
}
|
|
@ -27,6 +27,15 @@
|
|||
void __iomem *at91_pmc_base;
|
||||
EXPORT_SYMBOL_GPL(at91_pmc_base);
|
||||
|
||||
void at91rm9200_idle(void)
|
||||
{
|
||||
/*
|
||||
* Disable the processor clock. The processor will be automatically
|
||||
* re-enabled by an interrupt or by a reset.
|
||||
*/
|
||||
at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
|
||||
}
|
||||
|
||||
void at91sam9_idle(void)
|
||||
{
|
||||
at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
|
||||
|
|
|
@ -1141,34 +1141,6 @@ config RTC_DRV_AT91SAM9
|
|||
probably want to use the real RTC block instead of the "RTT as an
|
||||
RTC" driver.
|
||||
|
||||
config RTC_DRV_AT91SAM9_RTT
|
||||
int
|
||||
range 0 1
|
||||
default 0
|
||||
depends on RTC_DRV_AT91SAM9
|
||||
help
|
||||
This option is only relevant for legacy board support and
|
||||
won't be used when booting a DT board.
|
||||
|
||||
More than one RTT module is available. You can choose which
|
||||
one will be used as an RTC. The default of zero is normally
|
||||
OK to use, though some systems use that for non-RTC purposes.
|
||||
|
||||
config RTC_DRV_AT91SAM9_GPBR
|
||||
int
|
||||
range 0 3
|
||||
default 0
|
||||
prompt "Backup Register Number"
|
||||
depends on RTC_DRV_AT91SAM9
|
||||
help
|
||||
This option is only relevant for legacy board support and
|
||||
won't be used when booting a DT board.
|
||||
|
||||
The RTC driver needs to use one of the General Purpose Backup
|
||||
Registers (GPBRs) as well as the RTT. You can choose which one
|
||||
will be used. The default of zero is normally OK to use, but
|
||||
on some systems other software needs to use that register.
|
||||
|
||||
config RTC_DRV_AU1XXX
|
||||
tristate "Au1xxx Counter0 RTC support"
|
||||
depends on MIPS_ALCHEMY
|
||||
|
|
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Reference in New Issue