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Pin control fixes for the v3.18 series: 

- Two fixes for the Baytrail driver affecting IRQs and
   output state in sysfs
 - Use the linux-gpio mailing list also for pinctrl patches
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Merge tag 'pinctrl-v3.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin-control fixes from Linus Walleij:
 "This kernel cycle has been calm for both pin control and GPIO so far
  but here are three pin control patches for you anyway, only really
  dealing with Baytrail:

   - Two fixes for the Baytrail driver affecting IRQs and output state
     in sysfs
   - Use the linux-gpio mailing list also for pinctrl patches"

* tag 'pinctrl-v3.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl:
  pinctrl: baytrail: show output gpio state correctly on Intel Baytrail
  pinctrl: use linux-gpio mailing list
  pinctrl: baytrail: Clear DIRECT_IRQ bit
This commit is contained in:
Linus Torvalds 2014-11-03 21:06:22 -08:00
parent f3ed88a6bc d90c338189
commit 980d0d51b1
2 changed files with 7 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
MAINTAINERS
View File

@ -7180,6 +7180,7 @@ F: drivers/crypto/picoxcell*
PIN CONTROL SUBSYSTEM
M: Linus Walleij <linus.walleij@linaro.org>
L: linux-gpio@vger.kernel.org
S: Maintained
F: drivers/pinctrl/
F: include/linux/pinctrl/

8
drivers/pinctrl/pinctrl-baytrail.c
View File

@ -227,10 +227,14 @@ static int byt_irq_type(struct irq_data *d, unsigned type)
spin_lock_irqsave(&vg->lock, flags);
value = readl(reg);
WARN(value & BYT_DIRECT_IRQ_EN,
"Bad pad config for io mode, force direct_irq_en bit clearing");
/* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits
* are used to indicate high and low level triggering
*/
value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG |
BYT_TRIG_LVL);
switch (type) {
case IRQ_TYPE_LEVEL_HIGH:
@ -318,7 +322,7 @@ static int byt_gpio_direction_output(struct gpio_chip *chip,
"Potential Error: Setting GPIO with direct_irq_en to output");
reg_val = readl(reg) | BYT_DIR_MASK;
reg_val &= ~BYT_OUTPUT_EN;
reg_val &= ~(BYT_OUTPUT_EN | BYT_INPUT_EN);
if (value)
writel(reg_val | BYT_LEVEL, reg);