nvmem: add snvs_lpgpr driver
This is a driver for Low Power General Purpose Register (LPGPR) available on i.MX6 SoCs in Secure Non-Volatile Storage (SNVS) of this chip. It is a 32-bit read/write register located in the low power domain. Since LPGPR is located in the battery-backed power domain, LPGPR can be used by any application for retaining data during an SoC power-down mode. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -144,4 +144,14 @@ config MESON_EFUSE
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This driver can also be built as a module. If so, the module
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This driver can also be built as a module. If so, the module
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will be called nvmem_meson_efuse.
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will be called nvmem_meson_efuse.
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config NVMEM_SNVS_LPGPR
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tristate "Support for Low Power General Purpose Register"
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depends on SOC_IMX6 || COMPILE_TEST
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help
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This is a driver for Low Power General Purpose Register (LPGPR) available on
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i.MX6 SoCs in Secure Non-Volatile Storage (SNVS) of this chip.
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This driver can also be built as a module. If so, the module
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will be called nvmem-snvs-lpgpr.
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endif
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endif
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@ -30,3 +30,5 @@ obj-$(CONFIG_NVMEM_VF610_OCOTP) += nvmem-vf610-ocotp.o
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nvmem-vf610-ocotp-y := vf610-ocotp.o
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nvmem-vf610-ocotp-y := vf610-ocotp.o
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obj-$(CONFIG_MESON_EFUSE) += nvmem_meson_efuse.o
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obj-$(CONFIG_MESON_EFUSE) += nvmem_meson_efuse.o
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nvmem_meson_efuse-y := meson-efuse.o
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nvmem_meson_efuse-y := meson-efuse.o
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obj-$(CONFIG_NVMEM_SNVS_LPGPR) += nvmem_snvs_lpgpr.o
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nvmem_snvs_lpgpr-y := snvs_lpgpr.o
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@ -0,0 +1,156 @@
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/*
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* Copyright (c) 2015 Pengutronix, Steffen Trumtrar <kernel@pengutronix.de>
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* Copyright (c) 2017 Pengutronix, Oleksij Rempel <kernel@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2
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* as published by the Free Software Foundation.
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*/
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/nvmem-provider.h>
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#include <linux/of_device.h>
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#include <linux/regmap.h>
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#define IMX6Q_SNVS_HPLR 0x00
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#define IMX6Q_GPR_SL BIT(5)
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#define IMX6Q_SNVS_LPLR 0x34
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#define IMX6Q_GPR_HL BIT(5)
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#define IMX6Q_SNVS_LPGPR 0x68
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struct snvs_lpgpr_cfg {
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int offset;
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int offset_hplr;
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int offset_lplr;
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};
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struct snvs_lpgpr_priv {
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struct device_d *dev;
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struct regmap *regmap;
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struct nvmem_config cfg;
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const struct snvs_lpgpr_cfg *dcfg;
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};
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static const struct snvs_lpgpr_cfg snvs_lpgpr_cfg_imx6q = {
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.offset = IMX6Q_SNVS_LPGPR,
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.offset_hplr = IMX6Q_SNVS_HPLR,
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.offset_lplr = IMX6Q_SNVS_LPLR,
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};
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static int snvs_lpgpr_write(void *context, unsigned int offset, void *val,
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size_t bytes)
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{
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struct snvs_lpgpr_priv *priv = context;
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const struct snvs_lpgpr_cfg *dcfg = priv->dcfg;
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unsigned int lock_reg;
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int ret;
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ret = regmap_read(priv->regmap, dcfg->offset_hplr, &lock_reg);
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if (ret < 0)
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return ret;
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if (lock_reg & IMX6Q_GPR_SL)
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return -EPERM;
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ret = regmap_read(priv->regmap, dcfg->offset_lplr, &lock_reg);
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if (ret < 0)
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return ret;
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if (lock_reg & IMX6Q_GPR_HL)
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return -EPERM;
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return regmap_bulk_write(priv->regmap, dcfg->offset + offset, val,
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bytes / 4);
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}
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static int snvs_lpgpr_read(void *context, unsigned int offset, void *val,
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size_t bytes)
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{
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struct snvs_lpgpr_priv *priv = context;
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const struct snvs_lpgpr_cfg *dcfg = priv->dcfg;
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return regmap_bulk_read(priv->regmap, dcfg->offset + offset,
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val, bytes / 4);
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}
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static int snvs_lpgpr_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *node = dev->of_node;
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struct device_node *syscon_node;
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struct snvs_lpgpr_priv *priv;
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struct nvmem_config *cfg;
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struct nvmem_device *nvmem;
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const struct snvs_lpgpr_cfg *dcfg;
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if (!node)
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return -ENOENT;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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dcfg = of_device_get_match_data(dev);
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if (!dcfg)
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return -EINVAL;
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syscon_node = of_get_parent(node);
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if (!syscon_node)
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return -ENODEV;
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priv->regmap = syscon_node_to_regmap(syscon_node);
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of_node_put(syscon_node);
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if (IS_ERR(priv->regmap))
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return PTR_ERR(priv->regmap);
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priv->dcfg = dcfg;
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cfg = &priv->cfg;
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cfg->priv = priv;
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cfg->name = dev_name(dev);
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cfg->dev = dev;
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cfg->stride = 4,
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cfg->word_size = 4,
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cfg->size = 4,
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cfg->owner = THIS_MODULE,
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cfg->reg_read = snvs_lpgpr_read,
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cfg->reg_write = snvs_lpgpr_write,
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nvmem = nvmem_register(cfg);
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if (IS_ERR(nvmem))
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return PTR_ERR(nvmem);
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platform_set_drvdata(pdev, nvmem);
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return 0;
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}
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static int snvs_lpgpr_remove(struct platform_device *pdev)
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{
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struct nvmem_device *nvmem = platform_get_drvdata(pdev);
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return nvmem_unregister(nvmem);
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}
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static const struct of_device_id snvs_lpgpr_dt_ids[] = {
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{ .compatible = "fsl,imx6q-snvs-lpgpr", .data = &snvs_lpgpr_cfg_imx6q },
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{ .compatible = "fsl,imx6ul-snvs-lpgpr",
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.data = &snvs_lpgpr_cfg_imx6q },
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{ },
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};
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MODULE_DEVICE_TABLE(of, snvs_lpgpr_dt_ids);
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static struct platform_driver snvs_lpgpr_driver = {
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.probe = snvs_lpgpr_probe,
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.remove = snvs_lpgpr_remove,
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.driver = {
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.name = "snvs_lpgpr",
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.of_match_table = snvs_lpgpr_dt_ids,
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},
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};
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module_platform_driver(snvs_lpgpr_driver);
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MODULE_AUTHOR("Oleksij Rempel <o.rempel@pengutronix.de>");
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MODULE_DESCRIPTION("Low Power General Purpose Register in i.MX6 Secure Non-Volatile Storage");
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MODULE_LICENSE("GPL v2");
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