bnxt_en: Check context memory requirements from firmware.
New device requires host context memory as a backing store. Call firmware to check for context memory requirements and store the parameters. Allocate host pages accordingly. We also need to move the call bnxt_hwrm_queue_qportcfg() earlier so that all the supported hardware queues and the IDs are known before checking and allocating context memory. Signed-off-by: Michael Chan <michael.chan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Michael Chan
David S. Miller
parent
66cca20abc
commit
98f04cf0f1
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@ -5255,6 +5255,187 @@ func_qcfg_exit:
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return rc;
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}
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static int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
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{
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struct hwrm_func_backing_store_qcaps_input req = {0};
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struct hwrm_func_backing_store_qcaps_output *resp =
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bp->hwrm_cmd_resp_addr;
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int rc;
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if (bp->hwrm_spec_code < 0x10902 || BNXT_VF(bp) || bp->ctx)
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return 0;
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bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_QCAPS, -1, -1);
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mutex_lock(&bp->hwrm_cmd_lock);
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rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
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if (!rc) {
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struct bnxt_ctx_pg_info *ctx_pg;
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struct bnxt_ctx_mem_info *ctx;
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int i;
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ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
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if (!ctx) {
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rc = -ENOMEM;
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goto ctx_err;
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}
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ctx_pg = kzalloc(sizeof(*ctx_pg) * (bp->max_q + 1), GFP_KERNEL);
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if (!ctx_pg) {
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kfree(ctx);
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rc = -ENOMEM;
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goto ctx_err;
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}
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for (i = 0; i < bp->max_q + 1; i++, ctx_pg++)
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ctx->tqm_mem[i] = ctx_pg;
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bp->ctx = ctx;
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ctx->qp_max_entries = le32_to_cpu(resp->qp_max_entries);
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ctx->qp_min_qp1_entries = le16_to_cpu(resp->qp_min_qp1_entries);
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ctx->qp_max_l2_entries = le16_to_cpu(resp->qp_max_l2_entries);
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ctx->qp_entry_size = le16_to_cpu(resp->qp_entry_size);
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ctx->srq_max_l2_entries = le16_to_cpu(resp->srq_max_l2_entries);
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ctx->srq_max_entries = le32_to_cpu(resp->srq_max_entries);
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ctx->srq_entry_size = le16_to_cpu(resp->srq_entry_size);
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ctx->cq_max_l2_entries = le16_to_cpu(resp->cq_max_l2_entries);
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ctx->cq_max_entries = le32_to_cpu(resp->cq_max_entries);
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ctx->cq_entry_size = le16_to_cpu(resp->cq_entry_size);
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ctx->vnic_max_vnic_entries =
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le16_to_cpu(resp->vnic_max_vnic_entries);
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ctx->vnic_max_ring_table_entries =
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le16_to_cpu(resp->vnic_max_ring_table_entries);
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ctx->vnic_entry_size = le16_to_cpu(resp->vnic_entry_size);
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ctx->stat_max_entries = le32_to_cpu(resp->stat_max_entries);
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ctx->stat_entry_size = le16_to_cpu(resp->stat_entry_size);
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ctx->tqm_entry_size = le16_to_cpu(resp->tqm_entry_size);
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ctx->tqm_min_entries_per_ring =
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le32_to_cpu(resp->tqm_min_entries_per_ring);
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ctx->tqm_max_entries_per_ring =
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le32_to_cpu(resp->tqm_max_entries_per_ring);
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ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
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if (!ctx->tqm_entries_multiple)
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ctx->tqm_entries_multiple = 1;
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ctx->mrav_max_entries = le32_to_cpu(resp->mrav_max_entries);
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ctx->mrav_entry_size = le16_to_cpu(resp->mrav_entry_size);
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ctx->tim_entry_size = le16_to_cpu(resp->tim_entry_size);
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ctx->tim_max_entries = le32_to_cpu(resp->tim_max_entries);
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} else {
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rc = 0;
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}
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ctx_err:
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mutex_unlock(&bp->hwrm_cmd_lock);
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return rc;
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}
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static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
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struct bnxt_ctx_pg_info *ctx_pg, u32 mem_size)
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{
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struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
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if (!mem_size)
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return 0;
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rmem->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE);
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if (rmem->nr_pages > MAX_CTX_PAGES) {
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rmem->nr_pages = 0;
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return -EINVAL;
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}
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rmem->page_size = BNXT_PAGE_SIZE;
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rmem->pg_arr = ctx_pg->ctx_pg_arr;
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rmem->dma_arr = ctx_pg->ctx_dma_arr;
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return bnxt_alloc_ring(bp, rmem);
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}
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static void bnxt_free_ctx_mem(struct bnxt *bp)
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{
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struct bnxt_ctx_mem_info *ctx = bp->ctx;
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int i;
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if (!ctx)
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return;
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if (ctx->tqm_mem[0]) {
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for (i = 0; i < bp->max_q + 1; i++)
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bnxt_free_ring(bp, &ctx->tqm_mem[i]->ring_mem);
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kfree(ctx->tqm_mem[0]);
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ctx->tqm_mem[0] = NULL;
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}
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bnxt_free_ring(bp, &ctx->stat_mem.ring_mem);
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bnxt_free_ring(bp, &ctx->vnic_mem.ring_mem);
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bnxt_free_ring(bp, &ctx->cq_mem.ring_mem);
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bnxt_free_ring(bp, &ctx->srq_mem.ring_mem);
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bnxt_free_ring(bp, &ctx->qp_mem.ring_mem);
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ctx->flags &= ~BNXT_CTX_FLAG_INITED;
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}
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static int bnxt_alloc_ctx_mem(struct bnxt *bp)
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{
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struct bnxt_ctx_pg_info *ctx_pg;
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struct bnxt_ctx_mem_info *ctx;
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u32 mem_size, entries;
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int i, rc;
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rc = bnxt_hwrm_func_backing_store_qcaps(bp);
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if (rc) {
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netdev_err(bp->dev, "Failed querying context mem capability, rc = %d.\n",
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rc);
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return rc;
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}
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ctx = bp->ctx;
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if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
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return 0;
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ctx_pg = &ctx->qp_mem;
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ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries;
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mem_size = ctx->qp_entry_size * ctx_pg->entries;
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rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size);
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if (rc)
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return rc;
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ctx_pg = &ctx->srq_mem;
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ctx_pg->entries = ctx->srq_max_l2_entries;
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mem_size = ctx->srq_entry_size * ctx_pg->entries;
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rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size);
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if (rc)
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return rc;
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ctx_pg = &ctx->cq_mem;
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ctx_pg->entries = ctx->cq_max_l2_entries;
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mem_size = ctx->cq_entry_size * ctx_pg->entries;
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rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size);
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if (rc)
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return rc;
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ctx_pg = &ctx->vnic_mem;
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ctx_pg->entries = ctx->vnic_max_vnic_entries +
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ctx->vnic_max_ring_table_entries;
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mem_size = ctx->vnic_entry_size * ctx_pg->entries;
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rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size);
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if (rc)
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return rc;
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ctx_pg = &ctx->stat_mem;
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ctx_pg->entries = ctx->stat_max_entries;
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mem_size = ctx->stat_entry_size * ctx_pg->entries;
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rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size);
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if (rc)
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return rc;
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entries = ctx->qp_max_l2_entries;
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entries = roundup(entries, ctx->tqm_entries_multiple);
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entries = clamp_t(u32, entries, ctx->tqm_min_entries_per_ring,
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ctx->tqm_max_entries_per_ring);
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for (i = 0; i < bp->max_q + 1; i++) {
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ctx_pg = ctx->tqm_mem[i];
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ctx_pg->entries = entries;
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mem_size = ctx->tqm_entry_size * entries;
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rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size);
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if (rc)
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return rc;
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}
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ctx->flags |= BNXT_CTX_FLAG_INITED;
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return 0;
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}
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int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all)
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{
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struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
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@ -5382,6 +5563,9 @@ static int bnxt_hwrm_func_qcaps(struct bnxt *bp)
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if (rc)
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return rc;
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if (bp->hwrm_spec_code >= 0x10803) {
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rc = bnxt_alloc_ctx_mem(bp);
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if (rc)
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return rc;
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rc = bnxt_hwrm_func_resc_qcaps(bp, true);
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if (!rc)
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bp->fw_cap |= BNXT_FW_CAP_NEW_RM;
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@ -5426,13 +5610,15 @@ static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
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no_rdma = !(bp->flags & BNXT_FLAG_ROCE_CAP);
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qptr = &resp->queue_id0;
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for (i = 0, j = 0; i < bp->max_tc; i++) {
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bp->q_info[j].queue_id = *qptr++;
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bp->q_info[j].queue_id = *qptr;
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bp->q_ids[i] = *qptr++;
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bp->q_info[j].queue_profile = *qptr++;
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bp->tc_to_qidx[j] = j;
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if (!BNXT_CNPQ(bp->q_info[j].queue_profile) ||
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(no_rdma && BNXT_PF(bp)))
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j++;
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}
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bp->max_q = bp->max_tc;
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bp->max_tc = max_t(u8, j, 1);
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if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG)
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@ -8682,6 +8868,9 @@ static void bnxt_remove_one(struct pci_dev *pdev)
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bnxt_dcb_free(bp);
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kfree(bp->edev);
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bp->edev = NULL;
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bnxt_free_ctx_mem(bp);
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kfree(bp->ctx);
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bp->ctx = NULL;
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bnxt_cleanup_pci(bp);
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free_netdev(dev);
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}
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@ -9075,6 +9264,13 @@ static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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bp->ulp_probe = bnxt_ulp_probe;
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rc = bnxt_hwrm_queue_qportcfg(bp);
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if (rc) {
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netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
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rc);
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rc = -1;
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goto init_err_pci_clean;
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}
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/* Get the MAX capabilities for this function */
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rc = bnxt_hwrm_func_qcaps(bp);
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if (rc) {
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@ -9089,13 +9285,6 @@ static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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rc = -EADDRNOTAVAIL;
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goto init_err_pci_clean;
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}
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rc = bnxt_hwrm_queue_qportcfg(bp);
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if (rc) {
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netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
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rc);
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rc = -1;
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goto init_err_pci_clean;
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}
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bnxt_hwrm_func_qcfg(bp);
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bnxt_hwrm_port_led_qcaps(bp);
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@ -9195,6 +9384,9 @@ init_err_cleanup_tc:
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init_err_pci_clean:
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bnxt_free_hwrm_resources(bp);
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bnxt_free_ctx_mem(bp);
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kfree(bp->ctx);
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bp->ctx = NULL;
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bnxt_cleanup_pci(bp);
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init_err_free:
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@ -1117,6 +1117,51 @@ struct bnxt_vf_rep {
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#define PTU_PTE_LAST 0x2UL
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#define PTU_PTE_NEXT_TO_LAST 0x4UL
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#define MAX_CTX_PAGES (BNXT_PAGE_SIZE / 8)
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struct bnxt_ctx_pg_info {
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u32 entries;
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void *ctx_pg_arr[MAX_CTX_PAGES];
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dma_addr_t ctx_dma_arr[MAX_CTX_PAGES];
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struct bnxt_ring_mem_info ring_mem;
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};
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struct bnxt_ctx_mem_info {
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u32 qp_max_entries;
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u16 qp_min_qp1_entries;
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u16 qp_max_l2_entries;
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u16 qp_entry_size;
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u16 srq_max_l2_entries;
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u32 srq_max_entries;
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u16 srq_entry_size;
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u16 cq_max_l2_entries;
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u32 cq_max_entries;
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u16 cq_entry_size;
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u16 vnic_max_vnic_entries;
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u16 vnic_max_ring_table_entries;
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u16 vnic_entry_size;
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u32 stat_max_entries;
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u16 stat_entry_size;
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u16 tqm_entry_size;
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u32 tqm_min_entries_per_ring;
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u32 tqm_max_entries_per_ring;
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u32 mrav_max_entries;
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u16 mrav_entry_size;
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u16 tim_entry_size;
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u32 tim_max_entries;
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u8 tqm_entries_multiple;
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u32 flags;
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#define BNXT_CTX_FLAG_INITED 0x01
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struct bnxt_ctx_pg_info qp_mem;
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struct bnxt_ctx_pg_info srq_mem;
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struct bnxt_ctx_pg_info cq_mem;
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struct bnxt_ctx_pg_info vnic_mem;
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struct bnxt_ctx_pg_info stat_mem;
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struct bnxt_ctx_pg_info *tqm_mem[9];
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};
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struct bnxt {
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void __iomem *bar0;
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void __iomem *bar1;
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@ -1309,6 +1354,8 @@ struct bnxt {
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u8 max_lltc; /* lossless TCs */
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struct bnxt_queue_info q_info[BNXT_MAX_QUEUE];
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u8 tc_to_qidx[BNXT_MAX_QUEUE];
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u8 q_ids[BNXT_MAX_QUEUE];
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u8 max_q;
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unsigned int current_interval;
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#define BNXT_TIMER_INTERVAL HZ
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@ -1412,6 +1459,7 @@ struct bnxt {
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struct bnxt_hw_resc hw_resc;
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struct bnxt_pf_info pf;
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struct bnxt_ctx_mem_info *ctx;
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#ifdef CONFIG_BNXT_SRIOV
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int nr_vfs;
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struct bnxt_vf_info vf;
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