gpio: pl061: make use of raw_spinlock variants
The pl061 gpio driver currently implements an irq_chip for handling interrupts; due to how irq_chip handling is done, it's necessary for the irq_chip methods to be invoked from hardirq context, even on a a real-time kernel. Because the spinlock_t type becomes a "sleeping" spinlock w/ RT kernels, it is not suitable to be used with irq_chips. A quick audit of the operations under the lock reveal that they do only minimal, bounded work, and are therefore safe to do under a raw spinlock. Signed-off-by: Julia Cartwright <julia@ni.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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@ -50,7 +50,7 @@ struct pl061_context_save_regs {
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#endif
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#endif
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struct pl061 {
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struct pl061 {
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spinlock_t lock;
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raw_spinlock_t lock;
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void __iomem *base;
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void __iomem *base;
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struct gpio_chip gc;
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struct gpio_chip gc;
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@ -74,11 +74,11 @@ static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
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unsigned long flags;
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unsigned long flags;
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unsigned char gpiodir;
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unsigned char gpiodir;
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spin_lock_irqsave(&pl061->lock, flags);
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raw_spin_lock_irqsave(&pl061->lock, flags);
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gpiodir = readb(pl061->base + GPIODIR);
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gpiodir = readb(pl061->base + GPIODIR);
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gpiodir &= ~(BIT(offset));
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gpiodir &= ~(BIT(offset));
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writeb(gpiodir, pl061->base + GPIODIR);
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writeb(gpiodir, pl061->base + GPIODIR);
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spin_unlock_irqrestore(&pl061->lock, flags);
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raw_spin_unlock_irqrestore(&pl061->lock, flags);
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return 0;
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return 0;
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}
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}
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@ -90,7 +90,7 @@ static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,
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unsigned long flags;
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unsigned long flags;
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unsigned char gpiodir;
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unsigned char gpiodir;
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spin_lock_irqsave(&pl061->lock, flags);
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raw_spin_lock_irqsave(&pl061->lock, flags);
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writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
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writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
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gpiodir = readb(pl061->base + GPIODIR);
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gpiodir = readb(pl061->base + GPIODIR);
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gpiodir |= BIT(offset);
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gpiodir |= BIT(offset);
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@ -101,7 +101,7 @@ static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,
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* a gpio pin before configuring it in OUT mode.
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* a gpio pin before configuring it in OUT mode.
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*/
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*/
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writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
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writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
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spin_unlock_irqrestore(&pl061->lock, flags);
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raw_spin_unlock_irqrestore(&pl061->lock, flags);
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return 0;
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return 0;
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}
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}
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@ -143,7 +143,7 @@ static int pl061_irq_type(struct irq_data *d, unsigned trigger)
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}
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}
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spin_lock_irqsave(&pl061->lock, flags);
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raw_spin_lock_irqsave(&pl061->lock, flags);
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gpioiev = readb(pl061->base + GPIOIEV);
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gpioiev = readb(pl061->base + GPIOIEV);
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gpiois = readb(pl061->base + GPIOIS);
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gpiois = readb(pl061->base + GPIOIS);
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@ -203,7 +203,7 @@ static int pl061_irq_type(struct irq_data *d, unsigned trigger)
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writeb(gpioibe, pl061->base + GPIOIBE);
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writeb(gpioibe, pl061->base + GPIOIBE);
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writeb(gpioiev, pl061->base + GPIOIEV);
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writeb(gpioiev, pl061->base + GPIOIEV);
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spin_unlock_irqrestore(&pl061->lock, flags);
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raw_spin_unlock_irqrestore(&pl061->lock, flags);
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return 0;
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return 0;
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}
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}
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@ -235,10 +235,10 @@ static void pl061_irq_mask(struct irq_data *d)
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u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
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u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
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u8 gpioie;
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u8 gpioie;
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spin_lock(&pl061->lock);
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raw_spin_lock(&pl061->lock);
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gpioie = readb(pl061->base + GPIOIE) & ~mask;
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gpioie = readb(pl061->base + GPIOIE) & ~mask;
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writeb(gpioie, pl061->base + GPIOIE);
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writeb(gpioie, pl061->base + GPIOIE);
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spin_unlock(&pl061->lock);
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raw_spin_unlock(&pl061->lock);
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}
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}
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static void pl061_irq_unmask(struct irq_data *d)
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static void pl061_irq_unmask(struct irq_data *d)
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@ -248,10 +248,10 @@ static void pl061_irq_unmask(struct irq_data *d)
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u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
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u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
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u8 gpioie;
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u8 gpioie;
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spin_lock(&pl061->lock);
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raw_spin_lock(&pl061->lock);
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gpioie = readb(pl061->base + GPIOIE) | mask;
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gpioie = readb(pl061->base + GPIOIE) | mask;
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writeb(gpioie, pl061->base + GPIOIE);
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writeb(gpioie, pl061->base + GPIOIE);
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spin_unlock(&pl061->lock);
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raw_spin_unlock(&pl061->lock);
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}
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}
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/**
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/**
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@ -268,9 +268,9 @@ static void pl061_irq_ack(struct irq_data *d)
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struct pl061 *pl061 = gpiochip_get_data(gc);
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struct pl061 *pl061 = gpiochip_get_data(gc);
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u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
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u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
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spin_lock(&pl061->lock);
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raw_spin_lock(&pl061->lock);
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writeb(mask, pl061->base + GPIOIC);
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writeb(mask, pl061->base + GPIOIC);
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spin_unlock(&pl061->lock);
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raw_spin_unlock(&pl061->lock);
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}
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}
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static int pl061_irq_set_wake(struct irq_data *d, unsigned int state)
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static int pl061_irq_set_wake(struct irq_data *d, unsigned int state)
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@ -304,7 +304,7 @@ static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
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if (IS_ERR(pl061->base))
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if (IS_ERR(pl061->base))
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return PTR_ERR(pl061->base);
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return PTR_ERR(pl061->base);
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spin_lock_init(&pl061->lock);
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raw_spin_lock_init(&pl061->lock);
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if (of_property_read_bool(dev->of_node, "gpio-ranges")) {
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if (of_property_read_bool(dev->of_node, "gpio-ranges")) {
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pl061->gc.request = gpiochip_generic_request;
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pl061->gc.request = gpiochip_generic_request;
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pl061->gc.free = gpiochip_generic_free;
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pl061->gc.free = gpiochip_generic_free;
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